Lines Matching +full:tx +full:- +full:threshold
15 * 3. Neither the name of the author nor the names of any co-contributors
69 #define PCI_CMD_MWIE 0x0010 /* memory write-invalidate enable */
86 #define CSR_TSTAT 0x60 /* 10Base-T status */
88 #define CSR_TCTL 0x70 /* 10Base-T control */
92 #define CSR_TXBR 0x9c /* Transmit burst counter/time-out register */
101 #define PAR_MWIE 0x01000000U /* PCI memory-write-invalidate */
102 #define PAR_MRLE 0x00800000U /* PCI memory-read-line */
103 #define PAR_MRME 0x00200000U /* PCI memory-read-multiple */
107 #define PAR_TXAUTOPOLL 0x00060000U /* Programmable TX autopoll interval */
131 #define INT_100LINK 0x08000000U /* 100 Base-T link */
136 #define INT_10LINK 0x00001000U /* 10 Base-T link */
172 #define NAR_TR 0x0000c000U /* Transmit threshold mask */
173 #define NAR_TR_72 0x00000000U /* 72 B (128 @ 100Mbps) tx thresh */
174 #define NAR_TR_96 0x00004000U /* 96 B (256 @ 100Mbps) tx thresh */
175 #define NAR_TR_128 0x00008000U /* 128 B (512 @ 100Mbps) tx thresh */
176 #define NAR_TR_160 0x0000c000U /* 160 B (1K @ 100Mbsp) tx thresh */
179 #define NAR_SPEED 0x00400000U /* transmit threshold, set for 10bt */
223 #define TSTAT_10F 0x00000004U /* 10Base-T link failure */
224 #define TSTAT_100F 0x00000002U /* 100Base-T link failure */
248 #define TCTL_HDX 0x00000040U /* half-duplex enable */
256 #define FLOW_RESTART 0x00004000U /* re-start mode */
257 #define FLOW_RESTOP 0x00002000U /* re-stop mode */
258 #define FLOW_TXFCEN 0x00001000U /* tx flow control enable */
261 #define FLOW_STOPTX 0x00000200U /* tx flow status */
263 #define FLOW_RXFCTH1 0x00000080U /* rx flow threshold 1 */
264 #define FLOW_RXFCTH0 0x00000040U /* rx flow threshold 0 */