Lines Matching +full:0 +full:x62

64 #define IWN_HIADDR(paddr)	(((paddr) >> 32) & 0xf)
67 #define IWN_HIADDR(paddr)	(0)
76 #define IWN_HW_IF_CONFIG	0x000
77 #define IWN_INT_COALESCING	0x004
78 #define IWN_INT_PERIODIC	0x005	/* use IWN_WRITE_1 */
79 #define IWN_INT			0x008
80 #define IWN_INT_MASK		0x00c
81 #define IWN_FH_INT		0x010
82 #define IWN_RESET		0x020
83 #define IWN_GP_CNTRL		0x024
84 #define IWN_HW_REV		0x028
85 #define IWN_EEPROM		0x02c
86 #define IWN_EEPROM_GP		0x030
87 #define IWN_OTP_GP		0x034
88 #define IWN_GIO			0x03c
89 #define IWN_GP_DRIVER		0x050
90 #define IWN_UCODE_GP1_CLR	0x05c
91 #define IWN_LED			0x094
92 #define IWN_DRAM_INT_TBL	0x0a0
93 #define IWN_SHADOW_REG_CTRL	0x0a8
94 #define IWN_GIO_CHICKEN		0x100
95 #define IWN_ANA_PLL		0x20c
96 #define IWN_HW_REV_WA		0x22c
97 #define IWN_DBG_HPET_MEM	0x240
98 #define IWN_DBG_LINK_PWR_MGMT	0x250
99 #define IWN_MEM_RADDR		0x40c
100 #define IWN_MEM_WADDR		0x410
101 #define IWN_MEM_WDATA		0x418
102 #define IWN_MEM_RDATA		0x41c
103 #define IWN_PRPH_WADDR		0x444
104 #define IWN_PRPH_RADDR		0x448
105 #define IWN_PRPH_WDATA		0x44c
106 #define IWN_PRPH_RDATA		0x450
107 #define IWN_HBUS_TARG_WRPTR	0x460
112 #define IWN_FH_TFBD_CTRL0(qid)		(0x1900 + (qid) * 8)
113 #define IWN_FH_TFBD_CTRL1(qid)		(0x1904 + (qid) * 8)
114 #define IWN_FH_KW_ADDR			0x197c
115 #define IWN_FH_SRAM_ADDR(qid)		(0x19a4 + (qid) * 4)
116 #define IWN_FH_CBBC_QUEUE(qid)		(0x19d0 + (qid) * 4)
117 #define IWN_FH_STATUS_WPTR		0x1bc0
118 #define IWN_FH_RX_BASE			0x1bc4
119 #define IWN_FH_RX_WPTR			0x1bc8
120 #define IWN_FH_RX_CONFIG		0x1c00
121 #define IWN_FH_RX_STATUS		0x1c44
122 #define IWN_FH_TX_CONFIG(qid)		(0x1d00 + (qid) * 32)
123 #define IWN_FH_TXBUF_STATUS(qid)	(0x1d08 + (qid) * 32)
124 #define IWN_FH_TX_CHICKEN		0x1e98
125 #define IWN_FH_TX_STATUS		0x1eb0
130 #define IWN_SCHED_BASE			0xa02c00
131 #define IWN_SCHED_SRAM_ADDR		(IWN_SCHED_BASE + 0x000)
132 #define IWN5000_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x008)
133 #define IWN4965_SCHED_DRAM_ADDR		(IWN_SCHED_BASE + 0x010)
134 #define IWN5000_SCHED_TXFACT		(IWN_SCHED_BASE + 0x010)
135 #define IWN4965_SCHED_TXFACT		(IWN_SCHED_BASE + 0x01c)
136 #define IWN4965_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x064 + (qid) * 4)
137 #define IWN5000_SCHED_QUEUE_RDPTR(qid)	(IWN_SCHED_BASE + 0x068 + (qid) * 4)
138 #define IWN4965_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0d0)
139 #define IWN4965_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x0e4)
140 #define IWN5000_SCHED_QCHAIN_SEL	(IWN_SCHED_BASE + 0x0e8)
141 #define IWN4965_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x104 + (qid) * 4)
142 #define IWN5000_SCHED_INTR_MASK		(IWN_SCHED_BASE + 0x108)
143 #define IWN5000_SCHED_QUEUE_STATUS(qid)	(IWN_SCHED_BASE + 0x10c + (qid) * 4)
144 #define IWN5000_SCHED_AGGR_SEL		(IWN_SCHED_BASE + 0x248)
149 #define IWN4965_SCHED_CTX_OFF		0x380
151 #define IWN4965_SCHED_QUEUE_OFFSET(qid)	(0x380 + (qid) * 8)
152 #define IWN4965_SCHED_TRANS_TBL(qid)	(0x500 + (qid) * 2)
153 #define IWN5000_SCHED_CTX_OFF		0x600
155 #define IWN5000_SCHED_QUEUE_OFFSET(qid)	(0x600 + (qid) * 8)
156 #define IWN5000_SCHED_TRANS_TBL(qid)	(0x7e0 + (qid) * 2)
161 #define IWN_APMG_CLK_CTRL	0x3000
162 #define IWN_APMG_CLK_EN		0x3004
163 #define IWN_APMG_CLK_DIS	0x3008
164 #define IWN_APMG_PS		0x300c
165 #define IWN_APMG_DIGITAL_SVR	0x3058
166 #define IWN_APMG_ANALOG_SVR	0x306c
167 #define IWN_APMG_PCI_STT	0x3010
168 #define IWN_BSM_WR_CTRL		0x3400
169 #define IWN_BSM_WR_MEM_SRC	0x3404
170 #define IWN_BSM_WR_MEM_DST	0x3408
171 #define IWN_BSM_WR_DWCOUNT	0x340c
172 #define IWN_BSM_DRAM_TEXT_ADDR	0x3490
173 #define IWN_BSM_DRAM_TEXT_SIZE	0x3494
174 #define IWN_BSM_DRAM_DATA_ADDR	0x3498
175 #define IWN_BSM_DRAM_DATA_SIZE	0x349c
176 #define IWN_BSM_SRAM_BASE	0x3800
189 #define IWN_INT_PERIODIC_DIS	0x00
190 #define IWN_INT_PERIODIC_ENA	0xff
196 #define IWN_FW_TEXT_BASE	0x00000000
197 #define IWN_FW_DATA_BASE	0x00800000
200 #define IWN_RESET_NEVO			(1U << 0)
207 #define IWN_GP_CNTRL_MAC_ACCESS_ENA	(1 << 0)
208 #define IWN_GP_CNTRL_MAC_CLOCK_READY	(1 << 0)
216 #define IWN_HW_REV_TYPE_MASK	0x000001f0
217 #define IWN_HW_REV_TYPE_4965	0
240 #define IWN_GP_DRIVER_RADIO_3X3_HYB	(0 << 0)
241 #define IWN_GP_DRIVER_RADIO_2X2_HYB	(1 << 0)
242 #define IWN_GP_DRIVER_RADIO_2X2_IPA	(2 << 0)
254 #define IWN_LED_OFF		0x00000038
255 #define IWN_LED_ON		0x00000078
262 #define IWN_ANA_PLL_INIT	0x00880300
272 #define IWN_INT_ALIVE		(1 <<  0)
296 	(IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
298 	(IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
301 #define IWN_FH_TX_CONFIG_DMA_PAUSE		0
330 #define IWN_EEPROM_READ_VALID	(1 << 0)
334 #define IWN_EEPROM_GP_IF_OWNER	0x00000180
343 #define IWN4965_TXQ_STATUS_ACTIVE	0x0007fc01
344 #define IWN4965_TXQ_STATUS_INACTIVE	0x0007fc00
347 #define IWN5000_TXQ_STATUS_ACTIVE	0x00ff0018
348 #define IWN5000_TXQ_STATUS_INACTIVE	0x00ff0010
358 #define IWN_APMG_PS_PWR_SRC_VMAIN	0
364 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x)		(((x) & 0xf) << 5)
366 	IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
427 #define IWN_RX_NO_CRC_ERR	(1 <<  0)
470 #define IWN_ANT_A	(1 << 0)
494 #define IWN_RXCHAIN_DRIVER_FORCE	(1 << 0)
506 #define IWN_RXON_24GHZ		(1 <<  0)
518 #define IWN_FILTER_PROMISC	(1 << 0)
552 #define IWN_EDCA_UPDATE	(1 << 0)
577 #define IWN_NODE_UPDATE		(1 << 0)
584 #define IWN_ID_BSS		 0
589 #define IWN_FLAG_SET_KEY		(1 << 0)
660 #define IWN_TX_NEED_PROTECTION	(1 <<  0)	/* 5000 only */
691 #define IWN_LIFETIME_INFINITE	0xffffffff
740 #define IWN_WIMAX_COEX_STA_TABLE_VALID		(1 << 0)
778 #define IWN_PS_ALLOW_SLEEP	(1 << 0)
822 #define IWN_CHAN_ACTIVE		(1 << 0)
876 #define IWN_GOOD_CRC_TH_DISABLED	0
878 #define IWN_GOOD_CRC_TH_NEVER		htole16(0xffff)
896 #define IWN5000_TXPOWER_AUTO		0x7f
909 #define IWN_BT_COEX_CHAN_ANN	(1 << 0)
920 #define IWN_BT_KILL_ACK_MASK_DEF	htole32(0xffff0000)
922 #define IWN_BT_KILL_CTS_MASK_DEF	htole32(0xffff0000)
930 #define IWN_BT_BASIC_MODE_DISABLED	0
943 	uint16_t	reduce_txpower; /* bit 0 */
944 #if 0
953 			uint8_t		reduce_txpower; /* bit 0 */
960 #define IWN_BT_VALID_ENABLE_FLAGS	htole16(1 << 0)
981 #define IWN_BT_PRIO_BOOST_DEF	0xf0
990 #define IWN_BT_PRIO_BOOST_DEF32	0xf0f0f0
1032 #define IWN_SENSITIVITY_DEFAULTTBL	0
1159 #define IWN_MEASUREMENT_BASIC		(1 << 0)
1179 #define IWN_UCODE_RUNTIME	0
1320 #define IWN_MEASUREMENT_START	0
1337 #define IWN_MEASUREMENT_OK		0
1478 	uint32_t	zero;	/* Always 0, to differentiate from legacy. */
1480 #define IWN_FW_SIGNATURE	0x0a4c5749	/* "IWL\n" */
1484 #define IWN_FW_API(x)	(((x) >> 8) & 0xff)
1544 	IWN_UCODE_TLV_FLAGS_PAN			= (1 << 0),
1568 #define IWN_EEPROM_MAC		0x015
1569 #define IWN_EEPROM_SKU_CAP	0x045
1570 #define IWN_EEPROM_RFCFG	0x048
1571 #define IWN4965_EEPROM_DOMAIN	0x060
1572 #define IWN4965_EEPROM_BAND1	0x063
1573 #define IWN5000_EEPROM_REG	0x066
1574 #define IWN5000_EEPROM_CAL	0x067
1575 #define IWN4965_EEPROM_BAND2	0x072
1576 #define IWN4965_EEPROM_BAND3	0x080
1577 #define IWN4965_EEPROM_BAND4	0x08d
1578 #define IWN4965_EEPROM_BAND5	0x099
1579 #define IWN4965_EEPROM_BAND6	0x0a0
1580 #define IWN4965_EEPROM_BAND7	0x0a8
1581 #define IWN4965_EEPROM_MAXPOW	0x0e8
1582 #define IWN4965_EEPROM_VOLTAGE	0x0e9
1583 #define IWN4965_EEPROM_BANDS	0x0ea
1585 #define IWN5000_EEPROM_DOMAIN	0x001
1586 #define IWN5000_EEPROM_BAND1	0x004
1587 #define IWN5000_EEPROM_BAND2	0x013
1588 #define IWN5000_EEPROM_BAND3	0x021
1589 #define IWN5000_EEPROM_BAND4	0x02e
1590 #define IWN5000_EEPROM_BAND5	0x03a
1591 #define IWN5000_EEPROM_BAND6	0x041
1592 #define IWN5000_EEPROM_BAND7	0x049
1593 #define IWN6000_EEPROM_ENHINFO	0x054
1594 #define IWN5000_EEPROM_CRYSTAL	0x128
1595 #define IWN5000_EEPROM_TEMP	0x12a
1596 #define IWN5000_EEPROM_VOLT	0x12b
1597 #define IWN2000_EEPROM_RAWTEMP	0x12b
1605 #define IWN_RFCFG_TYPE(x)	(((x) >>  0) & 0x3)
1606 #define IWN_RFCFG_STEP(x)	(((x) >>  2) & 0x3)
1607 #define IWN_RFCFG_DASH(x)	(((x) >>  4) & 0x3)
1608 #define IWN_RFCFG_TXANTMSK(x)	(((x) >>  8) & 0xf)
1609 #define IWN_RFCFG_RXANTMSK(x)	(((x) >> 12) & 0xf)
1613 #define IWN_EEPROM_CHAN_VALID	(1 << 0)
1702 #define IWN_RIDX_CCK1	0
1714 	{  12, 0xd, 0 },
1715 	{  18, 0xf, 0 },
1716 	{  24, 0x5, 0 },
1717 	{  36, 0x7, 0 },
1718 	{  48, 0x9, 0 },
1719 	{  72, 0xb, 0 },
1720 	{  96, 0x1, 0 },
1721 	{ 108, 0x3, 0 },
1722 	{ 120, 0x3, 0 }
1732 	0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
1733 	0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
1734 	0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
1735 	0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
1736 	0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
1737 	0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
1738 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1739 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1740 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1741 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1745 	0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
1746 	0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
1747 	0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
1748 	0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
1749 	0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
1750 	0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
1751 	0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
1752 	0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
1753 	0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
1754 	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1762 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1763 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1764 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1765 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1766 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1767 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1768 	0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
1769 	0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
1770 	0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
1771 	0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
1775 	0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1776 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1777 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1778 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1779 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1780 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1781 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1782 	0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1783 	0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1784 	0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
1800 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
1801 	{ 200, 500, {  1,  2,  2,  2, -1 }, 0 },	/* PS level 1 */
1802 	{ 200, 300, {  1,  2,  2,  2, -1 }, 0 },	/* PS level 2 */
1803 	{  50, 100, {  2,  2,  2,  2, -1 }, 0 },	/* PS level 3 */
1809 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
1810 	{ 200, 500, {  1,  2,  3,  4,  4 }, 0 },	/* PS level 1 */
1811 	{ 200, 300, {  1,  2,  3,  4,  7 }, 0 },	/* PS level 2 */
1812 	{  50, 100, {  2,  4,  6,  7,  9 }, 0 },	/* PS level 3 */
1818 	{   0,   0, {  0,  0,  0,  0,  0 }, 0 },	/* CAM */
1819 	{ 200, 500, {  1,  2,  3,  4, -1 }, 0 },	/* PS level 1 */
1820 	{ 200, 300, {  2,  4,  6,  7, -1 }, 0 },	/* PS level 2 */
1821 	{  50, 100, {  2,  7,  9,  9, -1 }, 0 },	/* PS level 3 */
1822 	{  50,  25, {  2,  7,  9,  9, -1 }, 0 },	/* PS level 4 */
1823 	{  25,  25, {  4,  7, 10, 10, -1 }, 0 }		/* PS level 5 */
1923 	1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
1930 	{ 0x04, 0x03, 0x00, 0x00 },
1931 	{ 0x04, 0x03, 0x00, 0x03 },
1932 	{ 0x04, 0x03, 0x00, 0x03 },
1933 	{ 0x04, 0x03, 0x00, 0x03 },
1934 	{ 0x04, 0x03, 0x00, 0x00 },
1935 	{ 0x04, 0x03, 0x00, 0x07 },
1936 	{ 0x04, 0x03, 0x00, 0x00 },
1937 	{ 0x04, 0x03, 0x00, 0x03 },
1938 	{ 0x04, 0x03, 0x00, 0x03 },
1939 	{ 0x04, 0x03, 0x00, 0x00 },
1940 	{ 0x06, 0x03, 0x00, 0x07 },
1941 	{ 0x04, 0x03, 0x00, 0x00 },
1942 	{ 0x06, 0x06, 0x00, 0x03 },
1943 	{ 0x04, 0x03, 0x00, 0x07 },
1944 	{ 0x04, 0x03, 0x00, 0x00 },
1945 	{ 0x04, 0x03, 0x00, 0x00 }