Lines Matching refs:qid
1382 int qid, error; in iwn_detach() local
1443 for (qid = 0; qid < sc->ntxqs; qid++) in iwn_detach()
1444 iwn_free_tx_ring(sc, &sc->txq[qid]); in iwn_detach()
1977 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) in iwn_alloc_tx_ring() argument
1983 ring->qid = qid; in iwn_alloc_tx_ring()
2002 if (qid > 4) in iwn_alloc_tx_ring()
2043 if (ring->qid < 4) in iwn_reset_tx_ring()
2054 sc->qfullmsk &= ~(1 << ring->qid); in iwn_reset_tx_ring()
2762 txq = &sc->txq[le16toh(ba->qid)]; in iwn_rx_compressed_ba()
2909 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); in iwn5000_tx_done()
2924 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; in iwn_tx_done()
2944 sc->qfullmsk &= ~(1 << ring->qid); in iwn_tx_done()
2960 if ((desc->qid & 0xf) != IWN_CMD_QUEUE_NUM) in iwn_cmd_done()
3006 if (!(desc->qid & 0x80)) /* Reply to a command. */ in iwn_notif_intr()
3205 int qid; in iwn_wakeup_intr() local
3211 for (qid = 0; qid < sc->ntxqs; qid++) { in iwn_wakeup_intr()
3212 struct iwn_tx_ring *ring = &sc->txq[qid]; in iwn_wakeup_intr()
3213 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); in iwn_wakeup_intr()
3278 i, ring->qid, ring->cur, ring->queued); in iwn_fatal_intr()
3405 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, in iwn4965_update_sched() argument
3409 int w_idx = qid * IWN4965_SCHED_COUNT + idx; in iwn4965_update_sched()
3424 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, in iwn5000_update_sched() argument
3427 int w_idx = qid * IWN5000_SCHED_COUNT + idx; in iwn5000_update_sched()
3443 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) in iwn5000_reset_sched() argument
3445 int w_idx = qid * IWN5000_SCHED_COUNT + idx; in iwn5000_reset_sched()
3823 cmd->qid = ring->qid; in iwn_send()
3943 DTRACE_PROBE4(tx, int, ring->qid, int, ring->cur, size_t, MBLKL(mp), in iwn_send()
3972 sc->ops.update_sched(sc, ring->qid, ring->cur, tx->id, totlen); in iwn_send()
3976 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); in iwn_send()
3980 sc->qfullmsk |= 1 << ring->qid; in iwn_send()
4432 cmd->qid = ring->qid; in iwn_cmd()
4455 sc->ops.update_sched(sc, ring->qid, ring->cur, 0, 0); in iwn_cmd()
4459 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); in iwn_cmd()
6248 int qid = 7 + tid; in iwn4965_ampdu_tx_start() local
6251 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), in iwn4965_ampdu_tx_start()
6255 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), in iwn4965_ampdu_tx_start()
6259 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); in iwn4965_ampdu_tx_start()
6262 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); in iwn4965_ampdu_tx_start()
6263 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); in iwn4965_ampdu_tx_start()
6266 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), in iwn4965_ampdu_tx_start()
6269 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, in iwn4965_ampdu_tx_start()
6273 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); in iwn4965_ampdu_tx_start()
6276 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), in iwn4965_ampdu_tx_start()
6284 int qid = 7 + tid; in iwn4965_ampdu_tx_stop() local
6287 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), in iwn4965_ampdu_tx_stop()
6291 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); in iwn4965_ampdu_tx_stop()
6292 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); in iwn4965_ampdu_tx_stop()
6295 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); in iwn4965_ampdu_tx_stop()
6298 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), in iwn4965_ampdu_tx_stop()
6307 int qid = 10 + tid; in iwn5000_ampdu_tx_start() local
6310 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), in iwn5000_ampdu_tx_start()
6314 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), in iwn5000_ampdu_tx_start()
6318 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); in iwn5000_ampdu_tx_start()
6321 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); in iwn5000_ampdu_tx_start()
6324 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); in iwn5000_ampdu_tx_start()
6325 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); in iwn5000_ampdu_tx_start()
6328 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, in iwn5000_ampdu_tx_start()
6332 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); in iwn5000_ampdu_tx_start()
6335 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), in iwn5000_ampdu_tx_start()
6342 int qid = 10 + tid; in iwn5000_ampdu_tx_stop() local
6345 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), in iwn5000_ampdu_tx_stop()
6349 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); in iwn5000_ampdu_tx_stop()
6352 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); in iwn5000_ampdu_tx_stop()
6353 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); in iwn5000_ampdu_tx_stop()
6356 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); in iwn5000_ampdu_tx_stop()
6359 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), in iwn5000_ampdu_tx_stop()
6491 int error, qid; in iwn4965_post_alive() local
6509 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { in iwn4965_post_alive()
6510 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); in iwn4965_post_alive()
6511 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); in iwn4965_post_alive()
6515 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); in iwn4965_post_alive()
6518 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, in iwn4965_post_alive()
6528 for (qid = 0; qid < 7; qid++) { in iwn4965_post_alive()
6530 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), in iwn4965_post_alive()
6531 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); in iwn4965_post_alive()
6544 int error, qid; in iwn5000_post_alive() local
6566 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { in iwn5000_post_alive()
6567 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); in iwn5000_post_alive()
6568 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); in iwn5000_post_alive()
6571 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); in iwn5000_post_alive()
6574 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, in iwn5000_post_alive()
6584 for (qid = 0; qid < 7; qid++) { in iwn5000_post_alive()
6586 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), in iwn5000_post_alive()
6587 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); in iwn5000_post_alive()
7290 int error, chnl, qid; in iwn_hw_init() local
7349 for (qid = 0; qid < sc->ntxqs; qid++) { in iwn_hw_init()
7350 struct iwn_tx_ring *txq = &sc->txq[qid]; in iwn_hw_init()
7353 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), in iwn_hw_init()
7405 int chnl, qid, ntries; in iwn_hw_stop() local
7443 for (qid = 0; qid < sc->ntxqs; qid++) in iwn_hw_stop()
7444 iwn_reset_tx_ring(sc, &sc->txq[qid]); in iwn_hw_stop()