1300 		if (IWK_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24))  in iwk_reset_rx_ring()
1440 		if (IWK_READ(sc, IWK_FH_TSSR_TX_STATUS_REG) &  in iwk_reset_tx_ring()
1948 	tmp = IWK_READ(sc, CSR_GP_CNTRL);  in iwk_mac_access_enter()
1954 		if ((IWK_READ(sc, CSR_GP_CNTRL) &  in iwk_mac_access_enter()
1971 	uint32_t tmp = IWK_READ(sc, CSR_GP_CNTRL);  in iwk_mac_access_exit()
1980 	return (IWK_READ(sc, HBUS_TARG_MEM_RDAT));  in iwk_mem_read()
1994 	return (IWK_READ(sc, HBUS_TARG_PRPH_RDAT));  in iwk_reg_read()
2485 	r = IWK_READ(sc, CSR_INT);  in iwk_intr()
2493 	rfh = IWK_READ(sc, CSR_FH_INT_STATUS);  in iwk_intr()
2525 		uint32_t tmp = IWK_READ(sc, CSR_GP_CNTRL);  in iwk_intr()
3309 		tmp = IWK_READ(sc, CSR_GP_CNTRL);  in iwk_thread()
3945 	tmp = IWK_READ(sc, CSR_RESET);  in iwk_stop_master()
3948 	tmp = IWK_READ(sc, CSR_GP_CNTRL);  in iwk_stop_master()
3954 		if (IWK_READ(sc, CSR_RESET) &  in iwk_stop_master()
3990 	tmp = IWK_READ(sc, CSR_GIO_CHICKEN_BITS);  in iwk_preinit()
3994 	tmp = IWK_READ(sc, CSR_GP_CNTRL);  in iwk_preinit()
3999 		if (IWK_READ(sc, CSR_GP_CNTRL) &  in iwk_preinit()
4038 	tmp = IWK_READ(sc, CSR_SW_VER);  in iwk_preinit()
4066 		tmp = IWK_READ(sc, CSR_HW_IF_CONFIG_REG);  in iwk_eep_sem_down()
4071 			if (IWK_READ(sc, CSR_HW_IF_CONFIG_REG) &  in iwk_eep_sem_down()
4087 	tmp = IWK_READ(sc, CSR_HW_IF_CONFIG_REG);  in iwk_eep_sem_up()
4104 	eep_gp = IWK_READ(sc, CSR_EEPROM_GP);  in iwk_eep_load()
4119 		tmp = IWK_READ(sc, CSR_EEPROM_REG);  in iwk_eep_load()
4123 			rv = IWK_READ(sc, CSR_EEPROM_REG);  in iwk_eep_load()
4169 	tmp = IWK_READ(sc, CSR_GP_CNTRL);  in iwk_init()
4318 	tmp = IWK_READ(sc, CSR_RESET);  in iwk_stop()