Lines Matching +full:tx +full:- +full:threshold

49  * Maximum number of RX and TX rings that it appears the hardware supports. The
63  * These are the default auto-negotiation values the device supports which is
78  * threshold for rx mostly by surveying others. For tx, we picked 512 as that's
89  * These numbers deal with the tx ring, blocking, recycling, and notification
95  * than 1% of the default ring size.  We picked a default recycle threshold
96  * check during tx of 32, which is about 6.25% of the default ring size.
116  * 4-byte aligned.
121  * The buffer sizes that hardware uses for rx and tx are required to be 1 KiB
130 #define	IGC_RX_POLL_INTR	-1
143 #define	IGC_DMA_SYNC(buf, flag)		ASSERT0(ddi_dma_sync((buf)->idb_hdl, \
146 #define	IGC_DMA_SYNC(buf, flag)		(void) ddi_dma_sync((buf)->idb_hdl, \
170  * Hardware-specific limits.
224 	 * just which single MSI-X it has.
268 	 * This flag indicates that this is the first tx buffer for a packet and
269 	 * therefore its last descriptor for the packet is valid. See 'TX Data
274 	 * When set to true this tx buffer is being used to represent DMA
290  * This represents data that we have saved and goes into the tx context
330 	 * Data for the TX descriptors.
439 	 * Limits and device-specific data. All data in this section after the