113 static void dEISA_setchain(ddi_dma_cookie_t *cp, int chnl);
154 d37A_dma_valid(int chnl)  in d37A_dma_valid()  argument
157 	if (chnl == 4)  in d37A_dma_valid()
171 d37A_dma_release(int chnl)  in d37A_dma_release()  argument
174 	if (chnl == 4)  in d37A_dma_release()
177 	d37A_chnl_mode[chnl] = DMAE_TRANS_SNGL;  in d37A_dma_release()
188 d37A_dma_disable(int chnl)  in d37A_dma_disable()  argument
191 	    chnl, chan_addr[chnl].mask_reg));  in d37A_dma_disable()
193 	outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK);  in d37A_dma_disable()
206 d37A_dma_enable(int chnl)  in d37A_dma_enable()  argument
209 	    chnl, chan_addr[chnl].mask_reg, chnl & 3));  in d37A_dma_enable()
212 	outb(chan_addr[chnl].mask_reg, chnl & 3);  in d37A_dma_enable()
241 	int chnl, istate, nstate;  in d37A_intr()  local
246 		chnl = 0;  in d37A_intr()
251 				dEISA_setchain(d37A_next_cookie[chnl], chnl);  in d37A_intr()
253 				if (chnl < 4)  in d37A_intr()
254 					mask = inb(DMAC1_ALLMASK) >> (chnl);  in d37A_intr()
256 					mask = inb(DMAC2_ALLMASK) >> (chnl - 4);  in d37A_intr()
258 prom_printf("eisa: dma buffer chaining failure chnl %d!\n", chnl);  in d37A_intr()
262 			chnl++;  in d37A_intr()
265 		chnl = 0;  in d37A_intr()
267 			if ((nstate & 1) && d37A_next_cookie[chnl])  in d37A_intr()
268 				d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);  in d37A_intr()
269 			chnl++;  in d37A_intr()
288 dEISA_setchain(ddi_dma_cookie_t *cp, int chnl)  in dEISA_setchain()  argument
292 		    chnl, cp->dmac_address, cp->dmac_size));  in dEISA_setchain()
293 		(void) d37A_write_addr(cp->dmac_address, chnl);  in dEISA_setchain()
294 		(void) d37A_write_count(cp->dmac_size, chnl);  in dEISA_setchain()
295 		outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK);  in dEISA_setchain()
300 		outb(chan_addr[chnl].scm_reg, chnl);  in dEISA_setchain()
301 		dprintf(("dEISA_setchain: chnl=%d end\n", chnl));  in dEISA_setchain()
316 d37A_prog_chan(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl)  in d37A_prog_chan()  argument
318 	if (d37A_chnl_mode[chnl] == DMAE_TRANS_CSCD) {  in d37A_prog_chan()
320 		    chnl));  in d37A_prog_chan()
331 	    chnl, (void *)dmaereqp));  in d37A_prog_chan()
334 		switch (chnl) {  in d37A_prog_chan()
342 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));  in d37A_prog_chan()
357 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));  in d37A_prog_chan()
364 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));  in d37A_prog_chan()
368 		chnl &= 3;  in d37A_prog_chan()
371 	d37A_dma_disable(chnl);  in d37A_prog_chan()
373 		(void) d37A_set_mode(dmaereqp, chnl);  in d37A_prog_chan()
376 		(void) d37A_write_addr(cp->dmac_address, chnl);  in d37A_prog_chan()
377 		(void) d37A_write_count(cp->dmac_size, chnl);  in d37A_prog_chan()
381 		    (d37A_next_cookie[chnl] = _dmae_nxcookie(chnl))) {  in d37A_prog_chan()
387 			outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);  in d37A_prog_chan()
389 			dEISA_setchain(d37A_next_cookie[chnl], chnl);  in d37A_prog_chan()
390 			d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);  in d37A_prog_chan()
408 d37A_dma_swsetup(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl)  in d37A_dma_swsetup()  argument
410 	if (d37A_chnl_mode[chnl] == DMAE_TRANS_CSCD) {  in d37A_dma_swsetup()
412 		    chnl));  in d37A_dma_swsetup()
417 	    chnl, (void *)dmaereqp));  in d37A_dma_swsetup()
423 	switch (chnl) {  in d37A_dma_swsetup()
430 dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));  in d37A_dma_swsetup()
444 dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));  in d37A_dma_swsetup()
451 		dprintf(("d37A_dma_swsetup err: chnl %d not set up.\n", chnl));  in d37A_dma_swsetup()
457 	d37A_dma_disable(chnl);  in d37A_dma_swsetup()
458 	(void) d37A_set_mode(dmaereqp, chnl);  in d37A_dma_swsetup()
460 	(void) d37A_write_addr(cp->dmac_address, chnl);  in d37A_dma_swsetup()
461 	(void) d37A_write_count(cp->dmac_size, chnl);  in d37A_dma_swsetup()
465 	    (d37A_next_cookie[chnl] = _dmae_nxcookie(chnl))) {  in d37A_dma_swsetup()
470 		outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);  in d37A_dma_swsetup()
471 		dEISA_setchain(d37A_next_cookie[chnl], chnl);  in d37A_dma_swsetup()
472 		d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);  in d37A_dma_swsetup()
488 d37A_dma_swstart(int chnl)  in d37A_dma_swstart()  argument
490 	dprintf(("d37A_dma_swstart: chnl=%d\n", chnl));  in d37A_dma_swstart()
493 	d37A_dma_enable(chnl);  in d37A_dma_swstart()
494 	outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */  in d37A_dma_swstart()
507 d37A_dma_stop(int chnl)  in d37A_dma_stop()  argument
509 	dprintf(("d37A_dma_stop: chnl=%d\n", chnl));  in d37A_dma_stop()
512 	d37A_dma_disable(chnl);  in d37A_dma_stop()
513 	outb(chan_addr[chnl].reqt_reg, chnl & 3);    /* reset request bit */  in d37A_dma_stop()
526 d37A_get_chan_stat(int chnl, ulong_t *addressp, int *countp)  in d37A_get_chan_stat()  argument
532 	taddr = d37A_read_addr(chnl);  in d37A_get_chan_stat()
533 	tcount = d37A_read_count(chnl);  in d37A_get_chan_stat()
540 	    chnl, taddr, tcount));  in d37A_get_chan_stat()
553 d37A_set_mode(struct ddi_dmae_req *dmaereqp, int chnl)  in d37A_set_mode()  argument
561 	mode = chnl & 3;  in d37A_set_mode()
601 	d37A_chnl_mode[chnl] = dmaereqp->der_trans;  in d37A_set_mode()
604 	    chnl, chan_addr[chnl].mode_reg, mode));  in d37A_set_mode()
605 	outb(chan_addr[chnl].mode_reg, mode);  in d37A_set_mode()
609 	emode = chnl & 3;  in d37A_set_mode()
610 	d37A_chnl_path[chnl] = dmaereqp->der_path;  in d37A_set_mode()
626 		switch (chnl) {  in d37A_set_mode()
631 			d37A_chnl_path[chnl] = DMAE_PATH_8;  in d37A_set_mode()
637 			d37A_chnl_path[chnl] = DMAE_PATH_16;  in d37A_set_mode()
643 	outb(chan_addr[chnl].emode_reg, emode);  in d37A_set_mode()
646 	    chnl, chan_addr[chnl].emode_reg, emode));  in d37A_set_mode()
661 d37A_write_addr(ulong_t paddress, int chnl)  in d37A_write_addr()  argument
665 	dprintf(("d37A_write_addr: chnl=%d address=%lx\n", chnl, paddress));  in d37A_write_addr()
667 	switch (d37A_chnl_path[chnl]) {  in d37A_write_addr()
687 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_write_addr()
690 	outb(chan_addr[chnl].addr_reg, adr_byte[0]);  in d37A_write_addr()
691 	outb(chan_addr[chnl].addr_reg, adr_byte[1]);  in d37A_write_addr()
692 	outb(chan_addr[chnl].page_reg, adr_byte[2]);  in d37A_write_addr()
694 	outb(chan_addr[chnl].hpage_reg, adr_byte[3]);  in d37A_write_addr()
711 d37A_read_addr(int chnl)  in d37A_read_addr()  argument
718 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_read_addr()
720 	adr_byte[0] = inb(chan_addr[chnl].addr_reg);  in d37A_read_addr()
721 	adr_byte[1] = inb(chan_addr[chnl].addr_reg);  in d37A_read_addr()
722 	adr_byte[2] = inb(chan_addr[chnl].page_reg);  in d37A_read_addr()
724 	adr_byte[3] = inb(chan_addr[chnl].hpage_reg);  in d37A_read_addr()
729 	switch (d37A_chnl_path[chnl]) {  in d37A_read_addr()
749 	dprintf(("d37A_read_addr: chnl=%d address=%lx.\n", chnl, paddress));  in d37A_read_addr()
763 d37A_write_count(long count, int chnl)  in d37A_write_count()  argument
767 	dprintf(("d37A_write_count: chnl=%d count=0x%lx\n", chnl, count));  in d37A_write_count()
769 	switch (d37A_chnl_path[chnl]) {  in d37A_write_count()
787 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_write_count()
790 	outb(chan_addr[chnl].cnt_reg, count_byte[0]);  in d37A_write_count()
791 	outb(chan_addr[chnl].cnt_reg, count_byte[1]);  in d37A_write_count()
793 	outb(chan_addr[chnl].hcnt_reg, count_byte[2]);  in d37A_write_count()
810 d37A_read_count(int chnl)  in d37A_read_count()  argument
817 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_read_count()
819 	count_byte[0] = inb(chan_addr[chnl].cnt_reg);  in d37A_read_count()
820 	count_byte[1] = inb(chan_addr[chnl].cnt_reg);  in d37A_read_count()
822 	count_byte[2] = inb(chan_addr[chnl].hcnt_reg);  in d37A_read_count()
834 	switch (d37A_chnl_path[chnl]) {  in d37A_read_count()
848 	dprintf(("d37A_read_count: chnl=%d count=0x%lx\n", chnl, count));  in d37A_read_count()