241 i40e_intr_io_enable(i40e_t *i40e, int vector)  in i40e_intr_io_enable()  argument
246 	ASSERT3S(vector, >, 0);  in i40e_intr_io_enable()
250 	I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);  in i40e_intr_io_enable()
254 i40e_intr_io_disable(i40e_t *i40e, int vector)  in i40e_intr_io_disable()  argument
259 	ASSERT3S(vector, >, 0);  in i40e_intr_io_disable()
261 	I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);  in i40e_intr_io_disable()
386 i40e_set_lnklstn(i40e_t *i40e, uint_t vector, uint_t queue)  in i40e_set_lnklstn()  argument
394 	I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(vector), reg);  in i40e_set_lnklstn()
395 	DEBUGOUT2("PFINT_LNKLSTN[%u] = 0x%x", vector, reg);  in i40e_set_lnklstn()
405 i40e_set_rqctl(i40e_t *i40e, uint_t vector, uint_t queue)  in i40e_set_rqctl()  argument
410 	ASSERT3U(vector, ==, i40e->i40e_trqpairs[queue].itrq_rx_intrvec);  in i40e_set_rqctl()
412 	reg = (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |  in i40e_set_rqctl()
427 i40e_set_tqctl(i40e_t *i40e, uint_t vector, uint_t queue, uint_t next_queue)  in i40e_set_tqctl()  argument
432 	ASSERT3U(vector, ==, i40e->i40e_trqpairs[queue].itrq_tx_intrvec);  in i40e_set_tqctl()
434 	reg = (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |  in i40e_set_tqctl()