Lines Matching refs:cfg
91 tdc_tdr_cfg_t cfg; in hpi_txdma_channel_control() local
102 cfg.value = 0; in hpi_txdma_channel_control()
103 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
104 cfg.bits.reset = 1; in hpi_txdma_channel_control()
105 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
109 cfg.value = 0; in hpi_txdma_channel_control()
110 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
111 cfg.bits.enable = 1; in hpi_txdma_channel_control()
112 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
120 cfg.value = 0; in hpi_txdma_channel_control()
121 cfg.bits.reset = 1; in hpi_txdma_channel_control()
122 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
127 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
128 cfg.bits.enable = 1; in hpi_txdma_channel_control()
129 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
134 TXDMA_REG_READ64(handle, TDC_TDR_CFG, channel, &cfg.value); in hpi_txdma_channel_control()
135 cfg.bits.enable = 0; in hpi_txdma_channel_control()
136 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()