341 #define	ENAHW_AENQ_DESC_PHASE(desc)		\  argument
342 	((desc)->ead_flags & ENAHW_AENQ_DESC_PHASE_MASK)
437 #define	ENAHW_GET_FEAT_FLAGS_GET_CURR_VAL(desc)		\  argument
438 	((desc)->ecgf_comm.efc_flags) |= 0x1
439 #define	ENAHW_GET_FEAT_FLAGS_GET_DEF_VAL(desc)		\  argument
440 	((desc)->ecgf_comm.efc_flags) |= 0x3
837 #define	ENAHW_CMD_ID(desc, id)					\  argument
838 	(((desc)->ecd_cmd_id) |= ((id) & ENAHW_CMD_ID_MASK))
1337 #define	ENAHW_RESP_CMD_ID(desc)				\  argument
1338 	(((desc)->erd_cmd_id) & ENAHW_RESP_CMD_ID_MASK)
1599 #define	ENAHW_TX_DESC_LENGTH(desc, len)					\  argument
1600 	(((desc)->etd_len_ctrl) |= ((len) & ENAHW_TX_DESC_LENGTH_MASK))
1602 #define	ENAHW_TX_DESC_FIRST_ON(desc)				\  argument
1603 	(((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_FIRST_MASK)
1605 #define	ENAHW_TX_DESC_FIRST_OFF(desc)				\  argument
1606 	(((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_FIRST_MASK)
1608 #define	ENAHW_TX_DESC_REQID_HI(desc, reqid)				\  argument
1609 	(((desc)->etd_len_ctrl) |=					\
1613 #define	ENAHW_TX_DESC_REQID_LO(desc, reqid)				\  argument
1614 	(((desc)->etd_meta_ctrl) |=					\
1618 #define	ENAHW_TX_DESC_PHASE(desc, phase)				\  argument
1619 	(((desc)->etd_len_ctrl) |= (((phase) << ENAHW_TX_DESC_PHASE_SHIFT) & \
1622 #define	ENAHW_TX_DESC_LAST_ON(desc)				\  argument
1623 	(((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_LAST_MASK)
1625 #define	ENAHW_TX_DESC_LAST_OFF(desc)				\  argument
1626 	(((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_LAST_MASK)
1628 #define	ENAHW_TX_DESC_COMP_REQ_ON(desc)				\  argument
1629 	(((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_COMP_REQ_MASK)
1631 #define	ENAHW_TX_DESC_COMP_REQ_OFF(desc)				\  argument
1632 	(((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_COMP_REQ_MASK)
1634 #define	ENAHW_TX_DESC_META_DESC_ON(desc)				\  argument
1635 	(((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_META_DESC_MASK)
1637 #define	ENAHW_TX_DESC_META_DESC_OFF(desc)				\  argument
1638 	(((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_META_DESC_MASK)
1640 #define	ENAHW_TX_DESC_ADDR_LO(desc, addr)	\  argument
1641 	(((desc)->etd_buff_addr_lo) = (addr))
1643 #define	ENAHW_TX_DESC_ADDR_HI(desc, addr)				\  argument
1644 	(((desc)->etd_buff_addr_hi_hdr_sz) |=				\
1647 #define	ENAHW_TX_DESC_HEADER_LENGTH(desc, len)			\  argument
1648 	(((desc)->etd_buff_addr_hi_hdr_sz) |=			\
1652 #define	ENAHW_TX_DESC_DF_ON(desc)				\  argument
1653 	((desc)->etd_meta_ctrl |= ENAHW_TX_DESC_DF_MASK)
1655 #define	ENAHW_TX_DESC_TSO_OFF(desc)				\  argument
1656 	(((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_TSO_EN_MASK)
1658 #define	ENAHW_TX_DESC_L3_CSUM_OFF(desc)				\  argument
1659 	(((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L3_CSUM_EN_MASK)
1661 #define	ENAHW_TX_DESC_L4_CSUM_OFF(desc)				\  argument
1662 	(((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L4_CSUM_EN_MASK)
1664 #define	ENAHW_TX_DESC_L4_CSUM_PARTIAL_ON(desc)				\  argument
1665 	(((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L4_CSUM_PARTIAL_MASK)
1814 #define	ENAHW_RX_DESC_CLEAR_CTRL(desc)	((desc)->erd_ctrl = 0)  argument
1815 #define	ENAHW_RX_DESC_SET_PHASE(desc, val)				\  argument
1816 	((desc)->erd_ctrl |= ((val) & ENAHW_RX_DESC_PHASE_MASK))
1818 #define	ENAHW_RX_DESC_SET_FIRST(desc)			\  argument
1819 	((desc)->erd_ctrl |= ENAHW_RX_DESC_FIRST_MASK)
1821 #define	ENAHW_RX_DESC_SET_LAST(desc)			\  argument
1822 	((desc)->erd_ctrl |= ENAHW_RX_DESC_LAST_MASK)
1824 #define	ENAHW_RX_DESC_SET_COMP_REQ(desc)			\  argument
1825 	((desc)->erd_ctrl |= ENAHW_RX_DESC_COMP_REQ_MASK)
1928 #define	ENAHW_RX_CDESC_L3_PROTO(desc)				\  argument
1929 	((desc)->erc_status & ENAHW_RX_CDESC_L3_PROTO_MASK)
1931 #define	ENAHW_RX_CDESC_L3_CSUM_ERR(desc)				\  argument
1932 	((((desc)->erc_status & ENAHW_RX_CDESC_L3_CSUM_ERR_MASK) >>	\
1935 #define	ENAHW_RX_CDESC_L4_PROTO(desc)				\  argument
1936 	(((desc)->erc_status & ENAHW_RX_CDESC_L4_PROTO_MASK) >>	\
1939 #define	ENAHW_RX_CDESC_L4_CSUM_CHECKED(desc)				\  argument
1940 	((((desc)->erc_status & ENAHW_RX_CDESC_L4_CSUM_CHECKED_MASK) >>	\
1943 #define	ENAHW_RX_CDESC_L4_CSUM_ERR(desc)				\  argument
1944 	((((desc)->erc_status & ENAHW_RX_CDESC_L4_CSUM_ERR_MASK) >>	\
1947 #define	ENAHW_RX_CDESC_PHASE(desc)			 \  argument
1948 	(((desc)->erc_status & ENAHW_RX_CDESC_PHASE_MASK) >> \
1951 #define	ENAHW_RX_CDESC_FIRST(desc)			 \  argument
1952 	((((desc)->erc_status & ENAHW_RX_CDESC_FIRST_MASK) >> \
1955 #define	ENAHW_RX_CDESC_LAST(desc)			 \  argument
1956 	((((desc)->erc_status & ENAHW_RX_CDESC_LAST_MASK) >> \