20 ena_hw_bar_read32(const ena_t *ena, const uint16_t offset)  in ena_hw_bar_read32()  argument
22 	caddr_t addr = ena->ena_reg_base + offset;  in ena_hw_bar_read32()
23 	return (ena_hw_abs_read32(ena, (uint32_t *)addr));  in ena_hw_bar_read32()
27 ena_hw_abs_read32(const ena_t *ena, uint32_t *addr)  in ena_hw_abs_read32()  argument
29 	VERIFY3U(addr, >=, ena->ena_reg_base);  in ena_hw_abs_read32()
30 	VERIFY3U(addr, <, ena->ena_reg_base + (ena->ena_reg_size - 4));  in ena_hw_abs_read32()
32 	return (ddi_get32(ena->ena_reg_hdl, addr));  in ena_hw_abs_read32()
36 ena_hw_bar_write32(const ena_t *ena, const uint16_t offset, const uint32_t val)  in ena_hw_bar_write32()  argument
38 	caddr_t addr = ena->ena_reg_base + offset;  in ena_hw_bar_write32()
39 	ena_hw_abs_write32(ena, (uint32_t *)addr, val);  in ena_hw_bar_write32()
43 ena_hw_abs_write32(const ena_t *ena, uint32_t *addr, const uint32_t val)  in ena_hw_abs_write32()  argument
45 	VERIFY3P(ena, !=, NULL);  in ena_hw_abs_write32()
47 	VERIFY3U(addr, >=, ena->ena_reg_base);  in ena_hw_abs_write32()
48 	VERIFY3U(addr, <, ena->ena_reg_base + (ena->ena_reg_size - 4));  in ena_hw_abs_write32()
50 	ddi_put32(ena->ena_reg_hdl, addr, val);  in ena_hw_abs_write32()
54 enahw_resp_status_to_errno(ena_t *ena, enahw_resp_status_t status)  in enahw_resp_status_to_errno()  argument
87 		ena_err(ena, "unexpected status code: %d", status);  in enahw_resp_status_to_errno()
257 ena_update_regcache(ena_t *ena)  in ena_update_regcache()  argument
260 		ena_reg_t *r = &ena->ena_reg[i];  in ena_update_regcache()
262 		r->er_value = ena_hw_bar_read32(ena, r->er_offset);  in ena_update_regcache()
267 ena_init_regcache(ena_t *ena)  in ena_init_regcache()  argument
269 	bcopy(reg_cache_template, ena->ena_reg, sizeof (ena->ena_reg));  in ena_init_regcache()
270 	ena_update_regcache(ena);  in ena_init_regcache()