Lines Matching +full:tx +full:- +full:threshold

76 #define	CSR_NVCTL	0x10	/* Non-volatile Control Register */
116 #define	CSR_PRCPTHR	0xB0	/* PCI Receive Copy Threshold Register */
126 #define	CSR_ETXTHR	0xDC	/* PCI Early Transmit Threshold Register */
141 #define	COMMAND_TXQUEUED	(1UL << 2)	/* Queue TX Descriptor */
144 #define	COMMAND_STOP_TDMA	(1UL << 5)	/* Stop TX DMA */
159 #define	INTSTAT_RCT	(1UL << 11)	/* Receive Copy Threshold */
169 #define	INTSTAT_RCTS	(1UL << 22)	/* Receive Copy Threshold Status */
187 #define	INTMASK_RCT	(1UL << 11)	/* Receive Copy Threshold */
200 #define	GENCTL_RFT_32	(0UL << 8)	/* Receive FIFO Threshold (1/4) */
201 #define	GENCTL_RFT_64	(1UL << 8)	/* Receive FIFO Threshold (1/2) */
202 #define	GENCTL_RFT_96	(2UL << 8)	/* Receive FIFO Threshold (3/4) */
203 #define	GENCTL_RFT_128	(3UL << 8)	/* Receive FIFO Threshold (FULL) */
226 #define	NVCTL_IPG_DLY	7		/* Inter-packet Gap Timer Delay */
251 #define	MMCFG_STXC	(1UL << 14)	/* Select TX Clock */
252 #define	MMCFG_SNTXC	(1UL << 15)	/* Set No TX Clock */
291 #define	TXSTAT_ND	(1UL << 1)	/* Non-deferred Transmission */
294 #define	TXSTAT_UFLO	(1UL << 4)	/* TX Underrun */
313 	ddi_get32((efep)->efe_regs_acch, \
314 	    (efep)->efe_regs + ((reg) / sizeof (uint32_t)))
317 	ddi_put32((efep)->efe_regs_acch, \
318 	    (efep)->efe_regs + ((reg) / sizeof (uint32_t)), (val))
332 #define	DESCADDR(rp, x)		((rp)->r_dmac.dmac_address + DESCSZ(x))
333 #define	DESCLEN(rp)		((rp)->r_len)
335 #define	BUFADDR(bp)		((bp)->b_dmac.dmac_address)
336 #define	BUFLEN(bp)		((bp)->b_len)
338 #define	NEXTDESC(rp, x)		(((x) + 1) % (rp)->r_len)
341 #define	GETDESC(rp, x) 		(&(rp)->r_descp[(x)])
344 	ddi_get16((rp)->r_acch, (addr))
347 	ddi_put16((rp)->r_acch, (addr), (val))
350 	ddi_get32((rp)->r_acch, (addr))
353 	ddi_put32((rp)->r_acch, (addr), (val))
356 	(void) ddi_dma_sync((rp)->r_dmah, DESCSZ(x), \
359 #define	GETBUF(rp, x)		((rp)->r_bufpp[(x)])
362 	(void) ddi_dma_sync((bp)->b_dmah, 0, (bp)->b_len, (type))