Lines Matching full:receive

83 #define	CSR_RXFIFO	0x2C	/* Receive FIFO Contents */
96 #define	CSR_RXCON	0x60	/* Receive Control Register */
97 #define	CSR_RXSTAT	0x64	/* Receive Status Register */
98 #define	CSR_RXCNT	0x68	/* Receive Byte Count */
99 #define	CSR_RXTEST	0x6C	/* Receive Test */
104 #define	CSR_PRFDAR	0x80	/* PCI Receive First Descriptor Address */
105 #define	CSR_PRCDAR	0x84	/* PCI Receive Current Descriptor Address */
106 #define	CSR_PRHDAR	0x88	/* PCI Receive Host Data Address */
107 #define	CSR_PRFLAR	0x8C	/* PCI Receive Fragment List Address */
108 #define	CSR_PRDLGTH	0x90	/* PCI Receive DMA Length/Control */
109 #define	CSR_PRFCNT	0x94	/* PCI Receive Fragment Count */
110 #define	CSR_PRLCAR	0x98	/* PCI Receive RAM Current Address */
111 #define	CSR_PRLPAR	0x9C	/* PCI Receive RAM Packet Address */
112 #define	CSR_PREFAR	0xA0	/* PCI Receive End of Frame Address */
113 #define	CSR_PRSTAT	0xA4	/* PCI Receive DMA Status Register */
114 #define	CSR_PRBUF	0xA8	/* Receive RAM Buffer */
115 #define	CSR_RDNCAR	0xAC	/* Receive MTU Current Address */
116 #define	CSR_PRCPTHR	0xB0	/* PCI Receive Copy Threshold Register */
148 #define	INTSTAT_RCC	(1UL << 0)	/* Receive Copy Complete */
150 #define	INTSTAT_RQE	(1UL << 2)	/* Receive Queue Empty */
151 #define	INTSTAT_OVW	(1UL << 3)	/* Receive Overflow */
152 #define	INTSTAT_RXE	(1UL << 4)	/* Receive Error */
159 #define	INTSTAT_RCT	(1UL << 11)	/* Receive Copy Threshold */
164 #define	INTSTAT_RXIDLE	(1UL << 17)	/* Receive Idle */
166 #define	INTSTAT_RCIP	(1UL << 19)	/* Receive Copy in Progress */
168 #define	INTSTAT_RBE	(1UL << 21)	/* Receive Buffers Empty */
169 #define	INTSTAT_RCTS	(1UL << 22)	/* Receive Copy Threshold Status */
170 #define	INTSTAT_RSV	(1UL << 23)	/* Receive Status Valid */
176 #define	INTMASK_RCC	(1UL << 0)	/* Receive Copy Complete */
178 #define	INTMASK_RQE	(1UL << 2)	/* Receive Queue Empty */
179 #define	INTMASK_OVW	(1UL << 3)	/* Receive Overflow */
180 #define	INTMASK_RXE	(1UL << 4)	/* Receive Error */
187 #define	INTMASK_RCT	(1UL << 11)	/* Receive Copy Threshold */
196 #define	GENCTL_ONECOPY	(1UL << 4)	/* One Copy per Receive Frame */
198 #define	GENCTL_RDP	(1UL << 6)	/* Receive DMA Priority */
200 #define	GENCTL_RFT_32	(0UL << 8)	/* Receive FIFO Threshold (1/4) */
201 #define	GENCTL_RFT_64	(1UL << 8)	/* Receive FIFO Threshold (1/2) */
202 #define	GENCTL_RFT_96	(2UL << 8)	/* Receive FIFO Threshold (3/4) */
203 #define	GENCTL_RFT_128	(3UL << 8)	/* Receive FIFO Threshold (FULL) */
255 #define	RXCON_RRF	(1UL << 1)	/* Receive Runt Frames */
256 #define	RXCON_RBF	(1UL << 2)	/* Receive Broadcast Frames */
257 #define	RXCON_RMF	(1UL << 3)	/* Receive Multicast Frames */
258 #define	RXCON_RIIA	(1UL << 4)	/* Receive Inverse Addresses */
261 #define	RXCON_ERE	(1UL << 7)	/* Early Receive Enable */