651 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_init_nvm_params_ich8lan()  local
659 	nvm->type = e1000_nvm_flash_sw;  in e1000_init_nvm_params_ich8lan()
668 		nvm->flash_base_addr = 0;  in e1000_init_nvm_params_ich8lan()
672 		nvm->flash_bank_size = nvm_size / 2;  in e1000_init_nvm_params_ich8lan()
674 		nvm->flash_bank_size /= sizeof(u16);  in e1000_init_nvm_params_ich8lan()
694 		nvm->flash_base_addr = sector_base_addr  in e1000_init_nvm_params_ich8lan()
700 		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)  in e1000_init_nvm_params_ich8lan()
702 		nvm->flash_bank_size /= 2;  in e1000_init_nvm_params_ich8lan()
704 		nvm->flash_bank_size /= sizeof(u16);  in e1000_init_nvm_params_ich8lan()
707 	nvm->word_size = E1000_SHADOW_RAM_WORDS;  in e1000_init_nvm_params_ich8lan()
710 	for (i = 0; i < nvm->word_size; i++) {  in e1000_init_nvm_params_ich8lan()
719 	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;  in e1000_init_nvm_params_ich8lan()
720 	nvm->ops.release	= e1000_release_nvm_ich8lan;  in e1000_init_nvm_params_ich8lan()
722 		nvm->ops.read	= e1000_read_nvm_spt;  in e1000_init_nvm_params_ich8lan()
723 		nvm->ops.update	= e1000_update_nvm_checksum_spt;  in e1000_init_nvm_params_ich8lan()
725 		nvm->ops.read	= e1000_read_nvm_ich8lan;  in e1000_init_nvm_params_ich8lan()
726 		nvm->ops.update	= e1000_update_nvm_checksum_ich8lan;  in e1000_init_nvm_params_ich8lan()
728 	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;  in e1000_init_nvm_params_ich8lan()
729 	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;  in e1000_init_nvm_params_ich8lan()
730 	nvm->ops.write		= e1000_write_nvm_ich8lan;  in e1000_init_nvm_params_ich8lan()
1843 	hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;  in e1000_init_function_pointers_ich8lan()
2392 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,  in e1000_sw_lcd_config_ich8lan()
2397 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),  in e1000_sw_lcd_config_ich8lan()
3442 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_valid_nvm_bank_detect_ich8lan()  local
3443 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);  in e1000_valid_nvm_bank_detect_ich8lan()
3462 		bank1_offset = nvm->flash_bank_size;  in e1000_valid_nvm_bank_detect_ich8lan()
3553 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_read_nvm_spt()  local
3564 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_read_nvm_spt()
3571 	nvm->ops.acquire(hw);  in e1000_read_nvm_spt()
3579 	act_offset = (bank) ? nvm->flash_bank_size : 0;  in e1000_read_nvm_spt()
3625 	nvm->ops.release(hw);  in e1000_read_nvm_spt()
3646 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_read_nvm_ich8lan()  local
3655 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_read_nvm_ich8lan()
3662 	nvm->ops.acquire(hw);  in e1000_read_nvm_ich8lan()
3670 	act_offset = (bank) ? nvm->flash_bank_size : 0;  in e1000_read_nvm_ich8lan()
3687 	nvm->ops.release(hw);  in e1000_read_nvm_ich8lan()
3924 			     hw->nvm.flash_base_addr);  in e1000_read_flash_data_ich8lan()
3998 			     hw->nvm.flash_base_addr);  in e1000_read_flash_data32_ich8lan()
4065 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_write_nvm_ich8lan()  local
4071 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_write_nvm_ich8lan()
4077 	nvm->ops.acquire(hw);  in e1000_write_nvm_ich8lan()
4084 	nvm->ops.release(hw);  in e1000_write_nvm_ich8lan()
4102 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_update_nvm_checksum_spt()  local
4114 	if (nvm->type != e1000_nvm_flash_sw)  in e1000_update_nvm_checksum_spt()
4117 	nvm->ops.acquire(hw);  in e1000_update_nvm_checksum_spt()
4130 		new_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_spt()
4136 		old_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_spt()
4241 	nvm->ops.release(hw);  in e1000_update_nvm_checksum_spt()
4247 		nvm->ops.reload(hw);  in e1000_update_nvm_checksum_spt()
4271 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_update_nvm_checksum_ich8lan()  local
4283 	if (nvm->type != e1000_nvm_flash_sw)  in e1000_update_nvm_checksum_ich8lan()
4286 	nvm->ops.acquire(hw);  in e1000_update_nvm_checksum_ich8lan()
4299 		new_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_ich8lan()
4305 		old_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_ich8lan()
4394 	nvm->ops.release(hw);  in e1000_update_nvm_checksum_ich8lan()
4400 		nvm->ops.reload(hw);  in e1000_update_nvm_checksum_ich8lan()
4454 	ret_val = hw->nvm.ops.read(hw, word, 1, &data);  in e1000_validate_nvm_checksum_ich8lan()
4460 		ret_val = hw->nvm.ops.write(hw, word, 1, &data);  in e1000_validate_nvm_checksum_ich8lan()
4463 		ret_val = hw->nvm.ops.update(hw);  in e1000_validate_nvm_checksum_ich8lan()
4501 			     hw->nvm.flash_base_addr);  in e1000_write_flash_data_ich8lan()
4593 			     hw->nvm.flash_base_addr);  in e1000_write_flash_data32_ich8lan()
4757 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_erase_flash_bank_ich8lan()  local
4762 	u32 flash_bank_size = nvm->flash_bank_size * 2;  in e1000_erase_flash_bank_ich8lan()
4806 	flash_linear_addr = hw->nvm.flash_base_addr;  in e1000_erase_flash_bank_ich8lan()
4882 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);  in e1000_valid_led_default_ich8lan()
4918 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);  in e1000_id_led_init_pchlan()