Lines Matching refs:hw
74 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
86 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
87 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
95 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
99 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
102 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
104 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
105 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
106 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
111 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
114 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
117 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
118 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
121 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
122 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
123 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
124 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
127 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
139 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
141 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
142 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
143 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
145 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
146 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
147 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
200 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) in e1000_phy_is_accessible_pchlan() argument
209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); in e1000_phy_is_accessible_pchlan()
214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); in e1000_phy_is_accessible_pchlan()
223 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
224 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
227 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
235 if (hw->mac.type < e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
236 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
237 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_phy_is_accessible_pchlan()
239 ret_val = e1000_get_phy_id(hw); in e1000_phy_is_accessible_pchlan()
240 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
246 if (hw->mac.type >= e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
248 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_phy_is_accessible_pchlan()
251 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_phy_is_accessible_pchlan()
253 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_phy_is_accessible_pchlan()
256 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_phy_is_accessible_pchlan()
258 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_phy_is_accessible_pchlan()
272 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) in e1000_toggle_lanphypc_pch_lpt() argument
279 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); in e1000_toggle_lanphypc_pch_lpt()
282 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
285 mac_reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_toggle_lanphypc_pch_lpt()
288 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
289 E1000_WRITE_FLUSH(hw); in e1000_toggle_lanphypc_pch_lpt()
292 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
293 E1000_WRITE_FLUSH(hw); in e1000_toggle_lanphypc_pch_lpt()
295 if (hw->mac.type < e1000_pch_lpt) { in e1000_toggle_lanphypc_pch_lpt()
302 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & in e1000_toggle_lanphypc_pch_lpt()
316 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) in e1000_init_phy_workarounds_pchlan() argument
318 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_init_phy_workarounds_pchlan()
326 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); in e1000_init_phy_workarounds_pchlan()
331 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; in e1000_init_phy_workarounds_pchlan()
332 e1000_disable_ulp_lpt_lp(hw, TRUE); in e1000_init_phy_workarounds_pchlan()
334 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
344 switch (hw->mac.type) { in e1000_init_phy_workarounds_pchlan()
356 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
362 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_init_phy_workarounds_pchlan()
364 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan()
374 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
379 if ((hw->mac.type == e1000_pchlan) && in e1000_init_phy_workarounds_pchlan()
383 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
390 e1000_toggle_lanphypc_pch_lpt(hw); in e1000_init_phy_workarounds_pchlan()
391 if (hw->mac.type >= e1000_pch_lpt) { in e1000_init_phy_workarounds_pchlan()
392 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
398 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_init_phy_workarounds_pchlan()
400 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan()
402 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
412 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
416 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
426 ret_val = e1000_phy_hw_reset_generic(hw); in e1000_init_phy_workarounds_pchlan()
436 ret_val = hw->phy.ops.check_reset_block(hw); in e1000_init_phy_workarounds_pchlan()
443 if ((hw->mac.type == e1000_pch2lan) && in e1000_init_phy_workarounds_pchlan()
446 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); in e1000_init_phy_workarounds_pchlan()
458 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) in e1000_init_phy_params_pchlan() argument
460 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_pchlan()
488 ret_val = e1000_init_phy_workarounds_pchlan(hw); in e1000_init_phy_params_pchlan()
493 switch (hw->mac.type) { in e1000_init_phy_params_pchlan()
495 ret_val = e1000_get_phy_id(hw); in e1000_init_phy_params_pchlan()
516 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_init_phy_params_pchlan()
519 ret_val = e1000_get_phy_id(hw); in e1000_init_phy_params_pchlan()
557 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) in e1000_init_phy_params_ich8lan() argument
559 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_ich8lan()
584 ret_val = e1000_determine_phy_address(hw); in e1000_init_phy_params_ich8lan()
588 ret_val = e1000_determine_phy_address(hw); in e1000_init_phy_params_ich8lan()
599 ret_val = e1000_get_phy_id(hw); in e1000_init_phy_params_ich8lan()
649 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) in e1000_init_nvm_params_ich8lan() argument
651 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_ich8lan()
652 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_init_nvm_params_ich8lan()
661 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
670 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1) in e1000_init_nvm_params_ich8lan()
676 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; in e1000_init_nvm_params_ich8lan()
679 if (!hw->flash_address) { in e1000_init_nvm_params_ich8lan()
684 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); in e1000_init_nvm_params_ich8lan()
721 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
742 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) in e1000_init_mac_params_ich8lan() argument
744 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_ich8lan()
749 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_ich8lan()
853 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE); in e1000_init_mac_params_ich8lan()
867 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, in __e1000_access_emi_reg_locked() argument
874 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); in __e1000_access_emi_reg_locked()
879 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, in __e1000_access_emi_reg_locked()
882 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, in __e1000_access_emi_reg_locked()
896 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) in e1000_read_emi_reg_locked() argument
900 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE); in e1000_read_emi_reg_locked()
911 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) in e1000_write_emi_reg_locked() argument
915 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE); in e1000_write_emi_reg_locked()
932 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) in e1000_set_eee_pchlan() argument
934 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_eee_pchlan()
940 switch (hw->phy.type) { in e1000_set_eee_pchlan()
955 ret_val = hw->phy.ops.acquire(hw); in e1000_set_eee_pchlan()
959 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); in e1000_set_eee_pchlan()
969 ret_val = e1000_read_emi_reg_locked(hw, lpa, in e1000_set_eee_pchlan()
975 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); in e1000_set_eee_pchlan()
986 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); in e1000_set_eee_pchlan()
999 if (hw->phy.type == e1000_phy_82579) { in e1000_set_eee_pchlan()
1000 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, in e1000_set_eee_pchlan()
1006 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, in e1000_set_eee_pchlan()
1011 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); in e1000_set_eee_pchlan()
1015 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); in e1000_set_eee_pchlan()
1017 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
1033 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) in e1000_k1_workaround_lpt_lp() argument
1035 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); in e1000_k1_workaround_lpt_lp()
1036 u32 status = E1000_READ_REG(hw, E1000_STATUS); in e1000_k1_workaround_lpt_lp()
1041 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_workaround_lpt_lp()
1046 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_k1_workaround_lpt_lp()
1052 e1000_write_kmrn_reg_locked(hw, in e1000_k1_workaround_lpt_lp()
1061 E1000_WRITE_REG(hw, E1000_FEXTNVM6, in e1000_k1_workaround_lpt_lp()
1065 e1000_write_kmrn_reg_locked(hw, in e1000_k1_workaround_lpt_lp()
1069 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
1074 if ((hw->phy.revision > 5) || !link || in e1000_k1_workaround_lpt_lp()
1079 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®); in e1000_k1_workaround_lpt_lp()
1101 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); in e1000_k1_workaround_lpt_lp()
1106 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); in e1000_k1_workaround_lpt_lp()
1142 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) in e1000_platform_pm_pch_lpt() argument
1159 if (!hw->mac.max_frame_size) { in e1000_platform_pm_pch_lpt()
1164 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in e1000_platform_pm_pch_lpt()
1171 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; in e1000_platform_pm_pch_lpt()
1182 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; in e1000_platform_pm_pch_lpt()
1200 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); in e1000_platform_pm_pch_lpt()
1201 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); in e1000_platform_pm_pch_lpt()
1223 E1000_WRITE_REG(hw, E1000_LTRV, reg); in e1000_platform_pm_pch_lpt()
1226 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; in e1000_platform_pm_pch_lpt()
1228 E1000_WRITE_REG(hw, E1000_SVT, reg); in e1000_platform_pm_pch_lpt()
1231 reg = E1000_READ_REG(hw, E1000_SVCR); in e1000_platform_pm_pch_lpt()
1238 E1000_WRITE_REG(hw, E1000_SVCR, reg); in e1000_platform_pm_pch_lpt()
1250 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) in e1000_set_obff_timer_pch_lpt() argument
1266 svcr = E1000_READ_REG(hw, E1000_SVCR); in e1000_set_obff_timer_pch_lpt()
1269 E1000_WRITE_REG(hw, E1000_SVCR, svcr); in e1000_set_obff_timer_pch_lpt()
1284 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) in e1000_enable_ulp_lpt_lp() argument
1291 if ((hw->mac.type < e1000_pch_lpt) || in e1000_enable_ulp_lpt_lp()
1292 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_enable_ulp_lpt_lp()
1293 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_enable_ulp_lpt_lp()
1294 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || in e1000_enable_ulp_lpt_lp()
1295 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || in e1000_enable_ulp_lpt_lp()
1296 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) in e1000_enable_ulp_lpt_lp()
1299 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { in e1000_enable_ulp_lpt_lp()
1301 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_enable_ulp_lpt_lp()
1303 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_enable_ulp_lpt_lp()
1312 while (!(E1000_READ_REG(hw, E1000_FEXT) & in e1000_enable_ulp_lpt_lp()
1315 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) in e1000_enable_ulp_lpt_lp()
1324 (E1000_READ_REG(hw, E1000_FEXT) & in e1000_enable_ulp_lpt_lp()
1329 ret_val = hw->phy.ops.acquire(hw); in e1000_enable_ulp_lpt_lp()
1334 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_enable_ulp_lpt_lp()
1338 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_enable_ulp_lpt_lp()
1341 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_enable_ulp_lpt_lp()
1343 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_enable_ulp_lpt_lp()
1348 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { in e1000_enable_ulp_lpt_lp()
1349 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1357 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1367 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); in e1000_enable_ulp_lpt_lp()
1373 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC) in e1000_enable_ulp_lpt_lp()
1385 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_enable_ulp_lpt_lp()
1388 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); in e1000_enable_ulp_lpt_lp()
1390 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); in e1000_enable_ulp_lpt_lp()
1394 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_enable_ulp_lpt_lp()
1396 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && in e1000_enable_ulp_lpt_lp()
1397 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { in e1000_enable_ulp_lpt_lp()
1398 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1405 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1410 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; in e1000_enable_ulp_lpt_lp()
1430 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) in e1000_disable_ulp_lpt_lp() argument
1437 if ((hw->mac.type < e1000_pch_lpt) || in e1000_disable_ulp_lpt_lp()
1438 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_disable_ulp_lpt_lp()
1439 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_disable_ulp_lpt_lp()
1440 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || in e1000_disable_ulp_lpt_lp()
1441 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || in e1000_disable_ulp_lpt_lp()
1442 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) in e1000_disable_ulp_lpt_lp()
1445 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { in e1000_disable_ulp_lpt_lp()
1448 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_disable_ulp_lpt_lp()
1451 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_disable_ulp_lpt_lp()
1455 while (E1000_READ_REG(hw, E1000_FWSM) & in e1000_disable_ulp_lpt_lp()
1467 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_disable_ulp_lpt_lp()
1469 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_disable_ulp_lpt_lp()
1472 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_disable_ulp_lpt_lp()
1474 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_disable_ulp_lpt_lp()
1480 ret_val = hw->phy.ops.acquire(hw); in e1000_disable_ulp_lpt_lp()
1486 e1000_toggle_lanphypc_pch_lpt(hw); in e1000_disable_ulp_lpt_lp()
1489 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_disable_ulp_lpt_lp()
1494 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_disable_ulp_lpt_lp()
1496 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_disable_ulp_lpt_lp()
1500 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, in e1000_disable_ulp_lpt_lp()
1506 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_disable_ulp_lpt_lp()
1509 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_disable_ulp_lpt_lp()
1511 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_disable_ulp_lpt_lp()
1516 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); in e1000_disable_ulp_lpt_lp()
1520 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); in e1000_disable_ulp_lpt_lp()
1523 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); in e1000_disable_ulp_lpt_lp()
1534 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_disable_ulp_lpt_lp()
1538 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_disable_ulp_lpt_lp()
1541 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); in e1000_disable_ulp_lpt_lp()
1543 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); in e1000_disable_ulp_lpt_lp()
1546 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1548 hw->phy.ops.reset(hw); in e1000_disable_ulp_lpt_lp()
1555 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; in e1000_disable_ulp_lpt_lp()
1568 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) in e1000_check_for_copper_link_ich8lan() argument
1570 struct e1000_mac_info *mac = &hw->mac; in e1000_check_for_copper_link_ich8lan()
1590 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); in e1000_check_for_copper_link_ich8lan()
1594 if (hw->mac.type == e1000_pchlan) { in e1000_check_for_copper_link_ich8lan()
1595 ret_val = e1000_k1_gig_workaround_hv(hw, link); in e1000_check_for_copper_link_ich8lan()
1604 if ((hw->mac.type >= e1000_pch2lan) && link) { in e1000_check_for_copper_link_ich8lan()
1607 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex); in e1000_check_for_copper_link_ich8lan()
1608 tipg_reg = E1000_READ_REG(hw, E1000_TIPG); in e1000_check_for_copper_link_ich8lan()
1615 } else if (hw->mac.type >= e1000_pch_spt && in e1000_check_for_copper_link_ich8lan()
1625 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg); in e1000_check_for_copper_link_ich8lan()
1627 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1631 if (hw->mac.type == e1000_pch2lan) in e1000_check_for_copper_link_ich8lan()
1635 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); in e1000_check_for_copper_link_ich8lan()
1637 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1640 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, in e1000_check_for_copper_link_ich8lan()
1647 hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1652 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1657 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1661 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1666 if (hw->mac.type >= e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1671 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1675 ret_val = hw->phy.ops.read_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1679 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1688 hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1691 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1695 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1699 ret_val = hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1702 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1715 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1718 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); in e1000_check_for_copper_link_ich8lan()
1721 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); in e1000_check_for_copper_link_ich8lan()
1725 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || in e1000_check_for_copper_link_ich8lan()
1726 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || in e1000_check_for_copper_link_ich8lan()
1727 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || in e1000_check_for_copper_link_ich8lan()
1728 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { in e1000_check_for_copper_link_ich8lan()
1729 ret_val = e1000_k1_workaround_lpt_lp(hw, link); in e1000_check_for_copper_link_ich8lan()
1733 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1738 ret_val = e1000_platform_pm_pch_lpt(hw, link); in e1000_check_for_copper_link_ich8lan()
1744 hw->dev_spec.ich8lan.eee_lp_ability = 0; in e1000_check_for_copper_link_ich8lan()
1747 if (hw->mac.type == e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1748 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG); in e1000_check_for_copper_link_ich8lan()
1749 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); in e1000_check_for_copper_link_ich8lan()
1752 (hw->dev_spec.ich8lan.disable_k1_off == FALSE)) in e1000_check_for_copper_link_ich8lan()
1757 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); in e1000_check_for_copper_link_ich8lan()
1765 switch (hw->mac.type) { in e1000_check_for_copper_link_ich8lan()
1767 ret_val = e1000_k1_workaround_lv(hw); in e1000_check_for_copper_link_ich8lan()
1772 if (hw->phy.type == e1000_phy_82578) { in e1000_check_for_copper_link_ich8lan()
1773 ret_val = e1000_link_stall_workaround_hv(hw); in e1000_check_for_copper_link_ich8lan()
1783 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); in e1000_check_for_copper_link_ich8lan()
1786 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) != in e1000_check_for_copper_link_ich8lan()
1790 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); in e1000_check_for_copper_link_ich8lan()
1799 e1000_check_downshift_generic(hw); in e1000_check_for_copper_link_ich8lan()
1802 if (hw->phy.type > e1000_phy_82579) { in e1000_check_for_copper_link_ich8lan()
1803 ret_val = e1000_set_eee_pchlan(hw); in e1000_check_for_copper_link_ich8lan()
1818 mac->ops.config_collision_dist(hw); in e1000_check_for_copper_link_ich8lan()
1825 ret_val = e1000_config_fc_after_link_up_generic(hw); in e1000_check_for_copper_link_ich8lan()
1838 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) in e1000_init_function_pointers_ich8lan() argument
1842 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1843 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1844 switch (hw->mac.type) { in e1000_init_function_pointers_ich8lan()
1848 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1863 hw->phy.ops.init_params = e1000_init_phy_params_pchlan; in e1000_init_function_pointers_ich8lan()
1876 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) in e1000_acquire_nvm_ich8lan() argument
1880 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex); in e1000_acquire_nvm_ich8lan()
1891 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) in e1000_release_nvm_ich8lan() argument
1895 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex); in e1000_release_nvm_ich8lan()
1907 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) in e1000_acquire_swflag_ich8lan() argument
1914 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex); in e1000_acquire_swflag_ich8lan()
1917 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_acquire_swflag_ich8lan()
1934 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_acquire_swflag_ich8lan()
1937 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_acquire_swflag_ich8lan()
1947 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl); in e1000_acquire_swflag_ich8lan()
1949 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_acquire_swflag_ich8lan()
1956 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); in e1000_acquire_swflag_ich8lan()
1968 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) in e1000_release_swflag_ich8lan() argument
1974 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_release_swflag_ich8lan()
1978 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_release_swflag_ich8lan()
1983 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); in e1000_release_swflag_ich8lan()
1996 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) in e1000_check_mng_mode_ich8lan() argument
2002 fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_check_mng_mode_ich8lan()
2017 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) in e1000_check_mng_mode_pchlan() argument
2023 fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_check_mng_mode_pchlan()
2040 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) in e1000_rar_set_pch2lan() argument
2060 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); in e1000_rar_set_pch2lan()
2061 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2062 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); in e1000_rar_set_pch2lan()
2063 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2070 if (index < (u32) (hw->mac.rar_entry_count)) { in e1000_rar_set_pch2lan()
2073 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_rar_set_pch2lan()
2077 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); in e1000_rar_set_pch2lan()
2078 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2079 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); in e1000_rar_set_pch2lan()
2080 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2082 e1000_release_swflag_ich8lan(hw); in e1000_rar_set_pch2lan()
2085 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && in e1000_rar_set_pch2lan()
2086 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) in e1000_rar_set_pch2lan()
2090 (index - 1), E1000_READ_REG(hw, E1000_FWSM)); in e1000_rar_set_pch2lan()
2109 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) in e1000_rar_set_pch_lpt() argument
2129 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); in e1000_rar_set_pch_lpt()
2130 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2131 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); in e1000_rar_set_pch_lpt()
2132 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2139 if (index < hw->mac.rar_entry_count) { in e1000_rar_set_pch_lpt()
2140 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & in e1000_rar_set_pch_lpt()
2151 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_rar_set_pch_lpt()
2156 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), in e1000_rar_set_pch_lpt()
2158 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2159 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), in e1000_rar_set_pch_lpt()
2161 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2163 e1000_release_swflag_ich8lan(hw); in e1000_rar_set_pch_lpt()
2166 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && in e1000_rar_set_pch_lpt()
2167 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) in e1000_rar_set_pch_lpt()
2186 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, in e1000_update_mc_addr_list_pch2lan() argument
2196 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); in e1000_update_mc_addr_list_pch2lan()
2198 ret_val = hw->phy.ops.acquire(hw); in e1000_update_mc_addr_list_pch2lan()
2202 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_update_mc_addr_list_pch2lan()
2206 for (i = 0; i < hw->mac.mta_reg_count; i++) { in e1000_update_mc_addr_list_pch2lan()
2207 hw->phy.ops.write_reg_page(hw, BM_MTA(i), in e1000_update_mc_addr_list_pch2lan()
2208 (u16)(hw->mac.mta_shadow[i] & in e1000_update_mc_addr_list_pch2lan()
2210 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), in e1000_update_mc_addr_list_pch2lan()
2211 (u16)((hw->mac.mta_shadow[i] >> 16) & in e1000_update_mc_addr_list_pch2lan()
2215 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_update_mc_addr_list_pch2lan()
2218 hw->phy.ops.release(hw); in e1000_update_mc_addr_list_pch2lan()
2229 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) in e1000_check_reset_block_ich8lan() argument
2238 fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_check_reset_block_ich8lan()
2256 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) in e1000_write_smbus_addr() argument
2259 u32 strap = E1000_READ_REG(hw, E1000_STRAP); in e1000_write_smbus_addr()
2266 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); in e1000_write_smbus_addr()
2274 if (hw->phy.type == e1000_phy_i217) { in e1000_write_smbus_addr()
2287 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); in e1000_write_smbus_addr()
2297 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) in e1000_sw_lcd_config_ich8lan() argument
2299 struct e1000_phy_info *phy = &hw->phy; in e1000_sw_lcd_config_ich8lan()
2312 switch (hw->mac.type) { in e1000_sw_lcd_config_ich8lan()
2317 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || in e1000_sw_lcd_config_ich8lan()
2318 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { in e1000_sw_lcd_config_ich8lan()
2342 ret_val = hw->phy.ops.acquire(hw); in e1000_sw_lcd_config_ich8lan()
2346 data = E1000_READ_REG(hw, E1000_FEXTNVM); in e1000_sw_lcd_config_ich8lan()
2353 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_sw_lcd_config_ich8lan()
2354 if ((hw->mac.type < e1000_pch2lan) && in e1000_sw_lcd_config_ich8lan()
2358 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); in e1000_sw_lcd_config_ich8lan()
2367 if (((hw->mac.type == e1000_pchlan) && in e1000_sw_lcd_config_ich8lan()
2369 (hw->mac.type > e1000_pchlan)) { in e1000_sw_lcd_config_ich8lan()
2375 ret_val = e1000_write_smbus_addr(hw); in e1000_sw_lcd_config_ich8lan()
2379 data = E1000_READ_REG(hw, E1000_LEDCTL); in e1000_sw_lcd_config_ich8lan()
2380 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, in e1000_sw_lcd_config_ich8lan()
2392 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, in e1000_sw_lcd_config_ich8lan()
2397 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), in e1000_sw_lcd_config_ich8lan()
2411 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, in e1000_sw_lcd_config_ich8lan()
2418 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
2432 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) in e1000_k1_gig_workaround_hv() argument
2436 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; in e1000_k1_gig_workaround_hv()
2440 if (hw->mac.type != e1000_pchlan) in e1000_k1_gig_workaround_hv()
2444 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_gig_workaround_hv()
2450 if (hw->phy.type == e1000_phy_82578) { in e1000_k1_gig_workaround_hv()
2451 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, in e1000_k1_gig_workaround_hv()
2466 if (hw->phy.type == e1000_phy_82577) { in e1000_k1_gig_workaround_hv()
2467 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, in e1000_k1_gig_workaround_hv()
2483 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), in e1000_k1_gig_workaround_hv()
2490 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), in e1000_k1_gig_workaround_hv()
2496 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); in e1000_k1_gig_workaround_hv()
2499 hw->phy.ops.release(hw); in e1000_k1_gig_workaround_hv()
2514 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) in e1000_configure_k1_ich8lan() argument
2524 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_configure_k1_ich8lan()
2534 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_configure_k1_ich8lan()
2540 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_configure_k1_ich8lan()
2541 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_configure_k1_ich8lan()
2545 E1000_WRITE_REG(hw, E1000_CTRL, reg); in e1000_configure_k1_ich8lan()
2547 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); in e1000_configure_k1_ich8lan()
2548 E1000_WRITE_FLUSH(hw); in e1000_configure_k1_ich8lan()
2550 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); in e1000_configure_k1_ich8lan()
2551 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_configure_k1_ich8lan()
2552 E1000_WRITE_FLUSH(hw); in e1000_configure_k1_ich8lan()
2567 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) in e1000_oem_bits_config_ich8lan() argument
2575 if (hw->mac.type < e1000_pchlan) in e1000_oem_bits_config_ich8lan()
2578 ret_val = hw->phy.ops.acquire(hw); in e1000_oem_bits_config_ich8lan()
2582 if (hw->mac.type == e1000_pchlan) { in e1000_oem_bits_config_ich8lan()
2583 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_oem_bits_config_ich8lan()
2588 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); in e1000_oem_bits_config_ich8lan()
2592 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_oem_bits_config_ich8lan()
2594 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); in e1000_oem_bits_config_ich8lan()
2617 if ((d0_state || (hw->mac.type != e1000_pchlan)) && in e1000_oem_bits_config_ich8lan()
2618 !hw->phy.ops.check_reset_block(hw)) in e1000_oem_bits_config_ich8lan()
2621 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); in e1000_oem_bits_config_ich8lan()
2624 hw->phy.ops.release(hw); in e1000_oem_bits_config_ich8lan()
2634 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) in e1000_set_mdio_slow_mode_hv() argument
2641 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); in e1000_set_mdio_slow_mode_hv()
2647 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); in e1000_set_mdio_slow_mode_hv()
2656 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) in e1000_hv_phy_workarounds_ich8lan() argument
2663 if (hw->mac.type != e1000_pchlan) in e1000_hv_phy_workarounds_ich8lan()
2667 if (hw->phy.type == e1000_phy_82577) { in e1000_hv_phy_workarounds_ich8lan()
2668 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_hv_phy_workarounds_ich8lan()
2673 if (((hw->phy.type == e1000_phy_82577) && in e1000_hv_phy_workarounds_ich8lan()
2674 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || in e1000_hv_phy_workarounds_ich8lan()
2675 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { in e1000_hv_phy_workarounds_ich8lan()
2677 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2682 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, in e1000_hv_phy_workarounds_ich8lan()
2688 if (hw->phy.type == e1000_phy_82578) { in e1000_hv_phy_workarounds_ich8lan()
2692 if (hw->phy.revision < 2) { in e1000_hv_phy_workarounds_ich8lan()
2693 e1000_phy_sw_reset_generic(hw); in e1000_hv_phy_workarounds_ich8lan()
2694 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, in e1000_hv_phy_workarounds_ich8lan()
2700 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2704 hw->phy.addr = 1; in e1000_hv_phy_workarounds_ich8lan()
2705 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); in e1000_hv_phy_workarounds_ich8lan()
2706 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2713 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE); in e1000_hv_phy_workarounds_ich8lan()
2718 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2721 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); in e1000_hv_phy_workarounds_ich8lan()
2724 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, in e1000_hv_phy_workarounds_ich8lan()
2730 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); in e1000_hv_phy_workarounds_ich8lan()
2732 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2741 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) in e1000_copy_rx_addrs_to_phy_ich8lan() argument
2749 ret_val = hw->phy.ops.acquire(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2752 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_copy_rx_addrs_to_phy_ich8lan()
2757 for (i = 0; i < (hw->mac.rar_entry_count); i++) { in e1000_copy_rx_addrs_to_phy_ich8lan()
2758 mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); in e1000_copy_rx_addrs_to_phy_ich8lan()
2759 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2761 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2764 mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); in e1000_copy_rx_addrs_to_phy_ich8lan()
2765 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2767 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2772 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_copy_rx_addrs_to_phy_ich8lan()
2775 hw->phy.ops.release(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2802 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) in e1000_lv_jumbo_workaround_ich8lan() argument
2811 if (hw->mac.type < e1000_pch2lan) in e1000_lv_jumbo_workaround_ich8lan()
2815 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2816 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), in e1000_lv_jumbo_workaround_ich8lan()
2825 for (i = 0; i < hw->mac.rar_entry_count; i++) { in e1000_lv_jumbo_workaround_ich8lan()
2829 addr_high = E1000_READ_REG(hw, E1000_RAH(i)); in e1000_lv_jumbo_workaround_ich8lan()
2832 addr_low = E1000_READ_REG(hw, E1000_RAL(i)); in e1000_lv_jumbo_workaround_ich8lan()
2840 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), in e1000_lv_jumbo_workaround_ich8lan()
2845 e1000_copy_rx_addrs_to_phy_ich8lan(hw); in e1000_lv_jumbo_workaround_ich8lan()
2848 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); in e1000_lv_jumbo_workaround_ich8lan()
2851 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2853 mac_reg = E1000_READ_REG(hw, E1000_RCTL); in e1000_lv_jumbo_workaround_ich8lan()
2855 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2857 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2862 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2867 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2874 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2881 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2884 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2887 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2889 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2892 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2895 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2898 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); in e1000_lv_jumbo_workaround_ich8lan()
2901 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2902 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | in e1000_lv_jumbo_workaround_ich8lan()
2908 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); in e1000_lv_jumbo_workaround_ich8lan()
2910 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2912 mac_reg = E1000_READ_REG(hw, E1000_RCTL); in e1000_lv_jumbo_workaround_ich8lan()
2914 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2916 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2921 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2926 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2933 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2940 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2942 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2945 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2947 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2950 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2953 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2956 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); in e1000_lv_jumbo_workaround_ich8lan()
2959 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2960 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & in e1000_lv_jumbo_workaround_ich8lan()
2967 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & in e1000_lv_jumbo_workaround_ich8lan()
2975 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) in e1000_lv_phy_workarounds_ich8lan() argument
2981 if (hw->mac.type != e1000_pch2lan) in e1000_lv_phy_workarounds_ich8lan()
2985 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_lv_phy_workarounds_ich8lan()
2989 ret_val = hw->phy.ops.acquire(hw); in e1000_lv_phy_workarounds_ich8lan()
2993 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); in e1000_lv_phy_workarounds_ich8lan()
2997 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); in e1000_lv_phy_workarounds_ich8lan()
2999 hw->phy.ops.release(hw); in e1000_lv_phy_workarounds_ich8lan()
3011 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) in e1000_k1_workaround_lv() argument
3018 if (hw->mac.type != e1000_pch2lan) in e1000_k1_workaround_lv()
3022 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); in e1000_k1_workaround_lv()
3033 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, in e1000_k1_workaround_lv()
3038 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, in e1000_k1_workaround_lv()
3044 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); in e1000_k1_workaround_lv()
3047 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); in e1000_k1_workaround_lv()
3062 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) in e1000_gate_hw_phy_config_ich8lan() argument
3068 if (hw->mac.type < e1000_pch2lan) in e1000_gate_hw_phy_config_ich8lan()
3071 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_gate_hw_phy_config_ich8lan()
3078 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_gate_hw_phy_config_ich8lan()
3088 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) in e1000_lan_init_done_ich8lan() argument
3096 data = E1000_READ_REG(hw, E1000_STATUS); in e1000_lan_init_done_ich8lan()
3109 data = E1000_READ_REG(hw, E1000_STATUS); in e1000_lan_init_done_ich8lan()
3111 E1000_WRITE_REG(hw, E1000_STATUS, data); in e1000_lan_init_done_ich8lan()
3118 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) in e1000_post_phy_reset_ich8lan() argument
3125 if (hw->phy.ops.check_reset_block(hw)) in e1000_post_phy_reset_ich8lan()
3132 switch (hw->mac.type) { in e1000_post_phy_reset_ich8lan()
3134 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3139 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3148 if (hw->mac.type >= e1000_pchlan) { in e1000_post_phy_reset_ich8lan()
3149 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); in e1000_post_phy_reset_ich8lan()
3151 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); in e1000_post_phy_reset_ich8lan()
3155 ret_val = e1000_sw_lcd_config_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3160 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); in e1000_post_phy_reset_ich8lan()
3162 if (hw->mac.type == e1000_pch2lan) { in e1000_post_phy_reset_ich8lan()
3164 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_post_phy_reset_ich8lan()
3167 e1000_gate_hw_phy_config_ich8lan(hw, FALSE); in e1000_post_phy_reset_ich8lan()
3171 ret_val = hw->phy.ops.acquire(hw); in e1000_post_phy_reset_ich8lan()
3174 ret_val = e1000_write_emi_reg_locked(hw, in e1000_post_phy_reset_ich8lan()
3177 hw->phy.ops.release(hw); in e1000_post_phy_reset_ich8lan()
3191 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) in e1000_phy_hw_reset_ich8lan() argument
3198 if ((hw->mac.type == e1000_pch2lan) && in e1000_phy_hw_reset_ich8lan()
3199 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) in e1000_phy_hw_reset_ich8lan()
3200 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); in e1000_phy_hw_reset_ich8lan()
3202 ret_val = e1000_phy_hw_reset_generic(hw); in e1000_phy_hw_reset_ich8lan()
3206 return e1000_post_phy_reset_ich8lan(hw); in e1000_phy_hw_reset_ich8lan()
3220 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) in e1000_set_lplu_state_pchlan() argument
3226 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); in e1000_set_lplu_state_pchlan()
3235 if (!hw->phy.ops.check_reset_block(hw)) in e1000_set_lplu_state_pchlan()
3238 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); in e1000_set_lplu_state_pchlan()
3254 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) in e1000_set_d0_lplu_state_ich8lan() argument
3256 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_ich8lan()
3266 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d0_lplu_state_ich8lan()
3270 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3278 if (hw->mac.type == e1000_ich8lan) in e1000_set_d0_lplu_state_ich8lan()
3279 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_set_d0_lplu_state_ich8lan()
3282 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3288 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3295 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3306 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3313 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3319 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3326 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3350 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) in e1000_set_d3_lplu_state_ich8lan() argument
3352 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_ich8lan()
3359 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d3_lplu_state_ich8lan()
3363 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3374 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3381 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3387 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3394 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3404 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3412 if (hw->mac.type == e1000_ich8lan) in e1000_set_d3_lplu_state_ich8lan()
3413 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_set_d3_lplu_state_ich8lan()
3416 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3423 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3439 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) in e1000_valid_nvm_bank_detect_ich8lan() argument
3442 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_valid_nvm_bank_detect_ich8lan()
3451 switch (hw->mac.type) { in e1000_valid_nvm_bank_detect_ich8lan()
3469 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, in e1000_valid_nvm_bank_detect_ich8lan()
3481 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + in e1000_valid_nvm_bank_detect_ich8lan()
3497 eecd = E1000_READ_REG(hw, E1000_EECD); in e1000_valid_nvm_bank_detect_ich8lan()
3514 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, in e1000_valid_nvm_bank_detect_ich8lan()
3525 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + in e1000_valid_nvm_bank_detect_ich8lan()
3550 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, in e1000_read_nvm_spt() argument
3553 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_spt()
3554 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_spt()
3571 nvm->ops.acquire(hw); in e1000_read_nvm_spt()
3573 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_read_nvm_spt()
3592 e1000_read_flash_dword_ich8lan(hw, in e1000_read_nvm_spt()
3607 e1000_read_flash_dword_ich8lan(hw, in e1000_read_nvm_spt()
3625 nvm->ops.release(hw); in e1000_read_nvm_spt()
3643 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, in e1000_read_nvm_ich8lan() argument
3646 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_ich8lan()
3647 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_ich8lan()
3662 nvm->ops.acquire(hw); in e1000_read_nvm_ich8lan()
3664 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_read_nvm_ich8lan()
3678 ret_val = e1000_read_flash_word_ich8lan(hw, in e1000_read_nvm_ich8lan()
3687 nvm->ops.release(hw); in e1000_read_nvm_ich8lan()
3703 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) in e1000_flash_cycle_init_ich8lan() argument
3710 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_flash_cycle_init_ich8lan()
3721 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3722 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3725 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
3741 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3742 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3745 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3755 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_flash_cycle_init_ich8lan()
3768 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3769 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3772 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3789 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) in e1000_flash_cycle_ich8lan() argument
3798 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3799 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; in e1000_flash_cycle_ich8lan()
3801 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); in e1000_flash_cycle_ich8lan()
3804 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3805 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_ich8lan()
3808 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); in e1000_flash_cycle_ich8lan()
3812 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_flash_cycle_ich8lan()
3833 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_dword_ich8lan() argument
3844 return e1000_read_flash_data32_ich8lan(hw, offset, data); in e1000_read_flash_dword_ich8lan()
3856 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_word_ich8lan() argument
3867 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); in e1000_read_flash_word_ich8lan()
3878 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_byte_ich8lan() argument
3887 if (hw->mac.type >= e1000_pch_spt) in e1000_read_flash_byte_ich8lan()
3890 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); in e1000_read_flash_byte_ich8lan()
3909 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_data_ich8lan() argument
3924 hw->nvm.flash_base_addr); in e1000_read_flash_data_ich8lan()
3929 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_read_flash_data_ich8lan()
3932 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); in e1000_read_flash_data_ich8lan()
3937 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); in e1000_read_flash_data_ich8lan()
3938 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_read_flash_data_ich8lan()
3940 ret_val = e1000_flash_cycle_ich8lan(hw, in e1000_read_flash_data_ich8lan()
3949 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); in e1000_read_flash_data_ich8lan()
3961 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_read_flash_data_ich8lan()
3984 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_data32_ich8lan() argument
3995 if (offset > ICH_FLASH_LINEAR_ADDR_MASK && hw->mac.type < e1000_pch_spt) in e1000_read_flash_data32_ich8lan()
3998 hw->nvm.flash_base_addr); in e1000_read_flash_data32_ich8lan()
4003 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_read_flash_data32_ich8lan()
4009 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; in e1000_read_flash_data32_ich8lan()
4017 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_read_flash_data32_ich8lan()
4019 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_read_flash_data32_ich8lan()
4021 ret_val = e1000_flash_cycle_ich8lan(hw, in e1000_read_flash_data32_ich8lan()
4030 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); in e1000_read_flash_data32_ich8lan()
4038 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_read_flash_data32_ich8lan()
4062 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, in e1000_write_nvm_ich8lan() argument
4065 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_write_nvm_ich8lan()
4066 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_write_nvm_ich8lan()
4077 nvm->ops.acquire(hw); in e1000_write_nvm_ich8lan()
4084 nvm->ops.release(hw); in e1000_write_nvm_ich8lan()
4100 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) in e1000_update_nvm_checksum_spt() argument
4102 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_spt()
4103 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_spt()
4110 ret_val = e1000_update_nvm_checksum_generic(hw); in e1000_update_nvm_checksum_spt()
4117 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_spt()
4123 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_update_nvm_checksum_spt()
4132 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); in e1000_update_nvm_checksum_spt()
4138 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); in e1000_update_nvm_checksum_spt()
4147 ret_val = e1000_read_flash_dword_ich8lan(hw, in e1000_update_nvm_checksum_spt()
4180 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, in e1000_update_nvm_checksum_spt()
4203 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); in e1000_update_nvm_checksum_spt()
4209 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); in e1000_update_nvm_checksum_spt()
4223 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); in e1000_update_nvm_checksum_spt()
4229 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); in e1000_update_nvm_checksum_spt()
4241 nvm->ops.release(hw); in e1000_update_nvm_checksum_spt()
4247 nvm->ops.reload(hw); in e1000_update_nvm_checksum_spt()
4269 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) in e1000_update_nvm_checksum_ich8lan() argument
4271 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_ich8lan()
4272 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_ich8lan()
4279 ret_val = e1000_update_nvm_checksum_generic(hw); in e1000_update_nvm_checksum_ich8lan()
4286 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_ich8lan()
4292 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_update_nvm_checksum_ich8lan()
4301 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); in e1000_update_nvm_checksum_ich8lan()
4307 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); in e1000_update_nvm_checksum_ich8lan()
4315 ret_val = e1000_read_flash_word_ich8lan(hw, i + in e1000_update_nvm_checksum_ich8lan()
4337 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, in e1000_update_nvm_checksum_ich8lan()
4344 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, in e1000_update_nvm_checksum_ich8lan()
4365 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); in e1000_update_nvm_checksum_ich8lan()
4370 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1, in e1000_update_nvm_checksum_ich8lan()
4382 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); in e1000_update_nvm_checksum_ich8lan()
4394 nvm->ops.release(hw); in e1000_update_nvm_checksum_ich8lan()
4400 nvm->ops.reload(hw); in e1000_update_nvm_checksum_ich8lan()
4419 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) in e1000_validate_nvm_checksum_ich8lan() argument
4433 switch (hw->mac.type) { in e1000_validate_nvm_checksum_ich8lan()
4454 ret_val = hw->nvm.ops.read(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4460 ret_val = hw->nvm.ops.write(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4463 ret_val = hw->nvm.ops.update(hw); in e1000_validate_nvm_checksum_ich8lan()
4468 return e1000_validate_nvm_checksum_generic(hw); in e1000_validate_nvm_checksum_ich8lan()
4480 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_data_ich8lan() argument
4492 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data_ich8lan()
4501 hw->nvm.flash_base_addr); in e1000_write_flash_data_ich8lan()
4506 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_write_flash_data_ich8lan()
4512 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4514 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS) >> 16; in e1000_write_flash_data_ich8lan()
4517 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); in e1000_write_flash_data_ich8lan()
4526 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4527 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_write_flash_data_ich8lan()
4530 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, in e1000_write_flash_data_ich8lan()
4533 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_write_flash_data_ich8lan()
4540 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); in e1000_write_flash_data_ich8lan()
4546 e1000_flash_cycle_ich8lan(hw, in e1000_write_flash_data_ich8lan()
4556 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_write_flash_data_ich8lan()
4577 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_data32_ich8lan() argument
4588 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data32_ich8lan()
4593 hw->nvm.flash_base_addr); in e1000_write_flash_data32_ich8lan()
4597 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_write_flash_data32_ich8lan()
4604 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4605 hsflctl.regval = E1000_READ_FLASH_REG(hw, in e1000_write_flash_data32_ich8lan()
4609 hsflctl.regval = E1000_READ_FLASH_REG16(hw, in e1000_write_flash_data32_ich8lan()
4619 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4620 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_write_flash_data32_ich8lan()
4623 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, in e1000_write_flash_data32_ich8lan()
4626 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_write_flash_data32_ich8lan()
4628 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data); in e1000_write_flash_data32_ich8lan()
4633 ret_val = e1000_flash_cycle_ich8lan(hw, in e1000_write_flash_data32_ich8lan()
4644 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_write_flash_data32_ich8lan()
4666 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_byte_ich8lan() argument
4673 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); in e1000_write_flash_byte_ich8lan()
4685 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, in e1000_retry_write_flash_dword_ich8lan() argument
4696 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); in e1000_retry_write_flash_dword_ich8lan()
4703 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); in e1000_retry_write_flash_dword_ich8lan()
4722 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, in e1000_retry_write_flash_byte_ich8lan() argument
4730 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); in e1000_retry_write_flash_byte_ich8lan()
4737 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); in e1000_retry_write_flash_byte_ich8lan()
4755 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) in e1000_erase_flash_bank_ich8lan() argument
4757 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_erase_flash_bank_ich8lan()
4769 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_erase_flash_bank_ich8lan()
4806 flash_linear_addr = hw->nvm.flash_base_addr; in e1000_erase_flash_bank_ich8lan()
4814 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_erase_flash_bank_ich8lan()
4821 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4823 E1000_READ_FLASH_REG(hw, in e1000_erase_flash_bank_ich8lan()
4827 E1000_READ_FLASH_REG16(hw, in e1000_erase_flash_bank_ich8lan()
4831 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4832 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_erase_flash_bank_ich8lan()
4835 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, in e1000_erase_flash_bank_ich8lan()
4843 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, in e1000_erase_flash_bank_ich8lan()
4846 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); in e1000_erase_flash_bank_ich8lan()
4854 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_erase_flash_bank_ich8lan()
4876 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) in e1000_valid_led_default_ich8lan() argument
4882 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_ich8lan()
4907 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) in e1000_id_led_init_pchlan() argument
4909 struct e1000_mac_info *mac = &hw->mac; in e1000_id_led_init_pchlan()
4918 ret_val = hw->nvm.ops.valid_led_default(hw, &data); in e1000_id_led_init_pchlan()
4922 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); in e1000_id_led_init_pchlan()
4975 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) in e1000_get_bus_info_ich8lan() argument
4977 struct e1000_bus_info *bus = &hw->bus; in e1000_get_bus_info_ich8lan()
4982 ret_val = e1000_get_bus_info_pcie_generic(hw); in e1000_get_bus_info_ich8lan()
5002 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) in e1000_reset_hw_ich8lan() argument
5004 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_reset_hw_ich8lan()
5014 ret_val = e1000_disable_pcie_master_generic(hw); in e1000_reset_hw_ich8lan()
5019 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_ich8lan()
5025 E1000_WRITE_REG(hw, E1000_RCTL, 0); in e1000_reset_hw_ich8lan()
5026 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); in e1000_reset_hw_ich8lan()
5027 E1000_WRITE_FLUSH(hw); in e1000_reset_hw_ich8lan()
5032 if (hw->mac.type == e1000_ich8lan) { in e1000_reset_hw_ich8lan()
5034 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); in e1000_reset_hw_ich8lan()
5036 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); in e1000_reset_hw_ich8lan()
5039 if (hw->mac.type == e1000_pchlan) { in e1000_reset_hw_ich8lan()
5041 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); in e1000_reset_hw_ich8lan()
5051 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_reset_hw_ich8lan()
5053 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_reset_hw_ich8lan()
5063 if ((hw->mac.type == e1000_pch2lan) && in e1000_reset_hw_ich8lan()
5064 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) in e1000_reset_hw_ich8lan()
5065 e1000_gate_hw_phy_config_ich8lan(hw, TRUE); in e1000_reset_hw_ich8lan()
5067 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_reset_hw_ich8lan()
5069 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw_ich8lan()
5074 if (hw->mac.type == e1000_pch2lan) { in e1000_reset_hw_ich8lan()
5075 reg = E1000_READ_REG(hw, E1000_FEXTNVM3); in e1000_reset_hw_ich8lan()
5078 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); in e1000_reset_hw_ich8lan()
5082 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); in e1000_reset_hw_ich8lan()
5085 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_reset_hw_ich8lan()
5089 ret_val = e1000_post_phy_reset_ich8lan(hw); in e1000_reset_hw_ich8lan()
5098 if (hw->mac.type == e1000_pchlan) in e1000_reset_hw_ich8lan()
5099 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); in e1000_reset_hw_ich8lan()
5101 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_ich8lan()
5102 E1000_READ_REG(hw, E1000_ICR); in e1000_reset_hw_ich8lan()
5104 reg = E1000_READ_REG(hw, E1000_KABGTXD); in e1000_reset_hw_ich8lan()
5106 E1000_WRITE_REG(hw, E1000_KABGTXD, reg); in e1000_reset_hw_ich8lan()
5123 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) in e1000_init_hw_ich8lan() argument
5125 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_ich8lan()
5132 e1000_initialize_hw_bits_ich8lan(hw); in e1000_init_hw_ich8lan()
5135 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_ich8lan()
5141 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); in e1000_init_hw_ich8lan()
5146 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); in e1000_init_hw_ich8lan()
5152 if (hw->phy.type == e1000_phy_82578) { in e1000_init_hw_ich8lan()
5153 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); in e1000_init_hw_ich8lan()
5155 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); in e1000_init_hw_ich8lan()
5156 ret_val = e1000_phy_hw_reset_ich8lan(hw); in e1000_init_hw_ich8lan()
5162 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_ich8lan()
5165 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_ich8lan()
5170 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); in e1000_init_hw_ich8lan()
5171 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_init_hw_ich8lan()
5176 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); in e1000_init_hw_ich8lan()
5185 e1000_set_pcie_no_snoop_generic(hw, snoop); in e1000_init_hw_ich8lan()
5187 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_init_hw_ich8lan()
5189 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_init_hw_ich8lan()
5196 e1000_clear_hw_cntrs_ich8lan(hw); in e1000_init_hw_ich8lan()
5208 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) in e1000_initialize_hw_bits_ich8lan() argument
5215 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_initialize_hw_bits_ich8lan()
5218 if (hw->mac.type >= e1000_pchlan) in e1000_initialize_hw_bits_ich8lan()
5220 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); in e1000_initialize_hw_bits_ich8lan()
5223 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_initialize_hw_bits_ich8lan()
5225 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); in e1000_initialize_hw_bits_ich8lan()
5228 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_initialize_hw_bits_ich8lan()
5230 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); in e1000_initialize_hw_bits_ich8lan()
5233 reg = E1000_READ_REG(hw, E1000_TARC(0)); in e1000_initialize_hw_bits_ich8lan()
5234 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5237 E1000_WRITE_REG(hw, E1000_TARC(0), reg); in e1000_initialize_hw_bits_ich8lan()
5240 reg = E1000_READ_REG(hw, E1000_TARC(1)); in e1000_initialize_hw_bits_ich8lan()
5241 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) in e1000_initialize_hw_bits_ich8lan()
5246 E1000_WRITE_REG(hw, E1000_TARC(1), reg); in e1000_initialize_hw_bits_ich8lan()
5249 if (hw->mac.type == e1000_ich8lan) { in e1000_initialize_hw_bits_ich8lan()
5250 reg = E1000_READ_REG(hw, E1000_STATUS); in e1000_initialize_hw_bits_ich8lan()
5252 E1000_WRITE_REG(hw, E1000_STATUS, reg); in e1000_initialize_hw_bits_ich8lan()
5258 reg = E1000_READ_REG(hw, E1000_RFCTL); in e1000_initialize_hw_bits_ich8lan()
5264 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5266 E1000_WRITE_REG(hw, E1000_RFCTL, reg); in e1000_initialize_hw_bits_ich8lan()
5269 if (hw->mac.type >= e1000_pch_lpt) { in e1000_initialize_hw_bits_ich8lan()
5270 reg = E1000_READ_REG(hw, E1000_PBECCSTS); in e1000_initialize_hw_bits_ich8lan()
5272 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); in e1000_initialize_hw_bits_ich8lan()
5274 reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_initialize_hw_bits_ich8lan()
5276 E1000_WRITE_REG(hw, E1000_CTRL, reg); in e1000_initialize_hw_bits_ich8lan()
5292 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) in e1000_setup_link_ich8lan() argument
5298 if (hw->phy.ops.check_reset_block(hw)) in e1000_setup_link_ich8lan()
5305 if (hw->fc.requested_mode == e1000_fc_default) in e1000_setup_link_ich8lan()
5306 hw->fc.requested_mode = e1000_fc_full; in e1000_setup_link_ich8lan()
5311 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_ich8lan()
5314 hw->fc.current_mode); in e1000_setup_link_ich8lan()
5317 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_ich8lan()
5321 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); in e1000_setup_link_ich8lan()
5322 if ((hw->phy.type == e1000_phy_82578) || in e1000_setup_link_ich8lan()
5323 (hw->phy.type == e1000_phy_82579) || in e1000_setup_link_ich8lan()
5324 (hw->phy.type == e1000_phy_i217) || in e1000_setup_link_ich8lan()
5325 (hw->phy.type == e1000_phy_82577)) { in e1000_setup_link_ich8lan()
5326 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); in e1000_setup_link_ich8lan()
5328 ret_val = hw->phy.ops.write_reg(hw, in e1000_setup_link_ich8lan()
5330 hw->fc.pause_time); in e1000_setup_link_ich8lan()
5335 return e1000_set_fc_watermarks_generic(hw); in e1000_setup_link_ich8lan()
5346 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) in e1000_setup_copper_link_ich8lan() argument
5354 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_setup_copper_link_ich8lan()
5357 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); in e1000_setup_copper_link_ich8lan()
5363 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, in e1000_setup_copper_link_ich8lan()
5367 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_setup_copper_link_ich8lan()
5373 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_setup_copper_link_ich8lan()
5379 switch (hw->phy.type) { in e1000_setup_copper_link_ich8lan()
5381 ret_val = e1000_copper_link_setup_igp(hw); in e1000_setup_copper_link_ich8lan()
5387 ret_val = e1000_copper_link_setup_m88(hw); in e1000_setup_copper_link_ich8lan()
5393 ret_val = e1000_copper_link_setup_82577(hw); in e1000_setup_copper_link_ich8lan()
5398 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, in e1000_setup_copper_link_ich8lan()
5405 switch (hw->phy.mdix) { in e1000_setup_copper_link_ich8lan()
5417 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, in e1000_setup_copper_link_ich8lan()
5426 return e1000_setup_copper_link_generic(hw); in e1000_setup_copper_link_ich8lan()
5437 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) in e1000_setup_copper_link_pch_lpt() argument
5444 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_setup_copper_link_pch_lpt()
5447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); in e1000_setup_copper_link_pch_lpt()
5449 ret_val = e1000_copper_link_setup_82577(hw); in e1000_setup_copper_link_pch_lpt()
5453 return e1000_setup_copper_link_generic(hw); in e1000_setup_copper_link_pch_lpt()
5466 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, in e1000_get_link_up_info_ich8lan() argument
5473 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); in e1000_get_link_up_info_ich8lan()
5477 if ((hw->mac.type == e1000_ich8lan) && in e1000_get_link_up_info_ich8lan()
5478 (hw->phy.type == e1000_phy_igp_3) && in e1000_get_link_up_info_ich8lan()
5480 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); in e1000_get_link_up_info_ich8lan()
5501 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) in e1000_kmrn_lock_loss_workaround_ich8lan() argument
5503 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_kmrn_lock_loss_workaround_ich8lan()
5518 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); in e1000_kmrn_lock_loss_workaround_ich8lan()
5524 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5528 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5537 hw->phy.ops.reset(hw); in e1000_kmrn_lock_loss_workaround_ich8lan()
5541 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_kmrn_lock_loss_workaround_ich8lan()
5544 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_kmrn_lock_loss_workaround_ich8lan()
5549 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_kmrn_lock_loss_workaround_ich8lan()
5563 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, in e1000_set_kmrn_lock_loss_workaround_ich8lan() argument
5566 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_kmrn_lock_loss_workaround_ich8lan()
5570 if (hw->mac.type != e1000_ich8lan) { in e1000_set_kmrn_lock_loss_workaround_ich8lan()
5590 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) in e1000_igp3_phy_powerdown_workaround_ich8lan() argument
5598 if (hw->phy.type != e1000_phy_igp_3) in e1000_igp3_phy_powerdown_workaround_ich8lan()
5604 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5607 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5612 if (hw->mac.type == e1000_ich8lan) in e1000_igp3_phy_powerdown_workaround_ich8lan()
5613 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5616 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5618 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, in e1000_igp3_phy_powerdown_workaround_ich8lan()
5622 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5628 reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5629 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5644 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) in e1000_gig_downshift_workaround_ich8lan() argument
5651 if ((hw->mac.type != e1000_ich8lan) || in e1000_gig_downshift_workaround_ich8lan()
5652 (hw->phy.type == e1000_phy_ife)) in e1000_gig_downshift_workaround_ich8lan()
5655 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, in e1000_gig_downshift_workaround_ich8lan()
5660 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_gig_downshift_workaround_ich8lan()
5666 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, in e1000_gig_downshift_workaround_ich8lan()
5684 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) in e1000_suspend_workarounds_ich8lan() argument
5686 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_suspend_workarounds_ich8lan()
5692 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_suspend_workarounds_ich8lan()
5695 if (hw->phy.type == e1000_phy_i217) { in e1000_suspend_workarounds_ich8lan()
5696 u16 phy_reg, device_id = hw->device_id; in e1000_suspend_workarounds_ich8lan()
5702 (hw->mac.type >= e1000_pch_spt)) { in e1000_suspend_workarounds_ich8lan()
5703 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); in e1000_suspend_workarounds_ich8lan()
5705 E1000_WRITE_REG(hw, E1000_FEXTNVM6, in e1000_suspend_workarounds_ich8lan()
5709 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5717 e1000_read_emi_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5731 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { in e1000_suspend_workarounds_ich8lan()
5736 hw->phy.ops.read_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5740 hw->phy.ops.write_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5753 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_suspend_workarounds_ich8lan()
5756 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, in e1000_suspend_workarounds_ich8lan()
5759 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, in e1000_suspend_workarounds_ich8lan()
5765 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5767 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); in e1000_suspend_workarounds_ich8lan()
5770 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5772 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); in e1000_suspend_workarounds_ich8lan()
5778 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5780 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); in e1000_suspend_workarounds_ich8lan()
5783 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5786 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_suspend_workarounds_ich8lan()
5788 if (hw->mac.type == e1000_ich8lan) in e1000_suspend_workarounds_ich8lan()
5789 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_suspend_workarounds_ich8lan()
5791 if (hw->mac.type >= e1000_pchlan) { in e1000_suspend_workarounds_ich8lan()
5792 e1000_oem_bits_config_ich8lan(hw, FALSE); in e1000_suspend_workarounds_ich8lan()
5795 if (hw->mac.type == e1000_pchlan) in e1000_suspend_workarounds_ich8lan()
5796 e1000_phy_hw_reset_generic(hw); in e1000_suspend_workarounds_ich8lan()
5798 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5801 e1000_write_smbus_addr(hw); in e1000_suspend_workarounds_ich8lan()
5802 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5818 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw) in e1000_resume_workarounds_pchlan() argument
5823 if (hw->mac.type < e1000_pch2lan) in e1000_resume_workarounds_pchlan()
5826 ret_val = e1000_init_phy_workarounds_pchlan(hw); in e1000_resume_workarounds_pchlan()
5837 if (hw->phy.type == e1000_phy_i217) { in e1000_resume_workarounds_pchlan()
5840 ret_val = hw->phy.ops.acquire(hw); in e1000_resume_workarounds_pchlan()
5847 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); in e1000_resume_workarounds_pchlan()
5849 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); in e1000_resume_workarounds_pchlan()
5851 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_resume_workarounds_pchlan()
5856 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, in e1000_resume_workarounds_pchlan()
5861 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); in e1000_resume_workarounds_pchlan()
5864 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); in e1000_resume_workarounds_pchlan()
5867 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, in e1000_resume_workarounds_pchlan()
5872 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); in e1000_resume_workarounds_pchlan()
5876 hw->phy.ops.release(hw); in e1000_resume_workarounds_pchlan()
5888 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) in e1000_cleanup_led_ich8lan() argument
5892 if (hw->phy.type == e1000_phy_ife) in e1000_cleanup_led_ich8lan()
5893 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_cleanup_led_ich8lan()
5896 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); in e1000_cleanup_led_ich8lan()
5906 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) in e1000_led_on_ich8lan() argument
5910 if (hw->phy.type == e1000_phy_ife) in e1000_led_on_ich8lan()
5911 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_on_ich8lan()
5914 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); in e1000_led_on_ich8lan()
5924 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) in e1000_led_off_ich8lan() argument
5928 if (hw->phy.type == e1000_phy_ife) in e1000_led_off_ich8lan()
5929 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_off_ich8lan()
5932 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); in e1000_led_off_ich8lan()
5942 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) in e1000_setup_led_pchlan() argument
5946 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, in e1000_setup_led_pchlan()
5947 (u16)hw->mac.ledctl_mode1); in e1000_setup_led_pchlan()
5956 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) in e1000_cleanup_led_pchlan() argument
5960 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, in e1000_cleanup_led_pchlan()
5961 (u16)hw->mac.ledctl_default); in e1000_cleanup_led_pchlan()
5970 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) in e1000_led_on_pchlan() argument
5972 u16 data = (u16)hw->mac.ledctl_mode2; in e1000_led_on_pchlan()
5980 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { in e1000_led_on_pchlan()
5993 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); in e1000_led_on_pchlan()
6002 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) in e1000_led_off_pchlan() argument
6004 u16 data = (u16)hw->mac.ledctl_mode1; in e1000_led_off_pchlan()
6012 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { in e1000_led_off_pchlan()
6025 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); in e1000_led_off_pchlan()
6040 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) in e1000_get_cfg_done_ich8lan() argument
6048 e1000_get_cfg_done_generic(hw); in e1000_get_cfg_done_ich8lan()
6051 if (hw->mac.type >= e1000_ich10lan) { in e1000_get_cfg_done_ich8lan()
6052 e1000_lan_init_done_ich8lan(hw); in e1000_get_cfg_done_ich8lan()
6054 ret_val = e1000_get_auto_rd_done_generic(hw); in e1000_get_cfg_done_ich8lan()
6066 status = E1000_READ_REG(hw, E1000_STATUS); in e1000_get_cfg_done_ich8lan()
6068 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); in e1000_get_cfg_done_ich8lan()
6073 if (hw->mac.type <= e1000_ich9lan) { in e1000_get_cfg_done_ich8lan()
6074 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && in e1000_get_cfg_done_ich8lan()
6075 (hw->phy.type == e1000_phy_igp_3)) { in e1000_get_cfg_done_ich8lan()
6076 e1000_phy_init_script_igp3(hw); in e1000_get_cfg_done_ich8lan()
6079 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { in e1000_get_cfg_done_ich8lan()
6096 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) in e1000_power_down_phy_copper_ich8lan() argument
6099 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_ich8lan()
6100 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_ich8lan()
6101 e1000_power_down_phy_copper(hw); in e1000_power_down_phy_copper_ich8lan()
6113 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) in e1000_clear_hw_cntrs_ich8lan() argument
6120 e1000_clear_hw_cntrs_base_generic(hw); in e1000_clear_hw_cntrs_ich8lan()
6122 E1000_READ_REG(hw, E1000_ALGNERRC); in e1000_clear_hw_cntrs_ich8lan()
6123 E1000_READ_REG(hw, E1000_RXERRC); in e1000_clear_hw_cntrs_ich8lan()
6124 E1000_READ_REG(hw, E1000_TNCRS); in e1000_clear_hw_cntrs_ich8lan()
6125 E1000_READ_REG(hw, E1000_CEXTERR); in e1000_clear_hw_cntrs_ich8lan()
6126 E1000_READ_REG(hw, E1000_TSCTC); in e1000_clear_hw_cntrs_ich8lan()
6127 E1000_READ_REG(hw, E1000_TSCTFC); in e1000_clear_hw_cntrs_ich8lan()
6129 E1000_READ_REG(hw, E1000_MGTPRC); in e1000_clear_hw_cntrs_ich8lan()
6130 E1000_READ_REG(hw, E1000_MGTPDC); in e1000_clear_hw_cntrs_ich8lan()
6131 E1000_READ_REG(hw, E1000_MGTPTC); in e1000_clear_hw_cntrs_ich8lan()
6133 E1000_READ_REG(hw, E1000_IAC); in e1000_clear_hw_cntrs_ich8lan()
6134 E1000_READ_REG(hw, E1000_ICRXOC); in e1000_clear_hw_cntrs_ich8lan()
6137 if ((hw->phy.type == e1000_phy_82578) || in e1000_clear_hw_cntrs_ich8lan()
6138 (hw->phy.type == e1000_phy_82579) || in e1000_clear_hw_cntrs_ich8lan()
6139 (hw->phy.type == e1000_phy_i217) || in e1000_clear_hw_cntrs_ich8lan()
6140 (hw->phy.type == e1000_phy_82577)) { in e1000_clear_hw_cntrs_ich8lan()
6141 ret_val = hw->phy.ops.acquire(hw); in e1000_clear_hw_cntrs_ich8lan()
6144 ret_val = hw->phy.ops.set_page(hw, in e1000_clear_hw_cntrs_ich8lan()
6148 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6149 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6150 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6151 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6152 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6153 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6154 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6155 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6156 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6157 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6158 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6159 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6160 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6161 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6163 hw->phy.ops.release(hw); in e1000_clear_hw_cntrs_ich8lan()