Lines Matching refs:hw
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51 static void e1000_release_phy_82575(struct e1000_hw *hw);
52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
55 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
56 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
57 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
107 static void e1000_i2c_start(struct e1000_hw *hw);
108 static void e1000_i2c_stop(struct e1000_hw *hw);
109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
133 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) in e1000_sgmii_uses_mdio_82575() argument
140 switch (hw->mac.type) { in e1000_sgmii_uses_mdio_82575()
143 reg = E1000_READ_REG(hw, E1000_MDIC); in e1000_sgmii_uses_mdio_82575()
151 reg = E1000_READ_REG(hw, E1000_MDICNFG); in e1000_sgmii_uses_mdio_82575()
164 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) in e1000_init_phy_params_82575() argument
166 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82575()
175 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82575()
192 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_init_phy_params_82575()
194 if (e1000_sgmii_active_82575(hw)) { in e1000_init_phy_params_82575()
202 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_init_phy_params_82575()
203 e1000_reset_mdicnfg_82580(hw); in e1000_init_phy_params_82575()
205 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { in e1000_init_phy_params_82575()
209 switch (hw->mac.type) { in e1000_init_phy_params_82575()
228 ret_val = e1000_get_phy_id_82575(hw); in e1000_init_phy_params_82575()
257 ret_val = phy->ops.write_reg(hw, in e1000_init_phy_params_82575()
263 ret_val = phy->ops.read_reg(hw, in e1000_init_phy_params_82575()
273 hw->mac.ops.check_for_link = in e1000_init_phy_params_82575()
277 ret_val = e1000_initialize_M88E1512_phy(hw); in e1000_init_phy_params_82575()
282 ret_val = e1000_initialize_M88E1543_phy(hw); in e1000_init_phy_params_82575()
330 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) in e1000_init_nvm_params_82575() argument
332 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_82575()
333 u32 eecd = E1000_READ_REG(hw, E1000_EECD); in e1000_init_nvm_params_82575()
353 if (hw->mac.type < e1000_i210) { in e1000_init_nvm_params_82575()
394 switch (hw->mac.type) { in e1000_init_nvm_params_82575()
415 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) in e1000_init_mac_params_82575() argument
417 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_82575()
418 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_init_mac_params_82575()
423 e1000_get_media_type_82575(hw); in e1000_init_mac_params_82575()
427 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; in e1000_init_mac_params_82575()
451 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); in e1000_init_mac_params_82575()
471 (hw->phy.media_type == e1000_media_type_copper) in e1000_init_mac_params_82575()
485 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) { in e1000_init_mac_params_82575()
496 if (hw->mac.type >= e1000_82580) in e1000_init_mac_params_82575()
523 hw->mac.ops.set_lan_id(hw); in e1000_init_mac_params_82575()
534 void e1000_init_function_pointers_82575(struct e1000_hw *hw) in e1000_init_function_pointers_82575() argument
538 hw->mac.ops.init_params = e1000_init_mac_params_82575; in e1000_init_function_pointers_82575()
539 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; in e1000_init_function_pointers_82575()
540 hw->phy.ops.init_params = e1000_init_phy_params_82575; in e1000_init_function_pointers_82575()
541 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; in e1000_init_function_pointers_82575()
550 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) in e1000_acquire_phy_82575() argument
556 if (hw->bus.func == E1000_FUNC_1) in e1000_acquire_phy_82575()
558 else if (hw->bus.func == E1000_FUNC_2) in e1000_acquire_phy_82575()
560 else if (hw->bus.func == E1000_FUNC_3) in e1000_acquire_phy_82575()
563 return hw->mac.ops.acquire_swfw_sync(hw, mask); in e1000_acquire_phy_82575()
572 static void e1000_release_phy_82575(struct e1000_hw *hw) in e1000_release_phy_82575() argument
578 if (hw->bus.func == E1000_FUNC_1) in e1000_release_phy_82575()
580 else if (hw->bus.func == E1000_FUNC_2) in e1000_release_phy_82575()
582 else if (hw->bus.func == E1000_FUNC_3) in e1000_release_phy_82575()
585 hw->mac.ops.release_swfw_sync(hw, mask); in e1000_release_phy_82575()
597 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, in e1000_read_phy_reg_sgmii_82575() argument
609 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_sgmii_82575()
613 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); in e1000_read_phy_reg_sgmii_82575()
615 hw->phy.ops.release(hw); in e1000_read_phy_reg_sgmii_82575()
630 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, in e1000_write_phy_reg_sgmii_82575() argument
642 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_sgmii_82575()
646 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); in e1000_write_phy_reg_sgmii_82575()
648 hw->phy.ops.release(hw); in e1000_write_phy_reg_sgmii_82575()
661 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) in e1000_get_phy_id_82575() argument
663 struct e1000_phy_info *phy = &hw->phy; in e1000_get_phy_id_82575()
672 if (hw->mac.type == e1000_i354) in e1000_get_phy_id_82575()
673 e1000_get_phy_id(hw); in e1000_get_phy_id_82575()
682 if (!e1000_sgmii_active_82575(hw)) { in e1000_get_phy_id_82575()
684 ret_val = e1000_get_phy_id(hw); in e1000_get_phy_id_82575()
688 if (e1000_sgmii_uses_mdio_82575(hw)) { in e1000_get_phy_id_82575()
689 switch (hw->mac.type) { in e1000_get_phy_id_82575()
692 mdic = E1000_READ_REG(hw, E1000_MDIC); in e1000_get_phy_id_82575()
701 mdic = E1000_READ_REG(hw, E1000_MDICNFG); in e1000_get_phy_id_82575()
710 ret_val = e1000_get_phy_id(hw); in e1000_get_phy_id_82575()
715 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_get_phy_id_82575()
716 E1000_WRITE_REG(hw, E1000_CTRL_EXT, in e1000_get_phy_id_82575()
718 E1000_WRITE_FLUSH(hw); in e1000_get_phy_id_82575()
726 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); in e1000_get_phy_id_82575()
747 ret_val = e1000_get_phy_id(hw); in e1000_get_phy_id_82575()
751 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_get_phy_id_82575()
763 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) in e1000_phy_hw_reset_sgmii_82575() argument
766 struct e1000_phy_info *phy = &hw->phy; in e1000_phy_hw_reset_sgmii_82575()
777 if (!(hw->phy.ops.write_reg)) in e1000_phy_hw_reset_sgmii_82575()
784 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in e1000_phy_hw_reset_sgmii_82575()
788 ret_val = hw->phy.ops.commit(hw); in e1000_phy_hw_reset_sgmii_82575()
793 ret_val = e1000_initialize_M88E1512_phy(hw); in e1000_phy_hw_reset_sgmii_82575()
811 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) in e1000_set_d0_lplu_state_82575() argument
813 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_82575()
819 if (!(hw->phy.ops.read_reg)) in e1000_set_d0_lplu_state_82575()
822 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); in e1000_set_d0_lplu_state_82575()
828 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
834 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82575()
837 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82575()
843 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
852 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_82575()
859 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82575()
865 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_82575()
872 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82575()
897 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) in e1000_set_d0_lplu_state_82580() argument
899 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_82580()
904 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); in e1000_set_d0_lplu_state_82580()
926 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); in e1000_set_d0_lplu_state_82580()
944 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) in e1000_set_d3_lplu_state_82580() argument
946 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_82580()
951 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); in e1000_set_d3_lplu_state_82580()
973 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); in e1000_set_d3_lplu_state_82580()
986 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) in e1000_acquire_nvm_82575() argument
992 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); in e1000_acquire_nvm_82575()
1000 if (hw->mac.type == e1000_i350) { in e1000_acquire_nvm_82575()
1001 u32 eecd = E1000_READ_REG(hw, E1000_EECD); in e1000_acquire_nvm_82575()
1005 E1000_WRITE_REG(hw, E1000_EECD, eecd | in e1000_acquire_nvm_82575()
1011 if (hw->mac.type == e1000_82580) { in e1000_acquire_nvm_82575()
1012 u32 eecd = E1000_READ_REG(hw, E1000_EECD); in e1000_acquire_nvm_82575()
1015 E1000_WRITE_REG(hw, E1000_EECD, eecd | in e1000_acquire_nvm_82575()
1021 ret_val = e1000_acquire_nvm_generic(hw); in e1000_acquire_nvm_82575()
1023 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); in e1000_acquire_nvm_82575()
1036 static void e1000_release_nvm_82575(struct e1000_hw *hw) in e1000_release_nvm_82575() argument
1040 e1000_release_nvm_generic(hw); in e1000_release_nvm_82575()
1042 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); in e1000_release_nvm_82575()
1053 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) in e1000_acquire_swfw_sync_82575() argument
1064 if (e1000_get_hw_semaphore_generic(hw)) { in e1000_acquire_swfw_sync_82575()
1069 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); in e1000_acquire_swfw_sync_82575()
1077 e1000_put_hw_semaphore_generic(hw); in e1000_acquire_swfw_sync_82575()
1089 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); in e1000_acquire_swfw_sync_82575()
1091 e1000_put_hw_semaphore_generic(hw); in e1000_acquire_swfw_sync_82575()
1105 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) in e1000_release_swfw_sync_82575() argument
1111 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) in e1000_release_swfw_sync_82575()
1114 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); in e1000_release_swfw_sync_82575()
1116 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); in e1000_release_swfw_sync_82575()
1118 e1000_put_hw_semaphore_generic(hw); in e1000_release_swfw_sync_82575()
1131 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) in e1000_get_cfg_done_82575() argument
1138 if (hw->bus.func == E1000_FUNC_1) in e1000_get_cfg_done_82575()
1140 else if (hw->bus.func == E1000_FUNC_2) in e1000_get_cfg_done_82575()
1142 else if (hw->bus.func == E1000_FUNC_3) in e1000_get_cfg_done_82575()
1145 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) in e1000_get_cfg_done_82575()
1154 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && in e1000_get_cfg_done_82575()
1155 (hw->phy.type == e1000_phy_igp_3)) in e1000_get_cfg_done_82575()
1156 e1000_phy_init_script_igp3(hw); in e1000_get_cfg_done_82575()
1171 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, in e1000_get_link_up_info_82575() argument
1178 if (hw->phy.media_type != e1000_media_type_copper) in e1000_get_link_up_info_82575()
1179 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, in e1000_get_link_up_info_82575()
1182 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, in e1000_get_link_up_info_82575()
1195 static s32 e1000_check_for_link_82575(struct e1000_hw *hw) in e1000_check_for_link_82575() argument
1202 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_check_for_link_82575()
1203 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, in e1000_check_for_link_82575()
1210 hw->mac.get_link_status = !hw->mac.serdes_has_link; in e1000_check_for_link_82575()
1218 ret_val = e1000_config_fc_after_link_up_generic(hw); in e1000_check_for_link_82575()
1222 ret_val = e1000_check_for_copper_link_generic(hw); in e1000_check_for_link_82575()
1234 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw) in e1000_check_for_link_media_swap() argument
1236 struct e1000_phy_info *phy = &hw->phy; in e1000_check_for_link_media_swap()
1244 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in e1000_check_for_link_media_swap()
1248 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in e1000_check_for_link_media_swap()
1256 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); in e1000_check_for_link_media_swap()
1260 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in e1000_check_for_link_media_swap()
1268 if (port && (hw->dev_spec._82575.media_port != port)) { in e1000_check_for_link_media_swap()
1269 hw->dev_spec._82575.media_port = port; in e1000_check_for_link_media_swap()
1270 hw->dev_spec._82575.media_changed = TRUE; in e1000_check_for_link_media_swap()
1275 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in e1000_check_for_link_media_swap()
1278 e1000_check_for_link_82575(hw); in e1000_check_for_link_media_swap()
1280 e1000_check_for_link_82575(hw); in e1000_check_for_link_media_swap()
1282 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in e1000_check_for_link_media_swap()
1294 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) in e1000_power_up_serdes_link_82575() argument
1300 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in e1000_power_up_serdes_link_82575()
1301 !e1000_sgmii_active_82575(hw)) in e1000_power_up_serdes_link_82575()
1305 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); in e1000_power_up_serdes_link_82575()
1307 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); in e1000_power_up_serdes_link_82575()
1310 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_power_up_serdes_link_82575()
1312 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); in e1000_power_up_serdes_link_82575()
1315 E1000_WRITE_FLUSH(hw); in e1000_power_up_serdes_link_82575()
1328 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, in e1000_get_pcs_speed_and_duplex_82575() argument
1331 struct e1000_mac_info *mac = &hw->mac; in e1000_get_pcs_speed_and_duplex_82575()
1342 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); in e1000_get_pcs_speed_and_duplex_82575()
1366 status = E1000_READ_REG(hw, E1000_STATUS); in e1000_get_pcs_speed_and_duplex_82575()
1392 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) in e1000_shutdown_serdes_link_82575() argument
1398 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in e1000_shutdown_serdes_link_82575()
1399 !e1000_sgmii_active_82575(hw)) in e1000_shutdown_serdes_link_82575()
1402 if (!e1000_enable_mng_pass_thru(hw)) { in e1000_shutdown_serdes_link_82575()
1404 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); in e1000_shutdown_serdes_link_82575()
1406 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); in e1000_shutdown_serdes_link_82575()
1409 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_shutdown_serdes_link_82575()
1411 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); in e1000_shutdown_serdes_link_82575()
1414 E1000_WRITE_FLUSH(hw); in e1000_shutdown_serdes_link_82575()
1427 static s32 e1000_reset_hw_82575(struct e1000_hw *hw) in e1000_reset_hw_82575() argument
1438 ret_val = e1000_disable_pcie_master_generic(hw); in e1000_reset_hw_82575()
1443 ret_val = e1000_set_pcie_completion_timeout(hw); in e1000_reset_hw_82575()
1448 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_82575()
1450 E1000_WRITE_REG(hw, E1000_RCTL, 0); in e1000_reset_hw_82575()
1451 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); in e1000_reset_hw_82575()
1452 E1000_WRITE_FLUSH(hw); in e1000_reset_hw_82575()
1456 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_reset_hw_82575()
1459 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); in e1000_reset_hw_82575()
1461 ret_val = e1000_get_auto_rd_done_generic(hw); in e1000_reset_hw_82575()
1472 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) in e1000_reset_hw_82575()
1473 e1000_reset_init_script_82575(hw); in e1000_reset_hw_82575()
1476 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_82575()
1477 E1000_READ_REG(hw, E1000_ICR); in e1000_reset_hw_82575()
1480 ret_val = e1000_check_alt_mac_addr_generic(hw); in e1000_reset_hw_82575()
1491 s32 e1000_init_hw_82575(struct e1000_hw *hw) in e1000_init_hw_82575() argument
1493 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_82575()
1500 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_82575()
1508 mac->ops.clear_vfta(hw); in e1000_init_hw_82575()
1511 e1000_init_rx_addrs_generic(hw, rar_count); in e1000_init_hw_82575()
1516 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); in e1000_init_hw_82575()
1521 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); in e1000_init_hw_82575()
1524 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_82575()
1527 hw->dev_spec._82575.mtu = 1500; in e1000_init_hw_82575()
1535 e1000_clear_hw_cntrs_82575(hw); in e1000_init_hw_82575()
1548 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) in e1000_setup_copper_link_82575() argument
1556 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_setup_copper_link_82575()
1559 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); in e1000_setup_copper_link_82575()
1562 switch (hw->mac.type) { in e1000_setup_copper_link_82575()
1567 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); in e1000_setup_copper_link_82575()
1569 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); in e1000_setup_copper_link_82575()
1575 ret_val = e1000_setup_serdes_link_82575(hw); in e1000_setup_copper_link_82575()
1579 if (e1000_sgmii_active_82575(hw)) { in e1000_setup_copper_link_82575()
1583 ret_val = hw->phy.ops.reset(hw); in e1000_setup_copper_link_82575()
1589 switch (hw->phy.type) { in e1000_setup_copper_link_82575()
1592 switch (hw->phy.id) { in e1000_setup_copper_link_82575()
1599 ret_val = e1000_copper_link_setup_m88_gen2(hw); in e1000_setup_copper_link_82575()
1602 ret_val = e1000_copper_link_setup_m88(hw); in e1000_setup_copper_link_82575()
1607 ret_val = e1000_copper_link_setup_igp(hw); in e1000_setup_copper_link_82575()
1610 ret_val = e1000_copper_link_setup_82577(hw); in e1000_setup_copper_link_82575()
1620 ret_val = e1000_setup_copper_link_generic(hw); in e1000_setup_copper_link_82575()
1634 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) in e1000_setup_serdes_link_82575() argument
1643 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in e1000_setup_serdes_link_82575()
1644 !e1000_sgmii_active_82575(hw)) in e1000_setup_serdes_link_82575()
1653 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); in e1000_setup_serdes_link_82575()
1656 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_setup_serdes_link_82575()
1658 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_setup_serdes_link_82575()
1660 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_setup_serdes_link_82575()
1664 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) in e1000_setup_serdes_link_82575()
1667 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); in e1000_setup_serdes_link_82575()
1670 pcs_autoneg = hw->mac.autoneg; in e1000_setup_serdes_link_82575()
1684 if (hw->mac.type == e1000_82575 || in e1000_setup_serdes_link_82575()
1685 hw->mac.type == e1000_82576) { in e1000_setup_serdes_link_82575()
1686 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); in e1000_setup_serdes_link_82575()
1709 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); in e1000_setup_serdes_link_82575()
1729 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); in e1000_setup_serdes_link_82575()
1732 switch (hw->fc.requested_mode) { in e1000_setup_serdes_link_82575()
1745 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); in e1000_setup_serdes_link_82575()
1758 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); in e1000_setup_serdes_link_82575()
1760 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) in e1000_setup_serdes_link_82575()
1761 e1000_force_mac_fc_generic(hw); in e1000_setup_serdes_link_82575()
1777 static s32 e1000_get_media_type_82575(struct e1000_hw *hw) in e1000_get_media_type_82575() argument
1779 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_get_media_type_82575()
1789 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_get_media_type_82575()
1796 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_get_media_type_82575()
1799 hw->phy.media_type = e1000_media_type_copper; in e1000_get_media_type_82575()
1803 if (e1000_sgmii_uses_mdio_82575(hw)) { in e1000_get_media_type_82575()
1804 hw->phy.media_type = e1000_media_type_copper; in e1000_get_media_type_82575()
1812 ret_val = e1000_set_sfp_media_type_82575(hw); in e1000_get_media_type_82575()
1814 (hw->phy.media_type == e1000_media_type_unknown)) { in e1000_get_media_type_82575()
1819 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_get_media_type_82575()
1822 hw->phy.media_type = e1000_media_type_copper; in e1000_get_media_type_82575()
1836 if (hw->phy.media_type == e1000_media_type_copper) in e1000_get_media_type_82575()
1841 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_get_media_type_82575()
1856 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) in e1000_set_sfp_media_type_82575() argument
1860 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_set_sfp_media_type_82575()
1866 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_set_sfp_media_type_82575()
1868 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); in e1000_set_sfp_media_type_82575()
1870 E1000_WRITE_FLUSH(hw); in e1000_set_sfp_media_type_82575()
1874 ret_val = e1000_read_sfp_data_byte(hw, in e1000_set_sfp_media_type_82575()
1885 ret_val = e1000_read_sfp_data_byte(hw, in e1000_set_sfp_media_type_82575()
1896 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_set_sfp_media_type_82575()
1899 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_set_sfp_media_type_82575()
1902 hw->phy.media_type = e1000_media_type_copper; in e1000_set_sfp_media_type_82575()
1904 hw->phy.media_type = e1000_media_type_unknown; in e1000_set_sfp_media_type_82575()
1909 hw->phy.media_type = e1000_media_type_unknown; in e1000_set_sfp_media_type_82575()
1914 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_set_sfp_media_type_82575()
1926 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) in e1000_valid_led_default_82575() argument
1932 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_82575()
1939 switch (hw->phy.media_type) { in e1000_valid_led_default_82575()
1961 static bool e1000_sgmii_active_82575(struct e1000_hw *hw) in e1000_sgmii_active_82575() argument
1963 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in e1000_sgmii_active_82575()
1974 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw) in e1000_reset_init_script_82575() argument
1978 if (hw->mac.type == e1000_82575) { in e1000_reset_init_script_82575()
1981 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); in e1000_reset_init_script_82575()
1982 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); in e1000_reset_init_script_82575()
1983 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); in e1000_reset_init_script_82575()
1984 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); in e1000_reset_init_script_82575()
1987 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); in e1000_reset_init_script_82575()
1988 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); in e1000_reset_init_script_82575()
1991 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); in e1000_reset_init_script_82575()
1992 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); in e1000_reset_init_script_82575()
1993 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); in e1000_reset_init_script_82575()
1994 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); in e1000_reset_init_script_82575()
1997 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); in e1000_reset_init_script_82575()
1998 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); in e1000_reset_init_script_82575()
1999 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); in e1000_reset_init_script_82575()
2009 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) in e1000_read_mac_addr_82575() argument
2020 ret_val = e1000_check_alt_mac_addr_generic(hw); in e1000_read_mac_addr_82575()
2024 ret_val = e1000_read_mac_addr_generic(hw); in e1000_read_mac_addr_82575()
2037 static void e1000_config_collision_dist_82575(struct e1000_hw *hw) in e1000_config_collision_dist_82575() argument
2043 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); in e1000_config_collision_dist_82575()
2048 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); in e1000_config_collision_dist_82575()
2049 E1000_WRITE_FLUSH(hw); in e1000_config_collision_dist_82575()
2059 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) in e1000_power_down_phy_copper_82575() argument
2061 struct e1000_phy_info *phy = &hw->phy; in e1000_power_down_phy_copper_82575()
2067 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) in e1000_power_down_phy_copper_82575()
2068 e1000_power_down_phy_copper(hw); in e1000_power_down_phy_copper_82575()
2079 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) in e1000_clear_hw_cntrs_82575() argument
2083 e1000_clear_hw_cntrs_base_generic(hw); in e1000_clear_hw_cntrs_82575()
2085 E1000_READ_REG(hw, E1000_PRC64); in e1000_clear_hw_cntrs_82575()
2086 E1000_READ_REG(hw, E1000_PRC127); in e1000_clear_hw_cntrs_82575()
2087 E1000_READ_REG(hw, E1000_PRC255); in e1000_clear_hw_cntrs_82575()
2088 E1000_READ_REG(hw, E1000_PRC511); in e1000_clear_hw_cntrs_82575()
2089 E1000_READ_REG(hw, E1000_PRC1023); in e1000_clear_hw_cntrs_82575()
2090 E1000_READ_REG(hw, E1000_PRC1522); in e1000_clear_hw_cntrs_82575()
2091 E1000_READ_REG(hw, E1000_PTC64); in e1000_clear_hw_cntrs_82575()
2092 E1000_READ_REG(hw, E1000_PTC127); in e1000_clear_hw_cntrs_82575()
2093 E1000_READ_REG(hw, E1000_PTC255); in e1000_clear_hw_cntrs_82575()
2094 E1000_READ_REG(hw, E1000_PTC511); in e1000_clear_hw_cntrs_82575()
2095 E1000_READ_REG(hw, E1000_PTC1023); in e1000_clear_hw_cntrs_82575()
2096 E1000_READ_REG(hw, E1000_PTC1522); in e1000_clear_hw_cntrs_82575()
2098 E1000_READ_REG(hw, E1000_ALGNERRC); in e1000_clear_hw_cntrs_82575()
2099 E1000_READ_REG(hw, E1000_RXERRC); in e1000_clear_hw_cntrs_82575()
2100 E1000_READ_REG(hw, E1000_TNCRS); in e1000_clear_hw_cntrs_82575()
2101 E1000_READ_REG(hw, E1000_CEXTERR); in e1000_clear_hw_cntrs_82575()
2102 E1000_READ_REG(hw, E1000_TSCTC); in e1000_clear_hw_cntrs_82575()
2103 E1000_READ_REG(hw, E1000_TSCTFC); in e1000_clear_hw_cntrs_82575()
2105 E1000_READ_REG(hw, E1000_MGTPRC); in e1000_clear_hw_cntrs_82575()
2106 E1000_READ_REG(hw, E1000_MGTPDC); in e1000_clear_hw_cntrs_82575()
2107 E1000_READ_REG(hw, E1000_MGTPTC); in e1000_clear_hw_cntrs_82575()
2109 E1000_READ_REG(hw, E1000_IAC); in e1000_clear_hw_cntrs_82575()
2110 E1000_READ_REG(hw, E1000_ICRXOC); in e1000_clear_hw_cntrs_82575()
2112 E1000_READ_REG(hw, E1000_ICRXPTC); in e1000_clear_hw_cntrs_82575()
2113 E1000_READ_REG(hw, E1000_ICRXATC); in e1000_clear_hw_cntrs_82575()
2114 E1000_READ_REG(hw, E1000_ICTXPTC); in e1000_clear_hw_cntrs_82575()
2115 E1000_READ_REG(hw, E1000_ICTXATC); in e1000_clear_hw_cntrs_82575()
2116 E1000_READ_REG(hw, E1000_ICTXQEC); in e1000_clear_hw_cntrs_82575()
2117 E1000_READ_REG(hw, E1000_ICTXQMTC); in e1000_clear_hw_cntrs_82575()
2118 E1000_READ_REG(hw, E1000_ICRXDMTC); in e1000_clear_hw_cntrs_82575()
2120 E1000_READ_REG(hw, E1000_CBTMPC); in e1000_clear_hw_cntrs_82575()
2121 E1000_READ_REG(hw, E1000_HTDPMC); in e1000_clear_hw_cntrs_82575()
2122 E1000_READ_REG(hw, E1000_CBRMPC); in e1000_clear_hw_cntrs_82575()
2123 E1000_READ_REG(hw, E1000_RPTHC); in e1000_clear_hw_cntrs_82575()
2124 E1000_READ_REG(hw, E1000_HGPTC); in e1000_clear_hw_cntrs_82575()
2125 E1000_READ_REG(hw, E1000_HTCBDPC); in e1000_clear_hw_cntrs_82575()
2126 E1000_READ_REG(hw, E1000_HGORCL); in e1000_clear_hw_cntrs_82575()
2127 E1000_READ_REG(hw, E1000_HGORCH); in e1000_clear_hw_cntrs_82575()
2128 E1000_READ_REG(hw, E1000_HGOTCL); in e1000_clear_hw_cntrs_82575()
2129 E1000_READ_REG(hw, E1000_HGOTCH); in e1000_clear_hw_cntrs_82575()
2130 E1000_READ_REG(hw, E1000_LENERRS); in e1000_clear_hw_cntrs_82575()
2133 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || in e1000_clear_hw_cntrs_82575()
2134 e1000_sgmii_active_82575(hw)) in e1000_clear_hw_cntrs_82575()
2135 E1000_READ_REG(hw, E1000_SCVPC); in e1000_clear_hw_cntrs_82575()
2147 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) in e1000_rx_fifo_flush_82575() argument
2155 rfctl = E1000_READ_REG(hw, E1000_RFCTL); in e1000_rx_fifo_flush_82575()
2157 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); in e1000_rx_fifo_flush_82575()
2159 if (hw->mac.type != e1000_82575 || in e1000_rx_fifo_flush_82575()
2160 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) in e1000_rx_fifo_flush_82575()
2165 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); in e1000_rx_fifo_flush_82575()
2166 E1000_WRITE_REG(hw, E1000_RXDCTL(i), in e1000_rx_fifo_flush_82575()
2174 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); in e1000_rx_fifo_flush_82575()
2186 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); in e1000_rx_fifo_flush_82575()
2188 rlpml = E1000_READ_REG(hw, E1000_RLPML); in e1000_rx_fifo_flush_82575()
2189 E1000_WRITE_REG(hw, E1000_RLPML, 0); in e1000_rx_fifo_flush_82575()
2191 rctl = E1000_READ_REG(hw, E1000_RCTL); in e1000_rx_fifo_flush_82575()
2195 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); in e1000_rx_fifo_flush_82575()
2196 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); in e1000_rx_fifo_flush_82575()
2197 E1000_WRITE_FLUSH(hw); in e1000_rx_fifo_flush_82575()
2204 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); in e1000_rx_fifo_flush_82575()
2205 E1000_WRITE_REG(hw, E1000_RCTL, rctl); in e1000_rx_fifo_flush_82575()
2206 E1000_WRITE_FLUSH(hw); in e1000_rx_fifo_flush_82575()
2208 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); in e1000_rx_fifo_flush_82575()
2209 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); in e1000_rx_fifo_flush_82575()
2212 E1000_READ_REG(hw, E1000_ROC); in e1000_rx_fifo_flush_82575()
2213 E1000_READ_REG(hw, E1000_RNBC); in e1000_rx_fifo_flush_82575()
2214 E1000_READ_REG(hw, E1000_MPC); in e1000_rx_fifo_flush_82575()
2227 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) in e1000_set_pcie_completion_timeout() argument
2229 u32 gcr = E1000_READ_REG(hw, E1000_GCR); in e1000_set_pcie_completion_timeout()
2251 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, in e1000_set_pcie_completion_timeout()
2258 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, in e1000_set_pcie_completion_timeout()
2264 E1000_WRITE_REG(hw, E1000_GCR, gcr); in e1000_set_pcie_completion_timeout()
2276 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) in e1000_vmdq_set_anti_spoofing_pf() argument
2280 switch (hw->mac.type) { in e1000_vmdq_set_anti_spoofing_pf()
2292 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2304 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()
2314 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) in e1000_vmdq_set_loopback_pf() argument
2318 switch (hw->mac.type) { in e1000_vmdq_set_loopback_pf()
2320 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); in e1000_vmdq_set_loopback_pf()
2325 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); in e1000_vmdq_set_loopback_pf()
2329 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); in e1000_vmdq_set_loopback_pf()
2334 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); in e1000_vmdq_set_loopback_pf()
2351 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) in e1000_vmdq_set_replication_pf() argument
2353 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); in e1000_vmdq_set_replication_pf()
2360 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); in e1000_vmdq_set_replication_pf()
2372 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) in e1000_read_phy_reg_82580() argument
2378 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_82580()
2382 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); in e1000_read_phy_reg_82580()
2384 hw->phy.ops.release(hw); in e1000_read_phy_reg_82580()
2398 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) in e1000_write_phy_reg_82580() argument
2404 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_82580()
2408 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); in e1000_write_phy_reg_82580()
2410 hw->phy.ops.release(hw); in e1000_write_phy_reg_82580()
2424 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) in e1000_reset_mdicnfg_82580() argument
2432 if (hw->mac.type != e1000_82580) in e1000_reset_mdicnfg_82580()
2434 if (!e1000_sgmii_active_82575(hw)) in e1000_reset_mdicnfg_82580()
2437 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + in e1000_reset_mdicnfg_82580()
2438 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, in e1000_reset_mdicnfg_82580()
2445 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); in e1000_reset_mdicnfg_82580()
2450 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); in e1000_reset_mdicnfg_82580()
2462 static s32 e1000_reset_hw_82580(struct e1000_hw *hw) in e1000_reset_hw_82580() argument
2468 bool global_device_reset = hw->dev_spec._82575.global_device_reset; in e1000_reset_hw_82580()
2472 hw->dev_spec._82575.global_device_reset = FALSE; in e1000_reset_hw_82580()
2475 if (hw->mac.type == e1000_82580) in e1000_reset_hw_82580()
2479 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_reset_hw_82580()
2485 ret_val = e1000_disable_pcie_master_generic(hw); in e1000_reset_hw_82580()
2490 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_82580()
2491 E1000_WRITE_REG(hw, E1000_RCTL, 0); in e1000_reset_hw_82580()
2492 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); in e1000_reset_hw_82580()
2493 E1000_WRITE_FLUSH(hw); in e1000_reset_hw_82580()
2498 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, in e1000_reset_hw_82580()
2502 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & in e1000_reset_hw_82580()
2508 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); in e1000_reset_hw_82580()
2510 switch (hw->device_id) { in e1000_reset_hw_82580()
2514 E1000_WRITE_FLUSH(hw); in e1000_reset_hw_82580()
2521 ret_val = e1000_get_auto_rd_done_generic(hw); in e1000_reset_hw_82580()
2532 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); in e1000_reset_hw_82580()
2535 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_82580()
2536 E1000_READ_REG(hw, E1000_ICR); in e1000_reset_hw_82580()
2538 ret_val = e1000_reset_mdicnfg_82580(hw); in e1000_reset_hw_82580()
2543 ret_val = e1000_check_alt_mac_addr_generic(hw); in e1000_reset_hw_82580()
2547 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); in e1000_reset_hw_82580()
2581 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) in e1000_validate_nvm_checksum_with_offset() argument
2590 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in e1000_validate_nvm_checksum_with_offset()
2618 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) in e1000_update_nvm_checksum_with_offset() argument
2627 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in e1000_update_nvm_checksum_with_offset()
2635 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, in e1000_update_nvm_checksum_with_offset()
2652 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) in e1000_validate_nvm_checksum_82580() argument
2661 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in e1000_validate_nvm_checksum_82580()
2675 ret_val = e1000_validate_nvm_checksum_with_offset(hw, in e1000_validate_nvm_checksum_82580()
2693 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) in e1000_update_nvm_checksum_82580() argument
2701 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in e1000_update_nvm_checksum_82580()
2710 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, in e1000_update_nvm_checksum_82580()
2720 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); in e1000_update_nvm_checksum_82580()
2737 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) in e1000_validate_nvm_checksum_i350() argument
2747 ret_val = e1000_validate_nvm_checksum_with_offset(hw, in e1000_validate_nvm_checksum_i350()
2765 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) in e1000_update_nvm_checksum_i350() argument
2775 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); in e1000_update_nvm_checksum_i350()
2791 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address, in __e1000_access_emi_reg() argument
2798 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); in __e1000_access_emi_reg()
2803 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); in __e1000_access_emi_reg()
2805 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); in __e1000_access_emi_reg()
2816 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) in e1000_read_emi_reg() argument
2820 return __e1000_access_emi_reg(hw, addr, data, TRUE); in e1000_read_emi_reg()
2829 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw) in e1000_initialize_M88E1512_phy() argument
2831 struct e1000_phy_info *phy = &hw->phy; in e1000_initialize_M88E1512_phy()
2841 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); in e1000_initialize_M88E1512_phy()
2845 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); in e1000_initialize_M88E1512_phy()
2849 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); in e1000_initialize_M88E1512_phy()
2853 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); in e1000_initialize_M88E1512_phy()
2857 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); in e1000_initialize_M88E1512_phy()
2861 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); in e1000_initialize_M88E1512_phy()
2865 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); in e1000_initialize_M88E1512_phy()
2869 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); in e1000_initialize_M88E1512_phy()
2873 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); in e1000_initialize_M88E1512_phy()
2878 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); in e1000_initialize_M88E1512_phy()
2882 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); in e1000_initialize_M88E1512_phy()
2887 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); in e1000_initialize_M88E1512_phy()
2892 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); in e1000_initialize_M88E1512_phy()
2897 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in e1000_initialize_M88E1512_phy()
2901 ret_val = phy->ops.commit(hw); in e1000_initialize_M88E1512_phy()
2918 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw) in e1000_initialize_M88E1543_phy() argument
2920 struct e1000_phy_info *phy = &hw->phy; in e1000_initialize_M88E1543_phy()
2930 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); in e1000_initialize_M88E1543_phy()
2934 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); in e1000_initialize_M88E1543_phy()
2938 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); in e1000_initialize_M88E1543_phy()
2942 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); in e1000_initialize_M88E1543_phy()
2946 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); in e1000_initialize_M88E1543_phy()
2950 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); in e1000_initialize_M88E1543_phy()
2954 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); in e1000_initialize_M88E1543_phy()
2958 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C); in e1000_initialize_M88E1543_phy()
2962 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); in e1000_initialize_M88E1543_phy()
2967 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); in e1000_initialize_M88E1543_phy()
2971 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D); in e1000_initialize_M88E1543_phy()
2976 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); in e1000_initialize_M88E1543_phy()
2981 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); in e1000_initialize_M88E1543_phy()
2986 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1); in e1000_initialize_M88E1543_phy()
2991 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140); in e1000_initialize_M88E1543_phy()
2996 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in e1000_initialize_M88E1543_phy()
3000 ret_val = phy->ops.commit(hw); in e1000_initialize_M88E1543_phy()
3020 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) in e1000_set_eee_i350() argument
3026 if ((hw->mac.type < e1000_i350) || in e1000_set_eee_i350()
3027 (hw->phy.media_type != e1000_media_type_copper)) in e1000_set_eee_i350()
3029 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); in e1000_set_eee_i350()
3030 eeer = E1000_READ_REG(hw, E1000_EEER); in e1000_set_eee_i350()
3033 if (!(hw->dev_spec._82575.eee_disable)) { in e1000_set_eee_i350()
3034 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); in e1000_set_eee_i350()
3057 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); in e1000_set_eee_i350()
3058 E1000_WRITE_REG(hw, E1000_EEER, eeer); in e1000_set_eee_i350()
3059 E1000_READ_REG(hw, E1000_IPCNFG); in e1000_set_eee_i350()
3060 E1000_READ_REG(hw, E1000_EEER); in e1000_set_eee_i350()
3075 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) in e1000_set_eee_i354() argument
3077 struct e1000_phy_info *phy = &hw->phy; in e1000_set_eee_i354()
3083 if ((hw->phy.media_type != e1000_media_type_copper) || in e1000_set_eee_i354()
3088 if (!hw->dev_spec._82575.eee_disable) { in e1000_set_eee_i354()
3090 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); in e1000_set_eee_i354()
3094 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, in e1000_set_eee_i354()
3100 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, in e1000_set_eee_i354()
3106 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in e1000_set_eee_i354()
3111 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in e1000_set_eee_i354()
3127 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in e1000_set_eee_i354()
3132 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in e1000_set_eee_i354()
3140 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in e1000_set_eee_i354()
3157 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status) in e1000_get_eee_status_i354() argument
3159 struct e1000_phy_info *phy = &hw->phy; in e1000_get_eee_status_i354()
3166 if ((hw->phy.media_type != e1000_media_type_copper) || in e1000_get_eee_status_i354()
3171 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, in e1000_get_eee_status_i354()
3196 void e1000_clear_vfta_i350(struct e1000_hw *hw) in e1000_clear_vfta_i350() argument
3205 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); in e1000_clear_vfta_i350()
3207 E1000_WRITE_FLUSH(hw); in e1000_clear_vfta_i350()
3220 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) in e1000_write_vfta_i350() argument
3227 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); in e1000_write_vfta_i350()
3229 E1000_WRITE_FLUSH(hw); in e1000_write_vfta_i350()
3240 s32 e1000_set_i2c_bb(struct e1000_hw *hw) in e1000_set_i2c_bb() argument
3247 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_set_i2c_bb()
3249 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_set_i2c_bb()
3250 E1000_WRITE_FLUSH(hw); in e1000_set_i2c_bb()
3252 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_set_i2c_bb()
3256 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); in e1000_set_i2c_bb()
3257 E1000_WRITE_FLUSH(hw); in e1000_set_i2c_bb()
3272 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, in e1000_read_i2c_byte_generic() argument
3287 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) in e1000_read_i2c_byte_generic()
3293 e1000_i2c_start(hw); in e1000_read_i2c_byte_generic()
3296 status = e1000_clock_out_i2c_byte(hw, dev_addr); in e1000_read_i2c_byte_generic()
3300 status = e1000_get_i2c_ack(hw); in e1000_read_i2c_byte_generic()
3304 status = e1000_clock_out_i2c_byte(hw, byte_offset); in e1000_read_i2c_byte_generic()
3308 status = e1000_get_i2c_ack(hw); in e1000_read_i2c_byte_generic()
3312 e1000_i2c_start(hw); in e1000_read_i2c_byte_generic()
3315 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); in e1000_read_i2c_byte_generic()
3319 status = e1000_get_i2c_ack(hw); in e1000_read_i2c_byte_generic()
3323 status = e1000_clock_in_i2c_byte(hw, data); in e1000_read_i2c_byte_generic()
3327 status = e1000_clock_out_i2c_bit(hw, nack); in e1000_read_i2c_byte_generic()
3331 e1000_i2c_stop(hw); in e1000_read_i2c_byte_generic()
3335 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in e1000_read_i2c_byte_generic()
3337 e1000_i2c_bus_clear(hw); in e1000_read_i2c_byte_generic()
3346 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in e1000_read_i2c_byte_generic()
3363 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, in e1000_write_i2c_byte_generic() argument
3375 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { in e1000_write_i2c_byte_generic()
3381 e1000_i2c_start(hw); in e1000_write_i2c_byte_generic()
3383 status = e1000_clock_out_i2c_byte(hw, dev_addr); in e1000_write_i2c_byte_generic()
3387 status = e1000_get_i2c_ack(hw); in e1000_write_i2c_byte_generic()
3391 status = e1000_clock_out_i2c_byte(hw, byte_offset); in e1000_write_i2c_byte_generic()
3395 status = e1000_get_i2c_ack(hw); in e1000_write_i2c_byte_generic()
3399 status = e1000_clock_out_i2c_byte(hw, data); in e1000_write_i2c_byte_generic()
3403 status = e1000_get_i2c_ack(hw); in e1000_write_i2c_byte_generic()
3407 e1000_i2c_stop(hw); in e1000_write_i2c_byte_generic()
3411 e1000_i2c_bus_clear(hw); in e1000_write_i2c_byte_generic()
3419 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in e1000_write_i2c_byte_generic()
3432 static void e1000_i2c_start(struct e1000_hw *hw) in e1000_i2c_start() argument
3434 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_i2c_start()
3439 e1000_set_i2c_data(hw, &i2cctl, 1); in e1000_i2c_start()
3440 e1000_raise_i2c_clk(hw, &i2cctl); in e1000_i2c_start()
3445 e1000_set_i2c_data(hw, &i2cctl, 0); in e1000_i2c_start()
3450 e1000_lower_i2c_clk(hw, &i2cctl); in e1000_i2c_start()
3463 static void e1000_i2c_stop(struct e1000_hw *hw) in e1000_i2c_stop() argument
3465 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_i2c_stop()
3470 e1000_set_i2c_data(hw, &i2cctl, 0); in e1000_i2c_stop()
3471 e1000_raise_i2c_clk(hw, &i2cctl); in e1000_i2c_stop()
3476 e1000_set_i2c_data(hw, &i2cctl, 1); in e1000_i2c_stop()
3489 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) in e1000_clock_in_i2c_byte() argument
3498 e1000_clock_in_i2c_bit(hw, &bit); in e1000_clock_in_i2c_byte()
3512 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) in e1000_clock_out_i2c_byte() argument
3523 status = e1000_clock_out_i2c_bit(hw, bit); in e1000_clock_out_i2c_byte()
3530 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_clock_out_i2c_byte()
3533 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); in e1000_clock_out_i2c_byte()
3534 E1000_WRITE_FLUSH(hw); in e1000_clock_out_i2c_byte()
3545 static s32 e1000_get_i2c_ack(struct e1000_hw *hw) in e1000_get_i2c_ack() argument
3549 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_get_i2c_ack()
3555 e1000_raise_i2c_clk(hw, &i2cctl); in e1000_get_i2c_ack()
3563 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_get_i2c_ack()
3576 e1000_lower_i2c_clk(hw, &i2cctl); in e1000_get_i2c_ack()
3591 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) in e1000_clock_in_i2c_bit() argument
3593 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_clock_in_i2c_bit()
3597 e1000_raise_i2c_clk(hw, &i2cctl); in e1000_clock_in_i2c_bit()
3602 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_clock_in_i2c_bit()
3605 e1000_lower_i2c_clk(hw, &i2cctl); in e1000_clock_in_i2c_bit()
3620 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) in e1000_clock_out_i2c_bit() argument
3623 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_clock_out_i2c_bit()
3627 status = e1000_set_i2c_data(hw, &i2cctl, data); in e1000_clock_out_i2c_bit()
3629 e1000_raise_i2c_clk(hw, &i2cctl); in e1000_clock_out_i2c_bit()
3634 e1000_lower_i2c_clk(hw, &i2cctl); in e1000_clock_out_i2c_bit()
3654 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) in e1000_raise_i2c_clk() argument
3660 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); in e1000_raise_i2c_clk()
3661 E1000_WRITE_FLUSH(hw); in e1000_raise_i2c_clk()
3674 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) in e1000_lower_i2c_clk() argument
3681 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); in e1000_lower_i2c_clk()
3682 E1000_WRITE_FLUSH(hw); in e1000_lower_i2c_clk()
3696 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) in e1000_set_i2c_data() argument
3709 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); in e1000_set_i2c_data()
3710 E1000_WRITE_FLUSH(hw); in e1000_set_i2c_data()
3715 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_set_i2c_data()
3752 void e1000_i2c_bus_clear(struct e1000_hw *hw) in e1000_i2c_bus_clear() argument
3754 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); in e1000_i2c_bus_clear()
3759 e1000_i2c_start(hw); in e1000_i2c_bus_clear()
3761 e1000_set_i2c_data(hw, &i2cctl, 1); in e1000_i2c_bus_clear()
3764 e1000_raise_i2c_clk(hw, &i2cctl); in e1000_i2c_bus_clear()
3769 e1000_lower_i2c_clk(hw, &i2cctl); in e1000_i2c_bus_clear()
3775 e1000_i2c_start(hw); in e1000_i2c_bus_clear()
3778 e1000_i2c_stop(hw); in e1000_i2c_bus_clear()