34 	adapter_t *adapter;  member
50 static void tp_pm_configure(adapter_t *adapter, struct tp_params *p)  in tp_pm_configure()  argument
62 	t1_write_reg_4(adapter, A_TP_PM_SIZE, p->pm_size);  in tp_pm_configure()
63 	t1_write_reg_4(adapter, A_TP_PM_RX_BASE, p->pm_rx_base);  in tp_pm_configure()
64 	t1_write_reg_4(adapter, A_TP_PM_TX_BASE, p->pm_tx_base);  in tp_pm_configure()
65 	t1_write_reg_4(adapter, A_TP_PM_DEFRAG_BASE, p->pm_size);  in tp_pm_configure()
66 	t1_write_reg_4(adapter, A_TP_PM_RX_PG_SIZE, p->pm_rx_pg_size);  in tp_pm_configure()
67 	t1_write_reg_4(adapter, A_TP_PM_RX_MAX_PGS, p->pm_rx_num_pgs);  in tp_pm_configure()
68 	t1_write_reg_4(adapter, A_TP_PM_TX_PG_SIZE, p->pm_tx_pg_size);  in tp_pm_configure()
69 	t1_write_reg_4(adapter, A_TP_PM_TX_MAX_PGS, p->pm_tx_num_pgs);  in tp_pm_configure()
72 static void tp_cm_configure(adapter_t *adapter, u32 cm_size)  in tp_cm_configure()  argument
77 	t1_write_reg_4(adapter, A_TP_CM_SIZE, cm_size);  in tp_cm_configure()
78 	t1_write_reg_4(adapter, A_TP_CM_MM_BASE, mm_base);  in tp_cm_configure()
79 	t1_write_reg_4(adapter, A_TP_CM_TIMER_BASE, (cm_size >> 2) * 3);  in tp_cm_configure()
80 	t1_write_reg_4(adapter, A_TP_CM_MM_P_FLST_BASE,  in tp_cm_configure()
82 	t1_write_reg_4(adapter, A_TP_CM_MM_TX_FLST_BASE,  in tp_cm_configure()
84 	t1_write_reg_4(adapter, A_TP_CM_MM_RX_FLST_BASE,  in tp_cm_configure()
86 	t1_write_reg_4(adapter, A_TP_CM_MM_MAX_P, 0x40000);  in tp_cm_configure()
103 static void tp_set_tcp_time_params(adapter_t *adapter, unsigned int tp_clk)  in tp_set_tcp_time_params()  argument
105 	u32 tps = t1_tp_ticks_per_sec(adapter, tp_clk);  in tp_set_tcp_time_params()
109 	t1_write_reg_4(adapter, A_TP_2MSL, (1 SECONDS)/2);  in tp_set_tcp_time_params()
110 	t1_write_reg_4(adapter, A_TP_RXT_MIN, (1 SECONDS)/4);  in tp_set_tcp_time_params()
111 	t1_write_reg_4(adapter, A_TP_RXT_MAX, 64 SECONDS);  in tp_set_tcp_time_params()
112 	t1_write_reg_4(adapter, A_TP_PERS_MIN, (1 SECONDS)/2);  in tp_set_tcp_time_params()
113 	t1_write_reg_4(adapter, A_TP_PERS_MAX, 64 SECONDS);  in tp_set_tcp_time_params()
114 	t1_write_reg_4(adapter, A_TP_KEEP_IDLE, 7200 SECONDS);  in tp_set_tcp_time_params()
115 	t1_write_reg_4(adapter, A_TP_KEEP_INTVL, 75 SECONDS);  in tp_set_tcp_time_params()
116 	t1_write_reg_4(adapter, A_TP_INIT_SRTT, 3 SECONDS);  in tp_set_tcp_time_params()
117 	t1_write_reg_4(adapter, A_TP_FINWAIT2_TIME, 60 SECONDS);  in tp_set_tcp_time_params()
118 	t1_write_reg_4(adapter, A_TP_FAST_FINWAIT2_TIME, 3 SECONDS);  in tp_set_tcp_time_params()
122 	tp_scnt = t1_read_reg_4(adapter, A_TP_SHIFT_CNT);  in tp_set_tcp_time_params()
125 	t1_write_reg_4(adapter, A_TP_SHIFT_CNT, tp_scnt);  in tp_set_tcp_time_params()
128 	t1_write_reg_4(adapter, A_TP_DACK_TIME,  in tp_set_tcp_time_params()
129 		       tp_delayed_ack_ticks(adapter, tp_clk) / 5);  in tp_set_tcp_time_params()
139 	val = t1_read_reg_4(tp->adapter, A_TP_PARA_REG3);  in t1_tp_set_coalescing_size()
141 	if (tp->adapter->params.nports > 1)  in t1_tp_set_coalescing_size()
145 		u32 v = t1_is_T1B(tp->adapter) ? 0 : V_MAX_RX_SIZE(size);  in t1_tp_set_coalescing_size()
148 		t1_write_reg_4(tp->adapter, A_TP_PARA_REG2,  in t1_tp_set_coalescing_size()
155 	t1_write_reg_4(tp->adapter, A_TP_PARA_REG3, val);  in t1_tp_set_coalescing_size()
284 struct petp * __devinit t1_tp_create(adapter_t *adapter, struct tp_params *p)  in t1_tp_create()  argument
290 	tp->adapter = adapter;  in t1_tp_create()
302 		if (adapter->params.nports == 1)  in t1_tp_create()
317 	u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE);  in t1_tp_intr_enable()
320 	if (!t1_is_asic(tp->adapter)) {  in t1_tp_intr_enable()
322 		t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE,  in t1_tp_intr_enable()
324 		t1_write_reg_4(tp->adapter, A_PL_ENABLE,  in t1_tp_intr_enable()
330 		t1_write_reg_4(tp->adapter, A_TP_INT_ENABLE, 0);  in t1_tp_intr_enable()
331 		t1_write_reg_4(tp->adapter, A_PL_ENABLE,  in t1_tp_intr_enable()
338 	u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE);  in t1_tp_intr_disable()
341 	if (!t1_is_asic(tp->adapter)) {  in t1_tp_intr_disable()
343 		t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE, 0);  in t1_tp_intr_disable()
344 		t1_write_reg_4(tp->adapter, A_PL_ENABLE,  in t1_tp_intr_disable()
349 		t1_write_reg_4(tp->adapter, A_TP_INT_ENABLE, 0);  in t1_tp_intr_disable()
350 		t1_write_reg_4(tp->adapter, A_PL_ENABLE,  in t1_tp_intr_disable()
358 	if (!t1_is_asic(tp->adapter)) {  in t1_tp_intr_clear()
359 		t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_CAUSE,  in t1_tp_intr_clear()
361 		t1_write_reg_4(tp->adapter, A_PL_CAUSE, FPGA_PCIX_INTERRUPT_TP);  in t1_tp_intr_clear()
365 	t1_write_reg_4(tp->adapter, A_TP_INT_CAUSE, 0xffffffff);  in t1_tp_intr_clear()
366 	t1_write_reg_4(tp->adapter, A_PL_CAUSE, F_PL_INTR_TP);  in t1_tp_intr_clear()
375 	if (!t1_is_asic(tp->adapter))  in t1_tp_intr_handler()
379 	cause = t1_read_reg_4(tp->adapter, A_TP_INT_CAUSE);  in t1_tp_intr_handler()
380 	t1_write_reg_4(tp->adapter, A_TP_INT_CAUSE, cause);  in t1_tp_intr_handler()
386 	u32 val = t1_read_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG);  in set_csum_offload()
392 	t1_write_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG, val);  in set_csum_offload()
417 	adapter_t *adapter = tp->adapter;  in t1_tp_reset()  local
419 	tp_init(adapter, p, tp_clk);  in t1_tp_reset()
422 		tp_pm_configure(adapter, p);  in t1_tp_reset()
423 		tp_cm_configure(adapter, p->cm_size);  in t1_tp_reset()
425 		t1_write_reg_4(adapter, A_TP_RESET, F_CM_MEMMGR_INIT);  in t1_tp_reset()
426 		busy = t1_wait_op_done(adapter, A_TP_RESET, F_CM_MEMMGR_INIT,  in t1_tp_reset()
431 		t1_write_reg_4(adapter, A_TP_RESET, F_TP_RESET);  in t1_tp_reset()
434 		       adapter_name(adapter));  in t1_tp_reset()