Lines Matching refs:pmwrite
99 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32) in pmwrite() function
129 (void) pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
130 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
131 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
132 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
135 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_enable()
136 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_enable()
137 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_enable()
138 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_enable()
140 (void) pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff); in pm3393_interrupt_enable()
141 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
142 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
143 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
144 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
145 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff); in pm3393_interrupt_enable()
146 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
147 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
148 (void) pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff); in pm3393_interrupt_enable()
153 (void) pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, in pm3393_interrupt_enable()
176 (void) pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
177 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
178 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
179 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
180 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_disable()
181 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_disable()
182 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_disable()
183 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_disable()
184 (void) pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0); in pm3393_interrupt_disable()
185 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
186 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
187 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
188 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
189 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0); in pm3393_interrupt_disable()
190 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
191 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
192 (void) pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0); in pm3393_interrupt_disable()
195 (void) pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
358 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, in pm3393_enable()
368 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val); in pm3393_enable()
379 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_enable_port()
401 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL); in pm3393_disable()
403 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL); in pm3393_disable()
440 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu); in pm3393_set_mtu()
441 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu); in pm3393_set_mtu()
486 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode); in pm3393_set_rx_mode()
494 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff); in pm3393_set_rx_mode()
495 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff); in pm3393_set_rx_mode()
496 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff); in pm3393_set_rx_mode()
497 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff); in pm3393_set_rx_mode()
509 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]); in pm3393_set_rx_mode()
510 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]); in pm3393_set_rx_mode()
511 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]); in pm3393_set_rx_mode()
512 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]); in pm3393_set_rx_mode()
516 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode); in pm3393_set_rx_mode()
574 (void) pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_update_statistics()
652 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo); in pm3393_macaddress_set()
653 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid); in pm3393_macaddress_set()
654 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi); in pm3393_macaddress_set()
657 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo); in pm3393_macaddress_set()
658 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid); in pm3393_macaddress_set()
659 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi); in pm3393_macaddress_set()
667 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); in pm3393_macaddress_set()
669 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo); in pm3393_macaddress_set()
670 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid); in pm3393_macaddress_set()
671 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi); in pm3393_macaddress_set()
674 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); in pm3393_macaddress_set()