Lines Matching full:adapter
31 adapter_t *adapter; member
47 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr, in tricn_write() argument
52 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) | in tricn_write()
57 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0); in tricn_write()
59 busy = t1_wait_op_done(adapter, A_ESPI_GOSTAT, F_ESPI_CMD_BUSY, 0, in tricn_write()
63 CH_ERR("%s: TRICN write timed out\n", adapter_name(adapter)); in tricn_write()
69 static int tricn_read(adapter_t *adapter, int bundle_addr, int module_addr,
75 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
80 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
83 status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);
88 CH_ERR("%s: TRICN read timed out\n", adapter_name(adapter));
95 static int tricn_init(adapter_t *adapter) in tricn_init() argument
99 if (!(t1_read_reg_4(adapter, A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
100 CH_ERR("%s: ESPI clock not ready\n", adapter_name(adapter)); in tricn_init()
104 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST); in tricn_init()
107 (void) tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81); in tricn_init()
108 (void) tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81); in tricn_init()
109 (void) tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81); in tricn_init()
111 for (i=1; i<= 8; i++) (void) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1); in tricn_init()
112 for (i=1; i<= 2; i++) (void) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1); in tricn_init()
113 for (i=1; i<= 3; i++) (void) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1); in tricn_init()
114 (void) tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1); in tricn_init()
115 (void) tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1); in tricn_init()
116 (void) tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1); in tricn_init()
117 (void) tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80); in tricn_init()
118 (void) tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1); in tricn_init()
120 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST); in tricn_init()
127 u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_enable()
136 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK; in t1_espi_intr_enable()
137 t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable); in t1_espi_intr_enable()
138 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI); in t1_espi_intr_enable()
143 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
144 t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff); in t1_espi_intr_clear()
145 t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI); in t1_espi_intr_clear()
150 u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_disable()
152 t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, 0); in t1_espi_intr_disable()
153 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI); in t1_espi_intr_disable()
158 u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
172 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
179 if (status && t1_is_T1B(espi->adapter)) in t1_espi_intr_handler()
181 t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, status); in t1_espi_intr_handler()
190 static void espi_setup_for_pm3393(adapter_t *adapter) in espi_setup_for_pm3393() argument
192 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200; in espi_setup_for_pm3393()
194 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4); in espi_setup_for_pm3393()
195 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4); in espi_setup_for_pm3393()
196 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4); in espi_setup_for_pm3393()
197 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4); in espi_setup_for_pm3393()
198 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100); in espi_setup_for_pm3393()
199 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark); in espi_setup_for_pm3393()
200 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3); in espi_setup_for_pm3393()
201 t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008); in espi_setup_for_pm3393()
202 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_pm3393()
206 static void espi_setup_for_vsc7321(adapter_t *adapter) in espi_setup_for_vsc7321() argument
209 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200; in espi_setup_for_vsc7321()
211 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4); in espi_setup_for_vsc7321()
212 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4); in espi_setup_for_vsc7321()
213 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4); in espi_setup_for_vsc7321()
214 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4); in espi_setup_for_vsc7321()
215 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100); in espi_setup_for_vsc7321()
216 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark); in espi_setup_for_vsc7321()
217 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3); in espi_setup_for_vsc7321()
218 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_vsc7321()
221 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4); in espi_setup_for_vsc7321()
222 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f401f4); in espi_setup_for_vsc7321()
223 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4); in espi_setup_for_vsc7321()
224 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, 0xa00); in espi_setup_for_vsc7321()
225 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x1ff); in espi_setup_for_vsc7321()
226 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1); in espi_setup_for_vsc7321()
227 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_vsc7321()
230 t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008); in espi_setup_for_vsc7321()
236 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports) in espi_setup_for_ixf1010() argument
238 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1); in espi_setup_for_ixf1010()
240 if (is_T2(adapter)) { in espi_setup_for_ixf1010()
241 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, in espi_setup_for_ixf1010()
243 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, in espi_setup_for_ixf1010()
246 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, in espi_setup_for_ixf1010()
248 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, in espi_setup_for_ixf1010()
252 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, in espi_setup_for_ixf1010()
254 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, in espi_setup_for_ixf1010()
257 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_ixf1010()
264 adapter_t *adapter = espi->adapter; in t1_espi_init() local
267 t1_write_reg_4(adapter, A_ESPI_TRAIN, 0); in t1_espi_init()
269 if (is_T2(adapter)) { in t1_espi_init()
270 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, in t1_espi_init()
273 t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2, in t1_espi_init()
276 t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2, 0x800100); in t1_espi_init()
279 espi_setup_for_pm3393(adapter); in t1_espi_init()
281 espi_setup_for_vsc7321(adapter); in t1_espi_init()
284 espi_setup_for_ixf1010(adapter, nports); in t1_espi_init()
288 t1_write_reg_4(adapter, A_ESPI_FIFO_STATUS_ENABLE, in t1_espi_init()
291 if (is_T2(adapter)) { in t1_espi_init()
292 (void) tricn_init(adapter); in t1_espi_init()
297 espi->misc_ctrl = t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL); in t1_espi_init()
300 if (adapter->params.nports == 1) in t1_espi_init()
302 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl); in t1_espi_init()
311 if (is_T2(espi->adapter)) { in t1_espi_destroy()
317 struct peespi *t1_espi_create(adapter_t *adapter) in t1_espi_create() argument
322 espi->adapter = adapter; in t1_espi_create()
326 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val) in t1_espi_set_misc_ctrl() argument
328 struct peespi *espi = adapter->espi; in t1_espi_set_misc_ctrl()
330 if (!is_T2(adapter)) in t1_espi_set_misc_ctrl()
335 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl); in t1_espi_set_misc_ctrl()
339 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait) in t1_espi_get_mon() argument
341 struct peespi *espi = adapter->espi; in t1_espi_get_mon()
344 if (!is_T2(adapter)) return 0; in t1_espi_get_mon()
353 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, in t1_espi_get_mon()
355 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
356 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, in t1_espi_get_mon()
360 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
371 t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait) in t1_espi_get_mon_t204() argument
373 struct peespi *espi = adapter->espi; in t1_espi_get_mon_t204()
374 u8 i, nport = (u8)adapter->params.nports; in t1_espi_get_mon_t204()
384 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl); in t1_espi_get_mon_t204()
388 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, in t1_espi_get_mon_t204()
391 *valp = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3); in t1_espi_get_mon_t204()
394 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl); in t1_espi_get_mon_t204()