Lines Matching refs:ah
29 ath9k_hw_write_regs(struct ath_hal *ah, uint32_t modesIndex, uint32_t freqIndex, in ath9k_hw_write_regs() argument
32 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_write_regs()
39 ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_set_channel() argument
48 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ath9k_hw_set_channel()
69 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ath9k_hw_set_channel()
72 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_set_channel()
75 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_set_channel()
86 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ath9k_hw_set_channel()
102 REG_WRITE(ah, AR_PHY(0x37), reg32); in ath9k_hw_set_channel()
104 ah->ah_curchan = chan; in ath9k_hw_set_channel()
106 AH5416(ah)->ah_curchanRadIndex = -1; in ath9k_hw_set_channel()
112 ath9k_hw_ar9280_set_channel(struct ath_hal *ah, in ath9k_hw_ar9280_set_channel() argument
120 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ath9k_hw_ar9280_set_channel()
123 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ath9k_hw_ar9280_set_channel()
134 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ath9k_hw_ar9280_set_channel()
137 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_ar9280_set_channel()
140 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_ar9280_set_channel()
158 REG_RMW_FIELD(ah, AR_AN_SYNTH9, in ath9k_hw_ar9280_set_channel()
173 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ath9k_hw_ar9280_set_channel()
175 ah->ah_curchan = chan; in ath9k_hw_ar9280_set_channel()
177 AH5416(ah)->ah_curchanRadIndex = -1; in ath9k_hw_ar9280_set_channel()
209 ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, in ath9k_hw_set_rf_regs() argument
212 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_rf_regs()
220 if (AR_SREV_9280_10_OR_LATER(ah)) in ath9k_hw_set_rf_regs()
223 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV); in ath9k_hw_set_rf_regs()
243 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2); in ath9k_hw_set_rf_regs()
244 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2); in ath9k_hw_set_rf_regs()
250 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5); in ath9k_hw_set_rf_regs()
251 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5); in ath9k_hw_set_rf_regs()
283 ath9k_hw_rfdetach(struct ath_hal *ah) in ath9k_hw_rfdetach() argument
285 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_rfdetach()
336 ath9k_hw_init_rf(struct ath_hal *ah, int *status) in ath9k_hw_init_rf() argument
338 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_init_rf()
340 if (!AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_init_rf()
404 ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_decrease_chain_power() argument
408 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_decrease_chain_power()
431 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); in ath9k_hw_decrease_chain_power()
445 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); in ath9k_hw_decrease_chain_power()
447 REG_WRITE(ah, PHY_SWITCH_CHAIN_0, in ath9k_hw_decrease_chain_power()
448 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38) in ath9k_hw_decrease_chain_power()
449 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38)); in ath9k_hw_decrease_chain_power()