31 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,  in ath9k_hw_set_txq_interrupts()  argument
34 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_set_txq_interrupts()
42 	REG_WRITE(ah, AR_IMR_S0,  in ath9k_hw_set_txq_interrupts()
45 	REG_WRITE(ah, AR_IMR_S1,  in ath9k_hw_set_txq_interrupts()
48 	REG_RMW_FIELD(ah, AR_IMR_S2,  in ath9k_hw_set_txq_interrupts()
53 ath9k_hw_dmaRegDump(struct ath_hal *ah)  in ath9k_hw_dmaRegDump()  argument
60 	REG_WRITE(ah, AR_MACMISC,  in ath9k_hw_dmaRegDump()
71 		val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof (uint32_t)));  in ath9k_hw_dmaRegDump()
120 	    REG_READ(ah, AR_OBS_BUS_1)));  in ath9k_hw_dmaRegDump()
122 	    "AR_CR 0x%x \n", REG_READ(ah, AR_CR)));  in ath9k_hw_dmaRegDump()
126 ath9k_hw_gettxbuf(struct ath_hal *ah, uint32_t q)  in ath9k_hw_gettxbuf()  argument
128 	return (REG_READ(ah, AR_QTXDP(q)));  in ath9k_hw_gettxbuf()
132 ath9k_hw_puttxbuf(struct ath_hal *ah, uint32_t q, uint32_t txdp)  in ath9k_hw_puttxbuf()  argument
134 	REG_WRITE(ah, AR_QTXDP(q), txdp);  in ath9k_hw_puttxbuf()
140 ath9k_hw_txstart(struct ath_hal *ah, uint32_t q)  in ath9k_hw_txstart()  argument
145 	REG_WRITE(ah, AR_Q_TXE, 1 << q);  in ath9k_hw_txstart()
151 ath9k_hw_numtxpending(struct ath_hal *ah, uint32_t q)  in ath9k_hw_numtxpending()  argument
155 	npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;  in ath9k_hw_numtxpending()
158 		if (REG_READ(ah, AR_Q_TXE) & (1 << q))  in ath9k_hw_numtxpending()
166 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, boolean_t bIncTrigLevel)  in ath9k_hw_updatetxtriglevel()  argument
168 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_updatetxtriglevel()
172 	if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)  in ath9k_hw_updatetxtriglevel()
175 	omask = ath9k_hw_set_interrupts(ah,  in ath9k_hw_updatetxtriglevel()
178 	txcfg = REG_READ(ah, AR_TXCFG);  in ath9k_hw_updatetxtriglevel()
187 		REG_WRITE(ah, AR_TXCFG,  in ath9k_hw_updatetxtriglevel()
190 	(void) ath9k_hw_set_interrupts(ah, omask);  in ath9k_hw_updatetxtriglevel()
192 	ah->ah_txTrigLevel = (uint16_t)newLevel; /* ??? */  in ath9k_hw_updatetxtriglevel()
198 ath9k_hw_stoptxdma(struct ath_hal *ah, uint32_t q)  in ath9k_hw_stoptxdma()  argument
202 	REG_WRITE(ah, AR_Q_TXD, 1 << q);  in ath9k_hw_stoptxdma()
205 		if (ath9k_hw_numtxpending(ah, q) == 0)  in ath9k_hw_stoptxdma()
210 	if (ath9k_hw_numtxpending(ah, q)) {  in ath9k_hw_stoptxdma()
213 		    __func__, ath9k_hw_numtxpending(ah, q), q));  in ath9k_hw_stoptxdma()
216 			tsfLow = REG_READ(ah, AR_TSF_L32);  in ath9k_hw_stoptxdma()
217 			REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));  in ath9k_hw_stoptxdma()
218 			REG_WRITE(ah, AR_QUIET_PERIOD, 100);  in ath9k_hw_stoptxdma()
219 			REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);  in ath9k_hw_stoptxdma()
220 			REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);  in ath9k_hw_stoptxdma()
222 			if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))  in ath9k_hw_stoptxdma()
230 		REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);  in ath9k_hw_stoptxdma()
233 		REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);  in ath9k_hw_stoptxdma()
237 		while (ath9k_hw_numtxpending(ah, q)) {  in ath9k_hw_stoptxdma()
248 		REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);  in ath9k_hw_stoptxdma()
251 	REG_WRITE(ah, AR_Q_TXD, 0);  in ath9k_hw_stoptxdma()
258 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_filltxdesc()  argument
288 ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)  in ath9k_hw_cleartxdesc()  argument
300 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)  in ath9k_hw_txprocdesc()  argument
323 		(void) ath9k_hw_updatetxtriglevel(ah, B_TRUE);  in ath9k_hw_txprocdesc()
341 		(void) ath9k_hw_updatetxtriglevel(ah, B_TRUE);  in ath9k_hw_txprocdesc()
345 		(void) ath9k_hw_updatetxtriglevel(ah, B_TRUE);  in ath9k_hw_txprocdesc()
388 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_set11n_txdesc()  argument
393 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_set11n_txdesc()
416 	if (AR_SREV_9285(ah)) {  in ath9k_hw_set11n_txdesc()
427 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_set11n_ratescenario()  argument
487 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_set11n_aggr_first()  argument
499 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_set11n_aggr_middle()  argument
515 ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)  in ath9k_hw_set11n_aggr_last()  argument
526 ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)  in ath9k_hw_clr11n_aggr()  argument
535 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_set11n_burstduration()  argument
546 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_set11n_virtualmorefrag()  argument
558 ath9k_hw_gettxintrtxqs(struct ath_hal *ah, uint32_t *txqs)  in ath9k_hw_gettxintrtxqs()  argument
560 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_gettxintrtxqs()
567 ath9k_hw_set_txq_props(struct ath_hal *ah, int q,  in ath9k_hw_set_txq_props()  argument
571 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_set_txq_props()
572 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;  in ath9k_hw_set_txq_props()
639 ath9k_hw_get_txq_props(struct ath_hal *ah, int q,  in ath9k_hw_get_txq_props()  argument
642 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_get_txq_props()
643 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;  in ath9k_hw_get_txq_props()
678 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,  in ath9k_hw_setuptxqueue()  argument
681 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_setuptxqueue()
683 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;  in ath9k_hw_setuptxqueue()
744 		(void) ath9k_hw_set_txq_props(ah, q, qinfo);  in ath9k_hw_setuptxqueue()
751 ath9k_hw_releasetxqueue(struct ath_hal *ah, uint32_t q)  in ath9k_hw_releasetxqueue()  argument
753 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_releasetxqueue()
754 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;  in ath9k_hw_releasetxqueue()
779 	ath9k_hw_set_txq_interrupts(ah, qi);  in ath9k_hw_releasetxqueue()
785 ath9k_hw_resettxqueue(struct ath_hal *ah, uint32_t q)  in ath9k_hw_resettxqueue()  argument
787 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_resettxqueue()
788 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;  in ath9k_hw_resettxqueue()
789 	struct ath9k_channel *chan = ah->ah_curchan;  in ath9k_hw_resettxqueue()
823 	REG_WRITE(ah, AR_DLCL_IFS(q),  in ath9k_hw_resettxqueue()
828 	REG_WRITE(ah, AR_DRETRY_LIMIT(q),  in ath9k_hw_resettxqueue()
833 	REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);  in ath9k_hw_resettxqueue()
834 	REG_WRITE(ah, AR_DMISC(q),  in ath9k_hw_resettxqueue()
838 		REG_WRITE(ah, AR_QCBRCFG(q),  in ath9k_hw_resettxqueue()
841 		REG_WRITE(ah, AR_QMISC(q),  in ath9k_hw_resettxqueue()
842 		    REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |  in ath9k_hw_resettxqueue()
847 		REG_WRITE(ah, AR_QRDYTIMECFG(q),  in ath9k_hw_resettxqueue()
852 	REG_WRITE(ah, AR_DCHNTIME(q),  in ath9k_hw_resettxqueue()
858 		REG_WRITE(ah, AR_QMISC(q),  in ath9k_hw_resettxqueue()
859 		    REG_READ(ah, AR_QMISC(q)) |  in ath9k_hw_resettxqueue()
865 		REG_WRITE(ah, AR_DMISC(q),  in ath9k_hw_resettxqueue()
866 		    REG_READ(ah, AR_DMISC(q)) |  in ath9k_hw_resettxqueue()
870 		REG_WRITE(ah, AR_DMISC(q),  in ath9k_hw_resettxqueue()
871 		    REG_READ(ah, AR_DMISC(q)) |  in ath9k_hw_resettxqueue()
876 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |  in ath9k_hw_resettxqueue()
881 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |  in ath9k_hw_resettxqueue()
888 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |  in ath9k_hw_resettxqueue()
893 		    (ah->ah_config.sw_beacon_response_time -  in ath9k_hw_resettxqueue()
894 		    ah->ah_config.dma_beacon_response_time) -  in ath9k_hw_resettxqueue()
895 		    ah->ah_config.additional_swba_backoff) * 1024;  in ath9k_hw_resettxqueue()
896 		REG_WRITE(ah, AR_QRDYTIMECFG(q),  in ath9k_hw_resettxqueue()
898 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |  in ath9k_hw_resettxqueue()
903 		REG_WRITE(ah, AR_QMISC(q),  in ath9k_hw_resettxqueue()
904 		    REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);  in ath9k_hw_resettxqueue()
907 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |  in ath9k_hw_resettxqueue()
915 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |  in ath9k_hw_resettxqueue()
941 	ath9k_hw_set_txq_interrupts(ah, qi);  in ath9k_hw_resettxqueue()
948 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_rxprocdesc()  argument
980 	ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));  in ath9k_hw_rxprocdesc()
1016 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,  in ath9k_hw_setuprxdesc()  argument
1020 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;  in ath9k_hw_setuprxdesc()
1034 ath9k_hw_setrxabort(struct ath_hal *ah, boolean_t set)  in ath9k_hw_setrxabort()  argument
1039 		REG_SET_BIT(ah, AR_DIAG_SW,  in ath9k_hw_setrxabort()
1042 		if (!ath9k_hw_wait(ah, AR_OBS_BUS_1,  in ath9k_hw_setrxabort()
1044 			REG_CLR_BIT(ah, AR_DIAG_SW,  in ath9k_hw_setrxabort()
1047 			reg = REG_READ(ah, AR_OBS_BUS_1);  in ath9k_hw_setrxabort()
1056 		REG_CLR_BIT(ah, AR_DIAG_SW,  in ath9k_hw_setrxabort()
1064 ath9k_hw_putrxbuf(struct ath_hal *ah, uint32_t rxdp)  in ath9k_hw_putrxbuf()  argument
1066 	REG_WRITE(ah, AR_RXDP, rxdp);  in ath9k_hw_putrxbuf()
1070 ath9k_hw_rxena(struct ath_hal *ah)  in ath9k_hw_rxena()  argument
1072 	REG_WRITE(ah, AR_CR, AR_CR_RXE);  in ath9k_hw_rxena()
1076 ath9k_hw_startpcureceive(struct ath_hal *ah)  in ath9k_hw_startpcureceive()  argument
1078 	ath9k_enable_mib_counters(ah);  in ath9k_hw_startpcureceive()
1080 	ath9k_ani_reset(ah);  in ath9k_hw_startpcureceive()
1082 	REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));  in ath9k_hw_startpcureceive()
1086 ath9k_hw_stoppcurecv(struct ath_hal *ah)  in ath9k_hw_stoppcurecv()  argument
1088 	REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);  in ath9k_hw_stoppcurecv()
1090 	ath9k_hw_disable_mib_counters(ah);  in ath9k_hw_stoppcurecv()
1094 ath9k_hw_stopdmarecv(struct ath_hal *ah)  in ath9k_hw_stopdmarecv()  argument
1096 	REG_WRITE(ah, AR_CR, AR_CR_RXD);  in ath9k_hw_stopdmarecv()
1098 	if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {  in ath9k_hw_stopdmarecv()
1102 		    REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)));  in ath9k_hw_stopdmarecv()