Lines Matching refs:ah
47 static boolean_t ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type);
48 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
50 static uint32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
53 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
55 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
61 ath9k_hw_mac_usec(struct ath_hal *ah, uint32_t clks) in ath9k_hw_mac_usec() argument
63 if (ah->ah_curchan != NULL) in ath9k_hw_mac_usec()
65 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]); in ath9k_hw_mac_usec()
71 ath9k_hw_mac_to_usec(struct ath_hal *ah, uint32_t clks) in ath9k_hw_mac_to_usec() argument
73 struct ath9k_channel *chan = ah->ah_curchan; in ath9k_hw_mac_to_usec()
76 return (ath9k_hw_mac_usec(ah, clks) / 2); in ath9k_hw_mac_to_usec()
78 return (ath9k_hw_mac_usec(ah, clks)); in ath9k_hw_mac_to_usec()
82 ath9k_hw_mac_clks(struct ath_hal *ah, uint32_t usecs) in ath9k_hw_mac_clks() argument
84 if (ah->ah_curchan != NULL) in ath9k_hw_mac_clks()
85 return (usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, in ath9k_hw_mac_clks()
86 ah->ah_curchan)]); in ath9k_hw_mac_clks()
92 ath9k_hw_mac_to_clks(struct ath_hal *ah, uint32_t usecs) in ath9k_hw_mac_to_clks() argument
94 struct ath9k_channel *chan = ah->ah_curchan; in ath9k_hw_mac_to_clks()
97 return (ath9k_hw_mac_clks(ah, usecs) * 2); in ath9k_hw_mac_to_clks()
99 return (ath9k_hw_mac_clks(ah, usecs)); in ath9k_hw_mac_to_clks()
104 ath9k_hw_chan2wmode(struct ath_hal *ah, const struct ath9k_channel *chan) in ath9k_hw_chan2wmode() argument
115 ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask, uint32_t val) in ath9k_hw_wait() argument
120 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
127 reg, REG_READ(ah, reg), mask, val)); in ath9k_hw_wait()
146 ath9k_get_channel_edges(struct ath_hal *ah, in ath9k_get_channel_edges() argument
149 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_get_channel_edges()
165 ath9k_hw_computetxtime(struct ath_hal *ah, in ath9k_hw_computetxtime() argument
187 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { in ath9k_hw_computetxtime()
195 } else if (ah->ah_curchan && in ath9k_hw_computetxtime()
196 IS_CHAN_HALF_RATE(ah->ah_curchan)) { in ath9k_hw_computetxtime()
223 ath9k_hw_mhz2ieee(struct ath_hal *ah, uint32_t freq, uint32_t flags) in ath9k_hw_mhz2ieee() argument
233 if (ath9k_regd_is_public_safety_sku(ah) && in ath9k_hw_mhz2ieee()
248 if (ath9k_regd_is_public_safety_sku(ah) && in ath9k_hw_mhz2ieee()
264 ath9k_hw_get_channel_centers(struct ath_hal *ah, in ath9k_hw_get_channel_centers() argument
269 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_get_channel_centers()
300 ath9k_hw_read_revisions(struct ath_hal *ah) in ath9k_hw_read_revisions() argument
304 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
307 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
308 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; in ath9k_hw_read_revisions()
309 ah->ah_macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
310 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; in ath9k_hw_read_revisions()
312 if (!AR_SREV_9100(ah)) in ath9k_hw_read_revisions()
313 ah->ah_macVersion = MS(val, AR_SREV_VERSION); in ath9k_hw_read_revisions()
315 ah->ah_macRev = val & AR_SREV_REVISION; in ath9k_hw_read_revisions()
317 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) in ath9k_hw_read_revisions()
318 ah->ah_isPciExpress = B_TRUE; in ath9k_hw_read_revisions()
323 ath9k_hw_get_radiorev(struct ath_hal *ah) in ath9k_hw_get_radiorev() argument
328 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); in ath9k_hw_get_radiorev()
331 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); in ath9k_hw_get_radiorev()
332 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; in ath9k_hw_get_radiorev()
341 ath9k_hw_disablepcie(struct ath_hal *ah) in ath9k_hw_disablepcie() argument
343 if (!AR_SREV_9100(ah)) in ath9k_hw_disablepcie()
346 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
347 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
348 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
349 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
350 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
351 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
352 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
353 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
354 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
356 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
360 ath9k_hw_chip_test(struct ath_hal *ah) in ath9k_hw_chip_test() argument
372 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
375 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
376 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
389 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
390 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
401 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
429 ath9k_hw_set_defaults(struct ath_hal *ah) in ath9k_hw_set_defaults() argument
433 ah->ah_config.dma_beacon_response_time = 2; in ath9k_hw_set_defaults()
434 ah->ah_config.sw_beacon_response_time = 10; in ath9k_hw_set_defaults()
435 ah->ah_config.additional_swba_backoff = 0; in ath9k_hw_set_defaults()
436 ah->ah_config.ack_6mb = 0x0; in ath9k_hw_set_defaults()
437 ah->ah_config.cwm_ignore_extcca = 0; in ath9k_hw_set_defaults()
438 ah->ah_config.pcie_powersave_enable = 0; in ath9k_hw_set_defaults()
439 ah->ah_config.pcie_l1skp_enable = 0; in ath9k_hw_set_defaults()
440 ah->ah_config.pcie_clock_req = 0; in ath9k_hw_set_defaults()
441 ah->ah_config.pcie_power_reset = 0x100; in ath9k_hw_set_defaults()
442 ah->ah_config.pcie_restore = 0; in ath9k_hw_set_defaults()
443 ah->ah_config.pcie_waen = 0; in ath9k_hw_set_defaults()
444 ah->ah_config.analog_shiftreg = 1; in ath9k_hw_set_defaults()
445 ah->ah_config.ht_enable = 1; in ath9k_hw_set_defaults()
446 ah->ah_config.ofdm_trig_low = 200; in ath9k_hw_set_defaults()
447 ah->ah_config.ofdm_trig_high = 500; in ath9k_hw_set_defaults()
448 ah->ah_config.cck_trig_high = 200; in ath9k_hw_set_defaults()
449 ah->ah_config.cck_trig_low = 100; in ath9k_hw_set_defaults()
450 ah->ah_config.enable_ani = 1; in ath9k_hw_set_defaults()
451 ah->ah_config.noise_immunity_level = 4; in ath9k_hw_set_defaults()
452 ah->ah_config.ofdm_weaksignal_det = 1; in ath9k_hw_set_defaults()
453 ah->ah_config.cck_weaksignal_thr = 0; in ath9k_hw_set_defaults()
454 ah->ah_config.spur_immunity_level = 2; in ath9k_hw_set_defaults()
455 ah->ah_config.firstep_level = 0; in ath9k_hw_set_defaults()
456 ah->ah_config.rssi_thr_high = 40; in ath9k_hw_set_defaults()
457 ah->ah_config.rssi_thr_low = 7; in ath9k_hw_set_defaults()
458 ah->ah_config.diversity_control = 0; in ath9k_hw_set_defaults()
459 ah->ah_config.antenna_switch_swap = 0; in ath9k_hw_set_defaults()
462 ah->ah_config.spurchans[i][0] = AR_NO_SPUR; in ath9k_hw_set_defaults()
463 ah->ah_config.spurchans[i][1] = AR_NO_SPUR; in ath9k_hw_set_defaults()
466 ah->ah_config.intr_mitigation = 1; in ath9k_hw_set_defaults()
495 struct ath_hal *ah; in ath9k_hw_newstate() local
506 ah = &ahp->ah; in ath9k_hw_newstate()
507 ah->ah_sc = sc; in ath9k_hw_newstate()
508 ah->ah_sh = mem; in ath9k_hw_newstate()
509 ah->ah_magic = AR5416_MAGIC; in ath9k_hw_newstate()
510 ah->ah_countryCode = CTRY_DEFAULT; in ath9k_hw_newstate()
511 ah->ah_devid = device_id; in ath9k_hw_newstate()
512 ah->ah_subvendorid = 0; in ath9k_hw_newstate()
514 ah->ah_flags = 0; in ath9k_hw_newstate()
516 ah->ah_macVersion = AR_SREV_VERSION_9100; in ath9k_hw_newstate()
517 if (!AR_SREV_9100(ah)) in ath9k_hw_newstate()
518 ah->ah_flags = AH_USE_EEPROM; in ath9k_hw_newstate()
520 ah->ah_powerLimit = MAX_RATE_POWER; in ath9k_hw_newstate()
521 ah->ah_tpScale = ATH9K_TP_SCALE_MAX; in ath9k_hw_newstate()
523 ahp->ah_diversityControl = ah->ah_config.diversity_control; in ath9k_hw_newstate()
525 ah->ah_config.antenna_switch_swap; in ath9k_hw_newstate()
541 ath9k_hw_rfattach(struct ath_hal *ah) in ath9k_hw_rfattach() argument
546 rfStatus = ath9k_hw_init_rf(ah, &ecode); in ath9k_hw_rfattach()
558 ath9k_hw_rf_claim(struct ath_hal *ah) in ath9k_hw_rf_claim() argument
562 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ath9k_hw_rf_claim()
564 val = ath9k_hw_get_radiorev(ah); in ath9k_hw_rf_claim()
579 ah->ah_analog5GhzRev)); in ath9k_hw_rf_claim()
584 ah->ah_analog5GhzRev = (uint16_t)val; in ath9k_hw_rf_claim()
590 ath9k_hw_init_macaddr(struct ath_hal *ah) in ath9k_hw_init_macaddr() argument
595 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_init_macaddr()
599 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i)); in ath9k_hw_init_macaddr()
616 ath9k_hw_init_rxgain_ini(struct ath_hal *ah) in ath9k_hw_init_rxgain_ini() argument
619 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_init_rxgain_ini()
621 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { in ath9k_hw_init_rxgain_ini()
622 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); in ath9k_hw_init_rxgain_ini()
646 ath9k_hw_init_txgain_ini(struct ath_hal *ah) in ath9k_hw_init_txgain_ini() argument
649 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_init_txgain_ini()
651 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { in ath9k_hw_init_txgain_ini()
652 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); in ath9k_hw_init_txgain_ini()
672 ath9k_hw_post_attach(struct ath_hal *ah) in ath9k_hw_post_attach() argument
676 if (!ath9k_hw_chip_test(ah)) { in ath9k_hw_post_attach()
682 ecode = ath9k_hw_rf_claim(ah); in ath9k_hw_post_attach()
686 ecode = ath9k_hw_eeprom_attach(ah); in ath9k_hw_post_attach()
689 ecode = ath9k_hw_rfattach(ah); in ath9k_hw_post_attach()
693 if (!AR_SREV_9100(ah)) { in ath9k_hw_post_attach()
694 ath9k_hw_ani_setup(ah); in ath9k_hw_post_attach()
695 ath9k_hw_ani_attach(ah); in ath9k_hw_post_attach()
706 struct ath_hal *ah; in ath9k_hw_do_attach() local
715 ah = &ahp->ah; in ath9k_hw_do_attach()
717 ath9k_hw_set_defaults(ah); in ath9k_hw_do_attach()
719 if (ah->ah_config.intr_mitigation != 0) in ath9k_hw_do_attach()
722 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in ath9k_hw_do_attach()
729 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { in ath9k_hw_do_attach()
736 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { in ath9k_hw_do_attach()
737 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI || in ath9k_hw_do_attach()
738 (AR_SREV_9280(ah) && !ah->ah_isPciExpress)) { in ath9k_hw_do_attach()
739 ah->ah_config.serialize_regmode = in ath9k_hw_do_attach()
742 ah->ah_config.serialize_regmode = in ath9k_hw_do_attach()
748 ah->ah_config.serialize_regmode)); in ath9k_hw_do_attach()
750 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && in ath9k_hw_do_attach()
751 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && in ath9k_hw_do_attach()
752 (ah->ah_macVersion != AR_SREV_VERSION_9160) && in ath9k_hw_do_attach()
753 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && in ath9k_hw_do_attach()
754 (!AR_SREV_9285(ah))) { in ath9k_hw_do_attach()
757 ah->ah_macVersion, ah->ah_macRev)); in ath9k_hw_do_attach()
762 if (AR_SREV_9100(ah)) { in ath9k_hw_do_attach()
765 ah->ah_isPciExpress = B_FALSE; in ath9k_hw_do_attach()
767 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in ath9k_hw_do_attach()
769 if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_do_attach()
770 if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_do_attach()
790 if (AR_SREV_9160(ah)) { in ath9k_hw_do_attach()
791 ah->ah_config.enable_ani = 1; in ath9k_hw_do_attach()
796 if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_do_attach()
803 ah->ah_macVersion, ah->ah_macRev)); in ath9k_hw_do_attach()
805 if (AR_SREV_9285_12_OR_LATER(ah)) { in ath9k_hw_do_attach()
812 if (ah->ah_config.pcie_clock_req) { in ath9k_hw_do_attach()
823 } else if (AR_SREV_9285_10_OR_LATER(ah)) { in ath9k_hw_do_attach()
830 if (ah->ah_config.pcie_clock_req) { in ath9k_hw_do_attach()
841 } else if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_do_attach()
848 if (ah->ah_config.pcie_clock_req) { in ath9k_hw_do_attach()
862 } else if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_do_attach()
869 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_do_attach()
899 if (AR_SREV_9160_11(ah)) { in ath9k_hw_do_attach()
907 } else if (AR_SREV_9100_OR_LATER(ah)) { in ath9k_hw_do_attach()
975 if (ah->ah_isPciExpress) in ath9k_hw_do_attach()
976 ath9k_hw_configpcipowersave(ah, 0); in ath9k_hw_do_attach()
978 ath9k_hw_disablepcie(ah); in ath9k_hw_do_attach()
980 ecode = ath9k_hw_post_attach(ah); in ath9k_hw_do_attach()
985 if (AR_SREV_9280_20(ah)) in ath9k_hw_do_attach()
986 ath9k_hw_init_rxgain_ini(ah); in ath9k_hw_do_attach()
989 if (AR_SREV_9280_20(ah)) in ath9k_hw_do_attach()
990 ath9k_hw_init_txgain_ini(ah); in ath9k_hw_do_attach()
992 if (ah->ah_devid == AR9280_DEVID_PCI) { in ath9k_hw_do_attach()
1002 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom.def, in ath9k_hw_do_attach()
1008 if (!ath9k_hw_fill_cap_info(ah)) { in ath9k_hw_do_attach()
1014 ecode = ath9k_hw_init_macaddr(ah); in ath9k_hw_do_attach()
1022 if (AR_SREV_9285(ah)) in ath9k_hw_do_attach()
1023 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); in ath9k_hw_do_attach()
1025 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); in ath9k_hw_do_attach()
1027 ath9k_init_nfcal_hist_buffer(ah); in ath9k_hw_do_attach()
1029 return (ah); in ath9k_hw_do_attach()
1040 ath9k_hw_init_bb(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_init_bb() argument
1044 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ath9k_hw_init_bb()
1050 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ath9k_hw_init_bb()
1056 ath9k_hw_init_qos(struct ath_hal *ah) in ath9k_hw_init_qos() argument
1058 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
1059 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
1061 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
1066 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
1067 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
1068 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
1069 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
1070 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
1074 ath9k_hw_init_pll(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_init_pll() argument
1078 if (AR_SREV_9100(ah)) { in ath9k_hw_init_pll()
1084 if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_init_pll()
1096 if (AR_SREV_9280_20(ah)) { in ath9k_hw_init_pll()
1107 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_init_pll()
1134 REG_WRITE(ah, (uint16_t)(AR_RTC_PLL_CONTROL), pll); in ath9k_hw_init_pll()
1138 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
1142 ath9k_hw_init_chain_masks(struct ath_hal *ah) in ath9k_hw_init_chain_masks() argument
1144 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_init_chain_masks()
1152 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ath9k_hw_init_chain_masks()
1156 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) { in ath9k_hw_init_chain_masks()
1157 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ath9k_hw_init_chain_masks()
1158 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ath9k_hw_init_chain_masks()
1165 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ath9k_hw_init_chain_masks()
1166 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ath9k_hw_init_chain_masks()
1172 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); in ath9k_hw_init_chain_masks()
1174 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ath9k_hw_init_chain_masks()
1177 if (AR_SREV_9100(ah)) in ath9k_hw_init_chain_masks()
1178 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ath9k_hw_init_chain_masks()
1179 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ath9k_hw_init_chain_masks()
1183 ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode) in ath9k_hw_init_interrupt_masks() argument
1185 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_init_interrupt_masks()
1203 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); in ath9k_hw_init_interrupt_masks()
1204 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); in ath9k_hw_init_interrupt_masks()
1206 if (!AR_SREV_9100(ah)) { in ath9k_hw_init_interrupt_masks()
1207 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
1208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); in ath9k_hw_init_interrupt_masks()
1209 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
1214 ath9k_hw_set_ack_timeout(struct ath_hal *ah, uint32_t us) in ath9k_hw_set_ack_timeout() argument
1216 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_ack_timeout()
1218 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { in ath9k_hw_set_ack_timeout()
1225 REG_RMW_FIELD(ah, AR_TIME_OUT, in ath9k_hw_set_ack_timeout()
1226 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); in ath9k_hw_set_ack_timeout()
1233 ath9k_hw_set_cts_timeout(struct ath_hal *ah, uint32_t us) in ath9k_hw_set_cts_timeout() argument
1235 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_cts_timeout()
1237 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { in ath9k_hw_set_cts_timeout()
1244 REG_RMW_FIELD(ah, AR_TIME_OUT, in ath9k_hw_set_cts_timeout()
1245 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); in ath9k_hw_set_cts_timeout()
1252 ath9k_hw_set_global_txtimeout(struct ath_hal *ah, uint32_t tu) in ath9k_hw_set_global_txtimeout() argument
1254 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_global_txtimeout()
1264 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); in ath9k_hw_set_global_txtimeout()
1271 ath9k_hw_init_user_settings(struct ath_hal *ah) in ath9k_hw_init_user_settings() argument
1273 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_init_user_settings()
1279 REG_WRITE(ah, AR_PCU_MISC, in ath9k_hw_init_user_settings()
1280 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); in ath9k_hw_init_user_settings()
1282 (void) ath9k_hw_setslottime(ah, ahp->ah_slottime); in ath9k_hw_init_user_settings()
1284 (void) ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); in ath9k_hw_init_user_settings()
1286 (void) ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); in ath9k_hw_init_user_settings()
1289 (ah, ahp->ah_globaltxtimeout); in ath9k_hw_init_user_settings()
1300 ath9k_hw_detach(struct ath_hal *ah) in ath9k_hw_detach() argument
1302 if (!AR_SREV_9100(ah)) in ath9k_hw_detach()
1303 ath9k_hw_ani_detach(ah); in ath9k_hw_detach()
1305 ath9k_hw_rfdetach(ah); in ath9k_hw_detach()
1306 (void) ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); in ath9k_hw_detach()
1307 kmem_free(ah, sizeof (struct ath_hal_5416)); /* ???? */ in ath9k_hw_detach()
1314 struct ath_hal *ah = NULL; in ath9k_hw_attach() local
1323 ah = ath9k_hw_do_attach(device_id, sc, mem, error); in ath9k_hw_attach()
1330 return (ah); in ath9k_hw_attach()
1337 ath9k_hw_override_ini(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_override_ini() argument
1344 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ath9k_hw_override_ini()
1346 if (!AR_SREV_5416_V20_OR_LATER(ah) || in ath9k_hw_override_ini()
1347 AR_SREV_9280_10_OR_LATER(ah)) in ath9k_hw_override_ini()
1350 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ath9k_hw_override_ini()
1354 ath9k_hw_def_ini_fixup(struct ath_hal *ah, in ath9k_hw_def_ini_fixup() argument
1360 switch (ah->ah_devid) { in ath9k_hw_def_ini_fixup()
1395 ath9k_hw_ini_fixup(struct ath_hal *ah, struct ar5416_eeprom_def *pEepData, in ath9k_hw_ini_fixup() argument
1398 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_ini_fixup()
1403 return (ath9k_hw_def_ini_fixup(ah, pEepData, reg, value)); in ath9k_hw_ini_fixup()
1407 ath9k_hw_process_ini(struct ath_hal *ah, in ath9k_hw_process_ini() argument
1412 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_process_ini()
1445 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ath9k_hw_process_ini()
1447 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ath9k_hw_process_ini()
1449 ath9k_hw_set_addac(ah, chan); in ath9k_hw_process_ini()
1451 if (AR_SREV_5416_V22_OR_LATER(ah)) { in ath9k_hw_process_ini()
1473 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ath9k_hw_process_ini()
1479 REG_WRITE(ah, reg, val); in ath9k_hw_process_ini()
1482 ah->ah_config.analog_shiftreg) { in ath9k_hw_process_ini()
1490 if (AR_SREV_9280(ah)) { in ath9k_hw_process_ini()
1496 if (AR_SREV_9280(ah)) { in ath9k_hw_process_ini()
1506 REG_WRITE(ah, reg, val); in ath9k_hw_process_ini()
1509 ah->ah_config.analog_shiftreg) { in ath9k_hw_process_ini()
1517 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); in ath9k_hw_process_ini()
1519 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { in ath9k_hw_process_ini()
1525 ath9k_hw_override_ini(ah, chan); in ath9k_hw_process_ini()
1526 ath9k_hw_set_regs(ah, chan, macmode); in ath9k_hw_process_ini()
1527 ath9k_hw_init_chain_masks(ah); in ath9k_hw_process_ini()
1529 status = ath9k_hw_set_txpower(ah, chan, in ath9k_hw_process_ini()
1530 ath9k_regd_get_ctl(ah, chan), in ath9k_hw_process_ini()
1531 ath9k_regd_get_antenna_allowed(ah, chan), in ath9k_hw_process_ini()
1534 (uint32_t)ah->ah_powerLimit)); in ath9k_hw_process_ini()
1542 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { in ath9k_hw_process_ini()
1555 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_set_rfmode() argument
1565 if (!AR_SREV_9280_10_OR_LATER(ah)) in ath9k_hw_set_rfmode()
1569 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) in ath9k_hw_set_rfmode()
1573 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ath9k_hw_set_rfmode()
1577 ath9k_hw_mark_phy_inactive(struct ath_hal *ah) in ath9k_hw_mark_phy_inactive() argument
1579 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ath9k_hw_mark_phy_inactive()
1583 ath9k_hw_set_dma(struct ath_hal *ah) in ath9k_hw_set_dma() argument
1587 regval = REG_READ(ah, AR_AHB_MODE); in ath9k_hw_set_dma()
1588 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1590 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; in ath9k_hw_set_dma()
1591 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); in ath9k_hw_set_dma()
1593 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); in ath9k_hw_set_dma()
1595 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; in ath9k_hw_set_dma()
1596 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); in ath9k_hw_set_dma()
1598 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1600 if (AR_SREV_9285(ah)) { in ath9k_hw_set_dma()
1601 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, in ath9k_hw_set_dma()
1604 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, in ath9k_hw_set_dma()
1610 ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) in ath9k_hw_set_operating_mode() argument
1614 val = REG_READ(ah, AR_STA_ID1); in ath9k_hw_set_operating_mode()
1618 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP | in ath9k_hw_set_operating_mode()
1620 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1623 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC | in ath9k_hw_set_operating_mode()
1625 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1629 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); in ath9k_hw_set_operating_mode()
1636 ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, in ath9k_hw_get_delta_slope_vals() argument
1656 ath9k_hw_set_delta_slope(struct ath_hal *ah, in ath9k_hw_set_delta_slope() argument
1668 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ath9k_hw_set_delta_slope()
1671 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ath9k_hw_set_delta_slope()
1674 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ath9k_hw_set_delta_slope()
1676 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ath9k_hw_set_delta_slope()
1681 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ath9k_hw_set_delta_slope()
1684 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ath9k_hw_set_delta_slope()
1686 REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ath9k_hw_set_delta_slope()
1691 ath9k_hw_set_reset(struct ath_hal *ah, int type) in ath9k_hw_set_reset() argument
1696 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1699 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1703 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); in ath9k_hw_set_reset()
1707 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1708 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_hw_set_reset()
1710 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1718 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), rst_flags); in ath9k_hw_set_reset()
1721 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), 0); in ath9k_hw_set_reset()
1722 if (!ath9k_hw_wait(ah, (uint16_t)(AR_RTC_RC), AR_RTC_RC_M, 0)) { in ath9k_hw_set_reset()
1729 if (!AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1730 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1732 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_set_reset()
1734 if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1741 ath9k_hw_set_reset_power_on(struct ath_hal *ah) in ath9k_hw_set_reset_power_on() argument
1743 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1746 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 0); in ath9k_hw_set_reset_power_on()
1747 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 1); in ath9k_hw_set_reset_power_on()
1749 if (!ath9k_hw_wait(ah, in ath9k_hw_set_reset_power_on()
1760 ath9k_hw_read_revisions(ah); in ath9k_hw_set_reset_power_on()
1762 return (ath9k_hw_set_reset(ah, ATH9K_RESET_WARM)); in ath9k_hw_set_reset_power_on()
1766 ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type) in ath9k_hw_set_reset_reg() argument
1768 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1773 return (ath9k_hw_set_reset_power_on(ah)); in ath9k_hw_set_reset_reg()
1776 return (ath9k_hw_set_reset(ah, type)); in ath9k_hw_set_reset_reg()
1783 ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, in ath9k_hw_set_regs() argument
1788 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_regs()
1790 if (AR_SREV_9285_10_OR_LATER(ah)) in ath9k_hw_set_regs()
1791 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ath9k_hw_set_regs()
1807 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ath9k_hw_set_regs()
1809 ath9k_hw_set11nmac2040(ah, macmode); in ath9k_hw_set_regs()
1811 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ath9k_hw_set_regs()
1812 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ath9k_hw_set_regs()
1816 ath9k_hw_chip_reset(struct ath_hal *ah, in ath9k_hw_chip_reset() argument
1819 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_chip_reset()
1821 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) in ath9k_hw_chip_reset()
1824 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_chip_reset()
1829 ath9k_hw_init_pll(ah, chan); in ath9k_hw_chip_reset()
1831 ath9k_hw_set_rfmode(ah, chan); in ath9k_hw_chip_reset()
1837 ath9k_hw_check_chan(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_check_chan() argument
1858 return (ath9k_regd_check_channel(ah, chan)); in ath9k_hw_check_chan()
1862 ath9k_hw_channel_change(struct ath_hal *ah, in ath9k_hw_channel_change() argument
1869 if (ath9k_hw_numtxpending(ah, qnum)) { in ath9k_hw_channel_change()
1878 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ath9k_hw_channel_change()
1879 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ath9k_hw_channel_change()
1887 ath9k_hw_set_regs(ah, chan, macmode); in ath9k_hw_channel_change()
1889 if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_channel_change()
1890 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { in ath9k_hw_channel_change()
1896 if (!(ath9k_hw_set_channel(ah, chan))) { in ath9k_hw_channel_change()
1904 if (ath9k_hw_set_txpower(ah, chan, in ath9k_hw_channel_change()
1905 ath9k_regd_get_ctl(ah, chan), in ath9k_hw_channel_change()
1906 ath9k_regd_get_antenna_allowed(ah, chan), in ath9k_hw_channel_change()
1909 (uint32_t)ah->ah_powerLimit)) != 0) { in ath9k_hw_channel_change()
1916 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ath9k_hw_channel_change()
1924 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ath9k_hw_channel_change()
1927 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_channel_change()
1929 if (AR_SREV_9280_10_OR_LATER(ah)) in ath9k_hw_channel_change()
1930 ath9k_hw_9280_spur_mitigate(ah, chan); in ath9k_hw_channel_change()
1932 ath9k_hw_spur_mitigate(ah, chan); in ath9k_hw_channel_change()
1941 ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_9280_spur_mitigate() argument
1972 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ath9k_hw_9280_spur_mitigate()
1975 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; in ath9k_hw_9280_spur_mitigate()
1977 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); in ath9k_hw_9280_spur_mitigate()
2002 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ath9k_hw_9280_spur_mitigate()
2006 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ath9k_hw_9280_spur_mitigate()
2012 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ath9k_hw_9280_spur_mitigate()
2018 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ath9k_hw_9280_spur_mitigate()
2025 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ath9k_hw_9280_spur_mitigate()
2055 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ath9k_hw_9280_spur_mitigate()
2058 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ath9k_hw_9280_spur_mitigate()
2076 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ath9k_hw_9280_spur_mitigate()
2077 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ath9k_hw_9280_spur_mitigate()
2110 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2111 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2121 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2122 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2132 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2133 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2143 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2144 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2154 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2155 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2165 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2166 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2176 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2177 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2187 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2188 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ath9k_hw_9280_spur_mitigate()
2192 ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) in ath9k_hw_spur_mitigate() argument
2221 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); in ath9k_hw_spur_mitigate()
2236 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ath9k_hw_spur_mitigate()
2242 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ath9k_hw_spur_mitigate()
2249 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ath9k_hw_spur_mitigate()
2260 REG_WRITE(ah, AR_PHY_TIMING11, new); in ath9k_hw_spur_mitigate()
2278 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ath9k_hw_spur_mitigate()
2279 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ath9k_hw_spur_mitigate()
2312 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ath9k_hw_spur_mitigate()
2313 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ath9k_hw_spur_mitigate()
2323 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ath9k_hw_spur_mitigate()
2324 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ath9k_hw_spur_mitigate()
2334 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ath9k_hw_spur_mitigate()
2335 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ath9k_hw_spur_mitigate()
2345 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ath9k_hw_spur_mitigate()
2346 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ath9k_hw_spur_mitigate()
2356 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ath9k_hw_spur_mitigate()
2357 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ath9k_hw_spur_mitigate()
2367 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ath9k_hw_spur_mitigate()
2368 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ath9k_hw_spur_mitigate()
2378 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ath9k_hw_spur_mitigate()
2379 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ath9k_hw_spur_mitigate()
2389 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ath9k_hw_spur_mitigate()
2390 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ath9k_hw_spur_mitigate()
2394 ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, in ath9k_hw_reset() argument
2401 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_reset()
2402 struct ath9k_channel *curchan = ah->ah_curchan; in ath9k_hw_reset()
2412 if (AR_SREV_9280(ah)) { in ath9k_hw_reset()
2417 if (ath9k_hw_check_chan(ah, chan) == NULL) { in ath9k_hw_reset()
2425 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { in ath9k_hw_reset()
2433 (void) ath9k_hw_getnf(ah, curchan); in ath9k_hw_reset()
2437 (ah->ah_curchan != NULL) && in ath9k_hw_reset()
2438 (chan->channel != ah->ah_curchan->channel) && in ath9k_hw_reset()
2440 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && in ath9k_hw_reset()
2441 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && in ath9k_hw_reset()
2442 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) { in ath9k_hw_reset()
2444 if (ath9k_hw_channel_change(ah, chan, macmode)) { in ath9k_hw_reset()
2445 ath9k_hw_loadnf(ah, ah->ah_curchan); in ath9k_hw_reset()
2446 ath9k_hw_start_nfcal(ah); in ath9k_hw_reset()
2451 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); in ath9k_hw_reset()
2455 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; in ath9k_hw_reset()
2457 saveLedState = REG_READ(ah, AR_CFG_LED) & in ath9k_hw_reset()
2461 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_reset()
2463 if (!ath9k_hw_chip_reset(ah, chan)) { in ath9k_hw_reset()
2470 if (AR_SREV_9280(ah)) { in ath9k_hw_reset()
2471 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_reset()
2473 if (is_set(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) { in ath9k_hw_reset()
2475 ath9k_hw_set_gpio(ah, 9, 0); in ath9k_hw_reset()
2477 ath9k_hw_set_gpio(ah, 9, 1); in ath9k_hw_reset()
2479 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); in ath9k_hw_reset()
2482 ecode = ath9k_hw_process_ini(ah, chan, macmode); in ath9k_hw_reset()
2489 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_reset()
2491 if (AR_SREV_9280_10_OR_LATER(ah)) in ath9k_hw_reset()
2492 ath9k_hw_9280_spur_mitigate(ah, chan); in ath9k_hw_reset()
2494 ath9k_hw_spur_mitigate(ah, chan); in ath9k_hw_reset()
2496 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { in ath9k_hw_reset()
2503 ath9k_hw_decrease_chain_power(ah, chan); in ath9k_hw_reset()
2505 REG_WRITE(ah, AR_STA_ID0, ARN_LE_READ_32(ahp->ah_macaddr)); in ath9k_hw_reset()
2506 REG_WRITE(ah, AR_STA_ID1, ARN_LE_READ_16(ahp->ah_macaddr + 4) | in ath9k_hw_reset()
2509 (ah->ah_config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) | in ath9k_hw_reset()
2511 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); in ath9k_hw_reset()
2513 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask)); in ath9k_hw_reset()
2514 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4)); in ath9k_hw_reset()
2516 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset()
2518 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid)); in ath9k_hw_reset()
2519 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) | in ath9k_hw_reset()
2522 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset()
2524 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset()
2526 if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_reset()
2527 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { in ath9k_hw_reset()
2535 if (!(ath9k_hw_set_channel(ah, chan))) { in ath9k_hw_reset()
2544 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_reset()
2547 for (i = 0; i < ah->ah_caps.total_queues; i++) in ath9k_hw_reset()
2548 (void) ath9k_hw_resettxqueue(ah, i); in ath9k_hw_reset()
2550 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); in ath9k_hw_reset()
2551 ath9k_hw_init_qos(ah); in ath9k_hw_reset()
2554 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
2555 ath9k_enable_rfkill(ah); in ath9k_hw_reset()
2557 ath9k_hw_init_user_settings(ah); in ath9k_hw_reset()
2559 REG_WRITE(ah, AR_STA_ID1, in ath9k_hw_reset()
2560 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
2562 ath9k_hw_set_dma(ah); in ath9k_hw_reset()
2564 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
2568 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); in ath9k_hw_reset()
2569 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); in ath9k_hw_reset()
2572 ath9k_hw_init_bb(ah, chan); in ath9k_hw_reset()
2574 if (!ath9k_hw_init_cal(ah, chan)) { in ath9k_hw_reset()
2581 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ath9k_hw_reset()
2582 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ath9k_hw_reset()
2585 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
2587 if (AR_SREV_9100(ah)) { in ath9k_hw_reset()
2589 mask = REG_READ(ah, AR_CFG); in ath9k_hw_reset()
2597 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_reset()
2600 __func__, REG_READ(ah, AR_CFG))); in ath9k_hw_reset()
2606 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_reset()
2620 ath9k_hw_keyreset(struct ath_hal *ah, uint16_t entry) in ath9k_hw_keyreset() argument
2624 if (entry >= ah->ah_caps.keycache_size) { in ath9k_hw_keyreset()
2631 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); in ath9k_hw_keyreset()
2633 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath9k_hw_keyreset()
2634 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath9k_hw_keyreset()
2635 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath9k_hw_keyreset()
2636 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath9k_hw_keyreset()
2637 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath9k_hw_keyreset()
2638 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath9k_hw_keyreset()
2639 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath9k_hw_keyreset()
2640 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath9k_hw_keyreset()
2643 ATH9K_IS_MIC_ENABLED(ah)) { in ath9k_hw_keyreset()
2646 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ath9k_hw_keyreset()
2647 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); in ath9k_hw_keyreset()
2648 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); in ath9k_hw_keyreset()
2649 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); in ath9k_hw_keyreset()
2653 if (ah->ah_curchan == NULL) in ath9k_hw_keyreset()
2660 ath9k_hw_keysetmac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac) in ath9k_hw_keysetmac() argument
2664 if (entry >= ah->ah_caps.keycache_size) { in ath9k_hw_keysetmac()
2682 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); in ath9k_hw_keysetmac()
2683 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); in ath9k_hw_keysetmac()
2689 ath9k_hw_set_keycache_entry(struct ath_hal *ah, uint16_t entry, in ath9k_hw_set_keycache_entry() argument
2692 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_set_keycache_entry()
2698 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_keycache_entry()
2715 ah->ah_macRev)); in ath9k_hw_set_keycache_entry()
2722 if (ATH9K_IS_MIC_ENABLED(ah) && in ath9k_hw_set_keycache_entry()
2763 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { in ath9k_hw_set_keycache_entry()
2766 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); in ath9k_hw_set_keycache_entry()
2767 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); in ath9k_hw_set_keycache_entry()
2768 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); in ath9k_hw_set_keycache_entry()
2769 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); in ath9k_hw_set_keycache_entry()
2770 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); in ath9k_hw_set_keycache_entry()
2771 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); in ath9k_hw_set_keycache_entry()
2772 (void) ath9k_hw_keysetmac(ah, entry, mac); in ath9k_hw_set_keycache_entry()
2781 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); in ath9k_hw_set_keycache_entry()
2782 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); in ath9k_hw_set_keycache_entry()
2783 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); in ath9k_hw_set_keycache_entry()
2784 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); in ath9k_hw_set_keycache_entry()
2785 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); in ath9k_hw_set_keycache_entry()
2786 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), in ath9k_hw_set_keycache_entry()
2793 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); in ath9k_hw_set_keycache_entry()
2794 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); in ath9k_hw_set_keycache_entry()
2795 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); in ath9k_hw_set_keycache_entry()
2796 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); in ath9k_hw_set_keycache_entry()
2797 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); in ath9k_hw_set_keycache_entry()
2798 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), in ath9k_hw_set_keycache_entry()
2801 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); in ath9k_hw_set_keycache_entry()
2802 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); in ath9k_hw_set_keycache_entry()
2803 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); in ath9k_hw_set_keycache_entry()
2804 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); in ath9k_hw_set_keycache_entry()
2806 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); in ath9k_hw_set_keycache_entry()
2807 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); in ath9k_hw_set_keycache_entry()
2808 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); in ath9k_hw_set_keycache_entry()
2809 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); in ath9k_hw_set_keycache_entry()
2810 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); in ath9k_hw_set_keycache_entry()
2811 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); in ath9k_hw_set_keycache_entry()
2813 (void) ath9k_hw_keysetmac(ah, entry, mac); in ath9k_hw_set_keycache_entry()
2816 if (ah->ah_curchan == NULL) in ath9k_hw_set_keycache_entry()
2823 ath9k_hw_keyisvalid(struct ath_hal *ah, uint16_t entry) in ath9k_hw_keyisvalid() argument
2825 if (entry < ah->ah_caps.keycache_size) { in ath9k_hw_keyisvalid()
2826 uint32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); in ath9k_hw_keyisvalid()
2836 ath9k_set_power_sleep(struct ath_hal *ah, int setChip) in ath9k_set_power_sleep() argument
2838 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
2840 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_sleep()
2842 if (!AR_SREV_9100(ah)) in ath9k_set_power_sleep()
2843 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2845 REG_CLR_BIT(ah, (uint16_t)(AR_RTC_RESET), in ath9k_set_power_sleep()
2851 ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) in ath9k_set_power_network_sleep() argument
2853 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
2855 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_set_power_network_sleep()
2858 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2861 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2868 ath9k_hw_set_power_awake(struct ath_hal *ah, int setChip) in ath9k_hw_set_power_awake() argument
2874 if ((REG_READ(ah, AR_RTC_STATUS) & in ath9k_hw_set_power_awake()
2876 if (ath9k_hw_set_reset_reg(ah, in ath9k_hw_set_power_awake()
2881 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2882 REG_SET_BIT(ah, AR_RTC_RESET, in ath9k_hw_set_power_awake()
2885 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2890 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; in ath9k_hw_set_power_awake()
2894 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2907 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2913 ath9k_hw_setpower(struct ath_hal *ah, enum ath9k_power_mode mode) in ath9k_hw_setpower() argument
2915 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_setpower()
2931 status = ath9k_hw_set_power_awake(ah, setChip); in ath9k_hw_setpower()
2934 ath9k_set_power_sleep(ah, setChip); in ath9k_hw_setpower()
2938 ath9k_set_power_network_sleep(ah, setChip); in ath9k_hw_setpower()
2951 ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) in ath9k_hw_configpcipowersave() argument
2953 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_configpcipowersave()
2956 if (ah->ah_isPciExpress != B_TRUE) in ath9k_hw_configpcipowersave()
2959 if (ah->ah_config.pcie_powersave_enable == 2) in ath9k_hw_configpcipowersave()
2965 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_configpcipowersave()
2967 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), in ath9k_hw_configpcipowersave()
2971 } else if (AR_SREV_9280(ah) && in ath9k_hw_configpcipowersave()
2972 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) { in ath9k_hw_configpcipowersave()
2973 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); in ath9k_hw_configpcipowersave()
2974 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_configpcipowersave()
2976 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); in ath9k_hw_configpcipowersave()
2977 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); in ath9k_hw_configpcipowersave()
2978 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); in ath9k_hw_configpcipowersave()
2980 if (ah->ah_config.pcie_clock_req) in ath9k_hw_configpcipowersave()
2981 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); in ath9k_hw_configpcipowersave()
2983 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); in ath9k_hw_configpcipowersave()
2985 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_configpcipowersave()
2986 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_configpcipowersave()
2987 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); in ath9k_hw_configpcipowersave()
2989 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_configpcipowersave()
2993 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_configpcipowersave()
2994 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_configpcipowersave()
2995 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); in ath9k_hw_configpcipowersave()
2996 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); in ath9k_hw_configpcipowersave()
2997 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); in ath9k_hw_configpcipowersave()
2998 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); in ath9k_hw_configpcipowersave()
2999 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_configpcipowersave()
3000 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_configpcipowersave()
3001 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); in ath9k_hw_configpcipowersave()
3002 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_configpcipowersave()
3005 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ath9k_hw_configpcipowersave()
3007 if (ah->ah_config.pcie_waen) { in ath9k_hw_configpcipowersave()
3008 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); in ath9k_hw_configpcipowersave()
3010 if (AR_SREV_9285(ah)) in ath9k_hw_configpcipowersave()
3011 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); in ath9k_hw_configpcipowersave()
3012 else if (AR_SREV_9280(ah)) in ath9k_hw_configpcipowersave()
3013 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); in ath9k_hw_configpcipowersave()
3015 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); in ath9k_hw_configpcipowersave()
3022 ath9k_hw_intrpend(struct ath_hal *ah) in ath9k_hw_intrpend() argument
3026 if (AR_SREV_9100(ah)) in ath9k_hw_intrpend()
3029 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); in ath9k_hw_intrpend()
3033 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); in ath9k_hw_intrpend()
3043 ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) in ath9k_hw_getisr() argument
3047 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_getisr()
3050 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_getisr()
3052 if (!AR_SREV_9100(ah)) { in ath9k_hw_getisr()
3053 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { in ath9k_hw_getisr()
3054 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ath9k_hw_getisr()
3056 isr = REG_READ(ah, AR_ISR); in ath9k_hw_getisr()
3060 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & in ath9k_hw_getisr()
3069 isr = REG_READ(ah, AR_ISR); in ath9k_hw_getisr()
3075 isr2 = REG_READ(ah, AR_ISR_S2); in ath9k_hw_getisr()
3090 isr = REG_READ(ah, AR_ISR_RAC); in ath9k_hw_getisr()
3112 s0_s = REG_READ(ah, AR_ISR_S0_S); in ath9k_hw_getisr()
3116 s1_s = REG_READ(ah, AR_ISR_S1_S); in ath9k_hw_getisr()
3126 if (!AR_SREV_9100(ah)) { in ath9k_hw_getisr()
3128 uint32_t isr5 = REG_READ(ah, AR_ISR_S5_S); in ath9k_hw_getisr()
3137 if (AR_SREV_9100(ah)) in ath9k_hw_getisr()
3162 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); in ath9k_hw_getisr()
3163 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_getisr()
3172 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); in ath9k_hw_getisr()
3173 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); in ath9k_hw_getisr()
3180 ath9k_hw_intrget(struct ath_hal *ah) in ath9k_hw_intrget() argument
3182 return (AH5416(ah)->ah_maskReg); in ath9k_hw_intrget()
3186 ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) in ath9k_hw_set_interrupts() argument
3188 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_interrupts()
3191 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_set_interrupts()
3202 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); in ath9k_hw_set_interrupts()
3203 (void) REG_READ(ah, AR_IER); in ath9k_hw_set_interrupts()
3204 if (!AR_SREV_9100(ah)) { in ath9k_hw_set_interrupts()
3205 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); in ath9k_hw_set_interrupts()
3206 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); in ath9k_hw_set_interrupts()
3208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_interrupts()
3209 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); in ath9k_hw_set_interrupts()
3256 REG_WRITE(ah, AR_IMR, mask); in ath9k_hw_set_interrupts()
3257 mask = REG_READ(ah, AR_IMR_S2) & in ath9k_hw_set_interrupts()
3266 REG_WRITE(ah, AR_IMR_S2, mask | mask2); in ath9k_hw_set_interrupts()
3271 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
3273 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
3277 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); in ath9k_hw_set_interrupts()
3278 if (!AR_SREV_9100(ah)) { in ath9k_hw_set_interrupts()
3279 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, in ath9k_hw_set_interrupts()
3281 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); in ath9k_hw_set_interrupts()
3284 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, in ath9k_hw_set_interrupts()
3286 REG_WRITE(ah, AR_INTR_SYNC_MASK, in ath9k_hw_set_interrupts()
3298 ath9k_hw_beaconinit(struct ath_hal *ah, uint32_t next_beacon, in ath9k_hw_beaconinit() argument
3301 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_beaconinit()
3306 switch (ah->ah_opmode) { in ath9k_hw_beaconinit()
3309 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); in ath9k_hw_beaconinit()
3310 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); in ath9k_hw_beaconinit()
3311 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); in ath9k_hw_beaconinit()
3315 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
3317 REG_WRITE(ah, AR_NEXT_NDP_TIMER, in ath9k_hw_beaconinit()
3324 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); in ath9k_hw_beaconinit()
3325 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, in ath9k_hw_beaconinit()
3327 ah->ah_config. in ath9k_hw_beaconinit()
3329 REG_WRITE(ah, AR_NEXT_SWBA, in ath9k_hw_beaconinit()
3331 ah->ah_config. in ath9k_hw_beaconinit()
3339 __func__, ah->ah_opmode)); in ath9k_hw_beaconinit()
3343 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); in ath9k_hw_beaconinit()
3344 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); in ath9k_hw_beaconinit()
3345 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); in ath9k_hw_beaconinit()
3346 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); in ath9k_hw_beaconinit()
3351 ath9k_hw_reset_tsf(ah); in ath9k_hw_beaconinit()
3354 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
3358 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, in ath9k_hw_set_sta_beacon_timers() argument
3362 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_set_sta_beacon_timers()
3364 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); in ath9k_hw_set_sta_beacon_timers()
3366 REG_WRITE(ah, AR_BEACON_PERIOD, in ath9k_hw_set_sta_beacon_timers()
3368 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, in ath9k_hw_set_sta_beacon_timers()
3371 REG_RMW_FIELD(ah, AR_RSSI_THR, in ath9k_hw_set_sta_beacon_timers()
3397 REG_WRITE(ah, AR_NEXT_DTIM, in ath9k_hw_set_sta_beacon_timers()
3399 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); in ath9k_hw_set_sta_beacon_timers()
3401 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
3410 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
3413 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); in ath9k_hw_set_sta_beacon_timers()
3414 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); in ath9k_hw_set_sta_beacon_timers()
3416 REG_SET_BIT(ah, AR_TIMER_MODE, in ath9k_hw_set_sta_beacon_timers()
3422 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
3428 ath9k_hw_fill_cap_info(struct ath_hal *ah) in ath9k_hw_fill_cap_info() argument
3430 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_fill_cap_info()
3431 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_fill_cap_info()
3434 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0); in ath9k_hw_fill_cap_info()
3436 ah->ah_currentRD = eeval; in ath9k_hw_fill_cap_info()
3438 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1); in ath9k_hw_fill_cap_info()
3439 ah->ah_currentRDExt = eeval; in ath9k_hw_fill_cap_info()
3441 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); in ath9k_hw_fill_cap_info()
3443 if (ah->ah_opmode != ATH9K_M_HOSTAP && in ath9k_hw_fill_cap_info()
3444 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { in ath9k_hw_fill_cap_info()
3445 if (ah->ah_currentRD == 0x64 || in ath9k_hw_fill_cap_info()
3446 ah->ah_currentRD == 0x65) in ath9k_hw_fill_cap_info()
3447 ah->ah_currentRD += 5; in ath9k_hw_fill_cap_info()
3448 else if (ah->ah_currentRD == 0x41) in ath9k_hw_fill_cap_info()
3449 ah->ah_currentRD = 0x43; in ath9k_hw_fill_cap_info()
3453 ah->ah_currentRD)); in ath9k_hw_fill_cap_info()
3456 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); in ath9k_hw_fill_cap_info()
3462 if (ah->ah_config.ht_enable) { in ath9k_hw_fill_cap_info()
3478 if (ah->ah_config.ht_enable) { in ath9k_hw_fill_cap_info()
3491 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK); in ath9k_hw_fill_cap_info()
3492 if ((ah->ah_isPciExpress) || in ath9k_hw_fill_cap_info()
3495 ath9k_hw_get_eeprom(ah, EEP_RX_MASK); in ath9k_hw_fill_cap_info()
3498 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
3501 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0))) in ath9k_hw_fill_cap_info()
3520 if (ah->ah_config.ht_enable) in ath9k_hw_fill_cap_info()
3546 if (AR_SREV_9280_10_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
3551 if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
3559 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { in ath9k_hw_fill_cap_info()
3569 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT); in ath9k_hw_fill_cap_info()
3570 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { in ath9k_hw_fill_cap_info()
3571 ah->ah_rfkill_gpio = in ath9k_hw_fill_cap_info()
3572 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); in ath9k_hw_fill_cap_info()
3573 ah->ah_rfkill_polarity = in ath9k_hw_fill_cap_info()
3574 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); in ath9k_hw_fill_cap_info()
3580 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || in ath9k_hw_fill_cap_info()
3581 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || in ath9k_hw_fill_cap_info()
3582 (ah->ah_macVersion == AR_SREV_VERSION_9160) || in ath9k_hw_fill_cap_info()
3583 (ah->ah_macVersion == AR_SREV_VERSION_9100) || in ath9k_hw_fill_cap_info()
3584 (ah->ah_macVersion == AR_SREV_VERSION_9280)) in ath9k_hw_fill_cap_info()
3589 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) in ath9k_hw_fill_cap_info()
3594 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) { in ath9k_hw_fill_cap_info()
3610 ath9k_hw_get_num_ant_config(ah, 0); in ath9k_hw_fill_cap_info()
3613 ath9k_hw_get_num_ant_config(ah, 1); in ath9k_hw_fill_cap_info()
3619 ath9k_hw_getcapability(struct ath_hal *ah, in ath9k_hw_getcapability() argument
3623 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_getcapability()
3624 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_getcapability()
3657 return ((REG_READ(ah, AR_PHY_CCK_DETECT) & in ath9k_hw_getcapability()
3667 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { in ath9k_hw_getcapability()
3694 *result = ah->ah_powerLimit; in ath9k_hw_getcapability()
3697 *result = ah->ah_maxPowerLevel; in ath9k_hw_getcapability()
3700 *result = ah->ah_tpScale; in ath9k_hw_getcapability()
3711 ath9k_hw_setcapability(struct ath_hal *ah, in ath9k_hw_setcapability() argument
3716 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_setcapability()
3729 v = REG_READ(ah, AR_PHY_CCK_DETECT); in ath9k_hw_setcapability()
3734 REG_WRITE(ah, AR_PHY_CCK_DETECT, v); in ath9k_hw_setcapability()
3756 ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, in ath9k_hw_gpio_cfg_output_mux() argument
3771 if (AR_SREV_9280_20_OR_LATER(ah) || in ath9k_hw_gpio_cfg_output_mux()
3773 REG_RMW(ah, addr, (type << gpio_shift), in ath9k_hw_gpio_cfg_output_mux()
3776 tmp = REG_READ(ah, addr); in ath9k_hw_gpio_cfg_output_mux()
3780 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
3785 ath9k_hw_cfg_gpio_input(struct ath_hal *ah, uint32_t gpio) in ath9k_hw_cfg_gpio_input() argument
3789 ASSERT(gpio < ah->ah_caps.num_gpio_pins); in ath9k_hw_cfg_gpio_input()
3793 REG_RMW(ah, in ath9k_hw_cfg_gpio_input()
3800 ath9k_hw_gpio_get(struct ath_hal *ah, uint32_t gpio) in ath9k_hw_gpio_get() argument
3802 if (gpio >= ah->ah_caps.num_gpio_pins) in ath9k_hw_gpio_get()
3805 if (AR_SREV_9280_10_OR_LATER(ah)) { in ath9k_hw_gpio_get()
3806 return ((MS(REG_READ(ah, AR_GPIO_IN_OUT), in ath9k_hw_gpio_get()
3809 return ((MS(REG_READ(ah, in ath9k_hw_gpio_get()
3816 ath9k_hw_cfg_output(struct ath_hal *ah, uint32_t gpio, in ath9k_hw_cfg_output() argument
3821 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); in ath9k_hw_cfg_output()
3825 REG_RMW(ah, in ath9k_hw_cfg_output()
3832 ath9k_hw_set_gpio(struct ath_hal *ah, uint32_t gpio, uint32_t val) in ath9k_hw_set_gpio() argument
3834 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), in ath9k_hw_set_gpio()
3840 ath9k_enable_rfkill(struct ath_hal *ah) in ath9k_enable_rfkill() argument
3842 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_enable_rfkill()
3845 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, in ath9k_enable_rfkill()
3848 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); in ath9k_enable_rfkill()
3849 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); in ath9k_enable_rfkill()
3854 ath9k_hw_select_antconfig(struct ath_hal *ah, uint32_t cfg) in ath9k_hw_select_antconfig() argument
3856 struct ath9k_channel *chan = ah->ah_curchan; in ath9k_hw_select_antconfig()
3857 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; in ath9k_hw_select_antconfig()
3865 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan, in ath9k_hw_select_antconfig()
3867 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); in ath9k_hw_select_antconfig()
3876 ath9k_hw_getdefantenna(struct ath_hal *ah) in ath9k_hw_getdefantenna() argument
3878 return (REG_READ(ah, AR_DEF_ANTENNA) & 0x7); in ath9k_hw_getdefantenna()
3882 ath9k_hw_setantenna(struct ath_hal *ah, uint32_t antenna) in ath9k_hw_setantenna() argument
3884 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
3889 ath9k_hw_setantennaswitch(struct ath_hal *ah, in ath9k_hw_setantennaswitch() argument
3896 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_setantennaswitch()
3899 if (AR_SREV_9280(ah)) { in ath9k_hw_setantennaswitch()
3913 if (ah->ah_caps.tx_chainmask > in ath9k_hw_setantennaswitch()
3938 ath9k_hw_getrxfilter(struct ath_hal *ah) in ath9k_hw_getrxfilter() argument
3940 uint32_t bits = REG_READ(ah, AR_RX_FILTER); in ath9k_hw_getrxfilter()
3941 uint32_t phybits = REG_READ(ah, AR_PHY_ERR); in ath9k_hw_getrxfilter()
3952 ath9k_hw_setrxfilter(struct ath_hal *ah, uint32_t bits) in ath9k_hw_setrxfilter() argument
3956 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR); in ath9k_hw_setrxfilter()
3963 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
3966 REG_WRITE(ah, AR_RXCFG, in ath9k_hw_setrxfilter()
3967 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
3969 REG_WRITE(ah, AR_RXCFG, in ath9k_hw_setrxfilter()
3970 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
3974 ath9k_hw_phy_disable(struct ath_hal *ah) in ath9k_hw_phy_disable() argument
3976 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)); in ath9k_hw_phy_disable()
3980 ath9k_hw_disable(struct ath_hal *ah) in ath9k_hw_disable() argument
3982 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_disable()
3985 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)); in ath9k_hw_disable()
3989 ath9k_hw_set_txpowerlimit(struct ath_hal *ah, uint32_t limit) in ath9k_hw_set_txpowerlimit() argument
3991 struct ath9k_channel *chan = ah->ah_curchan; in ath9k_hw_set_txpowerlimit()
3994 ah->ah_powerLimit = (uint16_t)min(limit, (uint32_t)MAX_RATE_POWER); in ath9k_hw_set_txpowerlimit()
3996 if (ath9k_hw_set_txpower(ah, chan, in ath9k_hw_set_txpowerlimit()
3997 ath9k_regd_get_ctl(ah, chan), in ath9k_hw_set_txpowerlimit()
3998 ath9k_regd_get_antenna_allowed(ah, chan), in ath9k_hw_set_txpowerlimit()
4001 (uint32_t)ah->ah_powerLimit)) != 0) in ath9k_hw_set_txpowerlimit()
4008 ath9k_hw_getmac(struct ath_hal *ah, uint8_t *mac) in ath9k_hw_getmac() argument
4010 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_getmac()
4016 ath9k_hw_setmac(struct ath_hal *ah, const uint8_t *mac) in ath9k_hw_setmac() argument
4018 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_setmac()
4026 ath9k_hw_setopmode(struct ath_hal *ah) in ath9k_hw_setopmode() argument
4028 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); in ath9k_hw_setopmode()
4032 ath9k_hw_setmcastfilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) in ath9k_hw_setmcastfilter() argument
4034 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
4035 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
4039 ath9k_hw_getbssidmask(struct ath_hal *ah, uint8_t *mask) in ath9k_hw_getbssidmask() argument
4041 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_getbssidmask()
4047 ath9k_hw_setbssidmask(struct ath_hal *ah, const uint8_t *mask) in ath9k_hw_setbssidmask() argument
4049 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_setbssidmask()
4053 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask)); in ath9k_hw_setbssidmask()
4054 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4)); in ath9k_hw_setbssidmask()
4060 ath9k_hw_write_associd(struct ath_hal *ah, in ath9k_hw_write_associd() argument
4063 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_write_associd()
4068 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid)); in ath9k_hw_write_associd()
4069 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) | in ath9k_hw_write_associd()
4074 ath9k_hw_gettsf64(struct ath_hal *ah) in ath9k_hw_gettsf64() argument
4078 tsf = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
4079 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf64()
4085 ath9k_hw_reset_tsf(struct ath_hal *ah) in ath9k_hw_reset_tsf() argument
4090 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { in ath9k_hw_reset_tsf()
4101 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
4105 ath9k_hw_set_tsfadjust(struct ath_hal *ah, uint32_t setting) in ath9k_hw_set_tsfadjust() argument
4107 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_set_tsfadjust()
4118 ath9k_hw_setslottime(struct ath_hal *ah, uint32_t us) in ath9k_hw_setslottime() argument
4120 struct ath_hal_5416 *ahp = AH5416(ah); in ath9k_hw_setslottime()
4122 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { in ath9k_hw_setslottime()
4129 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); in ath9k_hw_setslottime()
4136 ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) in ath9k_hw_set11nmac2040() argument
4141 !ah->ah_config.cwm_ignore_extcca) in ath9k_hw_set11nmac2040()
4146 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()