40 ath9k_hw_nf_in_range(struct ath_hal *ah, signed short nf)  in ath9k_hw_nf_in_range()  argument
106 ath9k_hw_do_getnf(struct ath_hal *ah,  in ath9k_hw_do_getnf()  argument
111 	if (AR_SREV_9280_10_OR_LATER(ah))  in ath9k_hw_do_getnf()
112 		nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);  in ath9k_hw_do_getnf()
114 		nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);  in ath9k_hw_do_getnf()
122 	if (AR_SREV_9280_10_OR_LATER(ah))  in ath9k_hw_do_getnf()
123 		nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),  in ath9k_hw_do_getnf()
126 		nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),  in ath9k_hw_do_getnf()
135 	if (!AR_SREV_9280(ah)) {  in ath9k_hw_do_getnf()
136 		nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),  in ath9k_hw_do_getnf()
145 	if (AR_SREV_9280_10_OR_LATER(ah))  in ath9k_hw_do_getnf()
146 		nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),  in ath9k_hw_do_getnf()
149 		nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),  in ath9k_hw_do_getnf()
158 	if (AR_SREV_9280_10_OR_LATER(ah))  in ath9k_hw_do_getnf()
159 		nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),  in ath9k_hw_do_getnf()
162 		nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),  in ath9k_hw_do_getnf()
171 	if (!AR_SREV_9280(ah)) {  in ath9k_hw_do_getnf()
172 		nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),  in ath9k_hw_do_getnf()
183 getNoiseFloorThresh(struct ath_hal *ah,  in getNoiseFloorThresh()  argument
192 		*nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5);  in getNoiseFloorThresh()
199 		*nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2);  in getNoiseFloorThresh()
212 ath9k_hw_setup_calibration(struct ath_hal *ah,  in ath9k_hw_setup_calibration()  argument
215 	REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),  in ath9k_hw_setup_calibration()
221 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);  in ath9k_hw_setup_calibration()
227 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);  in ath9k_hw_setup_calibration()
232 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);  in ath9k_hw_setup_calibration()
237 		REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);  in ath9k_hw_setup_calibration()
244 	REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),  in ath9k_hw_setup_calibration()
249 ath9k_hw_reset_calibration(struct ath_hal *ah,  in ath9k_hw_reset_calibration()  argument
252 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_reset_calibration()
255 	ath9k_hw_setup_calibration(ah, currCal);  in ath9k_hw_reset_calibration()
270 ath9k_hw_per_calibration(struct ath_hal *ah,  in ath9k_hw_per_calibration()  argument
276 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_per_calibration()
281 		if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &  in ath9k_hw_per_calibration()
284 			currCal->calData->calCollect(ah);  in ath9k_hw_per_calibration()
295 				currCal->calData->calPostProc(ah, numChains);  in ath9k_hw_per_calibration()
300 				ath9k_hw_setup_calibration(ah, currCal);  in ath9k_hw_per_calibration()
304 		ath9k_hw_reset_calibration(ah, currCal);  in ath9k_hw_per_calibration()
309 ath9k_hw_iscal_supported(struct ath_hal *ah,  in ath9k_hw_iscal_supported()  argument
313 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_iscal_supported()
333 ath9k_hw_iqcal_collect(struct ath_hal *ah)  in ath9k_hw_iqcal_collect()  argument
335 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_iqcal_collect()
340 		    REG_READ(ah, AR_PHY_CAL_MEAS_0(i));  in ath9k_hw_iqcal_collect()
342 		    REG_READ(ah, AR_PHY_CAL_MEAS_1(i));  in ath9k_hw_iqcal_collect()
344 		    (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_2(i));  in ath9k_hw_iqcal_collect()
354 ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)  in ath9k_hw_adc_gaincal_collect()  argument
356 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_adc_gaincal_collect()
361 		    REG_READ(ah, AR_PHY_CAL_MEAS_0(i));  in ath9k_hw_adc_gaincal_collect()
363 		    REG_READ(ah, AR_PHY_CAL_MEAS_1(i));  in ath9k_hw_adc_gaincal_collect()
365 		    REG_READ(ah, AR_PHY_CAL_MEAS_2(i));  in ath9k_hw_adc_gaincal_collect()
367 		    REG_READ(ah, AR_PHY_CAL_MEAS_3(i));  in ath9k_hw_adc_gaincal_collect()
380 ath9k_hw_adc_dccal_collect(struct ath_hal *ah)  in ath9k_hw_adc_dccal_collect()  argument
382 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_adc_dccal_collect()
387 		    (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_0(i));  in ath9k_hw_adc_dccal_collect()
389 		    (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_1(i));  in ath9k_hw_adc_dccal_collect()
391 		    (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_2(i));  in ath9k_hw_adc_dccal_collect()
393 		    (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_3(i));  in ath9k_hw_adc_dccal_collect()
406 ath9k_hw_iqcalibrate(struct ath_hal *ah, uint8_t numChains)  in ath9k_hw_iqcalibrate()  argument
408 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_iqcalibrate()
469 			REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),  in ath9k_hw_iqcalibrate()
472 			REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),  in ath9k_hw_iqcalibrate()
482 	REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),  in ath9k_hw_iqcalibrate()
487 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, uint8_t numChains)  in ath9k_hw_adc_gaincal_calibrate()  argument
489 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_adc_gaincal_calibrate()
531 			val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));  in ath9k_hw_adc_gaincal_calibrate()
534 			REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);  in ath9k_hw_adc_gaincal_calibrate()
541 	REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),  in ath9k_hw_adc_gaincal_calibrate()
542 	    REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |  in ath9k_hw_adc_gaincal_calibrate()
547 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, uint8_t numChains)  in ath9k_hw_adc_dccal_calibrate()  argument
549 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_adc_dccal_calibrate()
591 		val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));  in ath9k_hw_adc_dccal_calibrate()
594 		REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);  in ath9k_hw_adc_dccal_calibrate()
600 	REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),  in ath9k_hw_adc_dccal_calibrate()
601 	    REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |  in ath9k_hw_adc_dccal_calibrate()
606 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,  in ath9k_hw_reset_calvalid()  argument
609 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_reset_calvalid()
611 	    ath9k_regd_check_channel(ah, chan);  in ath9k_hw_reset_calvalid()
616 	if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))  in ath9k_hw_reset_calvalid()
638 	if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))  in ath9k_hw_reset_calvalid()
652 ath9k_hw_start_nfcal(struct ath_hal *ah)  in ath9k_hw_start_nfcal()  argument
654 	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,  in ath9k_hw_start_nfcal()
656 	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,  in ath9k_hw_start_nfcal()
658 	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);  in ath9k_hw_start_nfcal()
663 ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)  in ath9k_hw_loadnf()  argument
678 	if (AR_SREV_9280(ah))  in ath9k_hw_loadnf()
686 	h = ah->nfCalHist;  in ath9k_hw_loadnf()
691 			val = REG_READ(ah, ar5416_cca_regs[i]);  in ath9k_hw_loadnf()
694 			REG_WRITE(ah, ar5416_cca_regs[i], val);  in ath9k_hw_loadnf()
698 	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,  in ath9k_hw_loadnf()
700 	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,  in ath9k_hw_loadnf()
702 	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);  in ath9k_hw_loadnf()
705 		if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &  in ath9k_hw_loadnf()
713 			val = REG_READ(ah, ar5416_cca_regs[i]);  in ath9k_hw_loadnf()
716 			REG_WRITE(ah, ar5416_cca_regs[i], val);  in ath9k_hw_loadnf()
722 ath9k_hw_getnf(struct ath_hal *ah, struct ath9k_channel *chan)  in ath9k_hw_getnf()  argument
729 	if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {  in ath9k_hw_getnf()
737 		ath9k_hw_do_getnf(ah, nfarray);  in ath9k_hw_getnf()
739 		if (getNoiseFloorThresh(ah, chan, &nfThresh) &&  in ath9k_hw_getnf()
752 	h = ah->nfCalHist;  in ath9k_hw_getnf()
762 ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)  in ath9k_init_nfcal_hist_buffer()  argument
767 	if (AR_SREV_9280(ah))  in ath9k_init_nfcal_hist_buffer()
769 	else if (AR_SREV_9285(ah))  in ath9k_init_nfcal_hist_buffer()
775 		ah->nfCalHist[i].currIndex = 0;  in ath9k_init_nfcal_hist_buffer()
776 		ah->nfCalHist[i].privNF = noise_floor;  in ath9k_init_nfcal_hist_buffer()
777 		ah->nfCalHist[i].invalidNFcount =  in ath9k_init_nfcal_hist_buffer()
780 			ah->nfCalHist[i].nfCalBuffer[j] = noise_floor;  in ath9k_init_nfcal_hist_buffer()
786 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)  in ath9k_hw_getchan_noise()  argument
791 	ichan = ath9k_regd_check_channel(ah, chan);  in ath9k_hw_getchan_noise()
799 		enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);  in ath9k_hw_getchan_noise()
804 	if (!ath9k_hw_nf_in_range(ah, nf))  in ath9k_hw_getchan_noise()
811 ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,  in ath9k_hw_calibrate()  argument
815 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_calibrate()
817 	struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);  in ath9k_hw_calibrate()
831 		ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,  in ath9k_hw_calibrate()
838 				ath9k_hw_reset_calibration(ah, currCal);  in ath9k_hw_calibrate()
844 		(void) ath9k_hw_getnf(ah, ichan);  in ath9k_hw_calibrate()
845 		ath9k_hw_loadnf(ah, ah->ah_curchan);  in ath9k_hw_calibrate()
846 		ath9k_hw_start_nfcal(ah);  in ath9k_hw_calibrate()
859 ath9k_hw_9285_pa_cal(struct ath_hal *ah)  in ath9k_hw_9285_pa_cal()  argument
875 	if (AR_SREV_9285_11(ah)) {  in ath9k_hw_9285_pa_cal()
876 		REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));  in ath9k_hw_9285_pa_cal()
881 		regList[i][1] = REG_READ(ah, regList[i][0]);  in ath9k_hw_9285_pa_cal()
883 	regVal = REG_READ(ah, 0x7834);  in ath9k_hw_9285_pa_cal()
885 	REG_WRITE(ah, 0x7834, regVal);  in ath9k_hw_9285_pa_cal()
886 	regVal = REG_READ(ah, 0x9808);  in ath9k_hw_9285_pa_cal()
888 	REG_WRITE(ah, 0x9808, regVal);  in ath9k_hw_9285_pa_cal()
890 	REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);  in ath9k_hw_9285_pa_cal()
891 	REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);  in ath9k_hw_9285_pa_cal()
892 	REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);  in ath9k_hw_9285_pa_cal()
893 	REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);  in ath9k_hw_9285_pa_cal()
894 	REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);  in ath9k_hw_9285_pa_cal()
895 	REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);  in ath9k_hw_9285_pa_cal()
896 	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);  in ath9k_hw_9285_pa_cal()
897 	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);  in ath9k_hw_9285_pa_cal()
898 	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);  in ath9k_hw_9285_pa_cal()
899 	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);  in ath9k_hw_9285_pa_cal()
900 	REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);  in ath9k_hw_9285_pa_cal()
901 	REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);  in ath9k_hw_9285_pa_cal()
902 	ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);  in ath9k_hw_9285_pa_cal()
903 	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);  in ath9k_hw_9285_pa_cal()
905 	REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);  in ath9k_hw_9285_pa_cal()
907 	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);  in ath9k_hw_9285_pa_cal()
908 	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);  in ath9k_hw_9285_pa_cal()
911 		regVal = REG_READ(ah, 0x7834);  in ath9k_hw_9285_pa_cal()
913 		REG_WRITE(ah, 0x7834, regVal);  in ath9k_hw_9285_pa_cal()
915 		regVal = REG_READ(ah, 0x7834);  in ath9k_hw_9285_pa_cal()
917 		reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);  in ath9k_hw_9285_pa_cal()
919 		REG_WRITE(ah, 0x7834, regVal);  in ath9k_hw_9285_pa_cal()
922 	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);  in ath9k_hw_9285_pa_cal()
924 	reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);  in ath9k_hw_9285_pa_cal()
925 	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);  in ath9k_hw_9285_pa_cal()
926 	offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);  in ath9k_hw_9285_pa_cal()
927 	offs_0   = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);  in ath9k_hw_9285_pa_cal()
934 	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);  in ath9k_hw_9285_pa_cal()
935 	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);  in ath9k_hw_9285_pa_cal()
937 	regVal = REG_READ(ah, 0x7834);  in ath9k_hw_9285_pa_cal()
939 	REG_WRITE(ah, 0x7834, regVal);  in ath9k_hw_9285_pa_cal()
940 	regVal = REG_READ(ah, 0x9808);  in ath9k_hw_9285_pa_cal()
942 	REG_WRITE(ah, 0x9808, regVal);  in ath9k_hw_9285_pa_cal()
945 		REG_WRITE(ah, regList[i][0], regList[i][1]);  in ath9k_hw_9285_pa_cal()
947 	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);  in ath9k_hw_9285_pa_cal()
949 	if (AR_SREV_9285_11(ah))  in ath9k_hw_9285_pa_cal()
950 		REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);  in ath9k_hw_9285_pa_cal()
955 ath9k_hw_init_cal(struct ath_hal *ah,  in ath9k_hw_init_cal()  argument
958 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_init_cal()
959 	struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);  in ath9k_hw_init_cal()
961 	REG_WRITE(ah, AR_PHY_AGC_CONTROL,  in ath9k_hw_init_cal()
962 	    REG_READ(ah, AR_PHY_AGC_CONTROL) |  in ath9k_hw_init_cal()
965 	if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {  in ath9k_hw_init_cal()
972 	if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))  in ath9k_hw_init_cal()
973 			ath9k_hw_9285_pa_cal(ah);  in ath9k_hw_init_cal()
975 	REG_WRITE(ah, AR_PHY_AGC_CONTROL,  in ath9k_hw_init_cal()
976 	    REG_READ(ah, AR_PHY_AGC_CONTROL) |  in ath9k_hw_init_cal()
981 	if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {  in ath9k_hw_init_cal()
982 		if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {  in ath9k_hw_init_cal()
991 		if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {  in ath9k_hw_init_cal()
1000 		if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {  in ath9k_hw_init_cal()
1013 			ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);  in ath9k_hw_init_cal()