28 ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, struct ath9k_channel *chan)  in ath9k_hw_get_ani_channel_idx()  argument
30 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_get_ani_channel_idx()
50 ath9k_hw_ani_control(struct ath_hal *ah, enum ath9k_ani_cmd cmd, int param)  in ath9k_hw_ani_control()  argument
52 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_control()
69 		REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,  in ath9k_hw_ani_control()
72 		REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,  in ath9k_hw_ani_control()
75 		REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,  in ath9k_hw_ani_control()
78 		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,  in ath9k_hw_ani_control()
98 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,  in ath9k_hw_ani_control()
101 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,  in ath9k_hw_ani_control()
104 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,  in ath9k_hw_ani_control()
107 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,  in ath9k_hw_ani_control()
110 		REG_RMW_FIELD(ah, AR_PHY_SFCORR,  in ath9k_hw_ani_control()
113 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,  in ath9k_hw_ani_control()
117 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,  in ath9k_hw_ani_control()
120 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,  in ath9k_hw_ani_control()
123 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,  in ath9k_hw_ani_control()
126 		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,  in ath9k_hw_ani_control()
131 			REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,  in ath9k_hw_ani_control()
134 			REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,  in ath9k_hw_ani_control()
150 		REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,  in ath9k_hw_ani_control()
175 		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,  in ath9k_hw_ani_control()
197 		REG_RMW_FIELD(ah, AR_PHY_TIMING5,  in ath9k_hw_ani_control()
235 ath9k_hw_update_mibstats(struct ath_hal *ah, struct ath9k_mib_stats *stats)  in ath9k_hw_update_mibstats()  argument
237 	stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);  in ath9k_hw_update_mibstats()
238 	stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);  in ath9k_hw_update_mibstats()
239 	stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);  in ath9k_hw_update_mibstats()
240 	stats->rts_good += REG_READ(ah, AR_RTS_OK);  in ath9k_hw_update_mibstats()
241 	stats->beacons += REG_READ(ah, AR_BEACON_CNT);  in ath9k_hw_update_mibstats()
245 ath9k_ani_restart(struct ath_hal *ah)  in ath9k_ani_restart()  argument
247 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_ani_restart()
250 	if (!DO_ANI(ah))  in ath9k_ani_restart()
279 		REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);  in ath9k_ani_restart()
280 		REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);  in ath9k_ani_restart()
281 		REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);  in ath9k_ani_restart()
282 		REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);  in ath9k_ani_restart()
284 		ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);  in ath9k_ani_restart()
291 ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)  in ath9k_hw_ani_ofdm_err_trigger()  argument
293 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_ofdm_err_trigger()
294 	struct ath9k_channel *chan = ah->ah_curchan;  in ath9k_hw_ani_ofdm_err_trigger()
299 	if (!DO_ANI(ah))  in ath9k_hw_ani_ofdm_err_trigger()
305 		if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,  in ath9k_hw_ani_ofdm_err_trigger()
312 		if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,  in ath9k_hw_ani_ofdm_err_trigger()
318 	if (ah->ah_opmode == ATH9K_M_HOSTAP) {  in ath9k_hw_ani_ofdm_err_trigger()
320 			(void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,  in ath9k_hw_ani_ofdm_err_trigger()
328 			if (ath9k_hw_ani_control(ah,  in ath9k_hw_ani_ofdm_err_trigger()
331 				(void) ath9k_hw_ani_control(ah,  in ath9k_hw_ani_ofdm_err_trigger()
337 			(void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,  in ath9k_hw_ani_ofdm_err_trigger()
343 			(void) ath9k_hw_ani_control(ah,  in ath9k_hw_ani_ofdm_err_trigger()
347 			(void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,  in ath9k_hw_ani_ofdm_err_trigger()
351 		mode = ath9k_hw_chan2wmode(ah, chan);  in ath9k_hw_ani_ofdm_err_trigger()
354 				(void) ath9k_hw_ani_control(ah,  in ath9k_hw_ani_ofdm_err_trigger()
358 				(void) ath9k_hw_ani_control(ah,  in ath9k_hw_ani_ofdm_err_trigger()
366 ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)  in ath9k_hw_ani_cck_err_trigger()  argument
368 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_cck_err_trigger()
369 	struct ath9k_channel *chan = ah->ah_curchan;  in ath9k_hw_ani_cck_err_trigger()
374 	if (!DO_ANI(ah))  in ath9k_hw_ani_cck_err_trigger()
379 		if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,  in ath9k_hw_ani_cck_err_trigger()
384 	if (ah->ah_opmode == ATH9K_M_HOSTAP) {  in ath9k_hw_ani_cck_err_trigger()
386 			(void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,  in ath9k_hw_ani_cck_err_trigger()
394 			(void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,  in ath9k_hw_ani_cck_err_trigger()
397 		mode = ath9k_hw_chan2wmode(ah, chan);  in ath9k_hw_ani_cck_err_trigger()
400 				(void) ath9k_hw_ani_control(ah,  in ath9k_hw_ani_cck_err_trigger()
407 ath9k_hw_ani_lower_immunity(struct ath_hal *ah)  in ath9k_hw_ani_lower_immunity()  argument
409 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_lower_immunity()
415 	if (ah->ah_opmode == ATH9K_M_HOSTAP) {  in ath9k_hw_ani_lower_immunity()
417 			if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,  in ath9k_hw_ani_lower_immunity()
428 				if (ath9k_hw_ani_control(ah,  in ath9k_hw_ani_lower_immunity()
434 				if (ath9k_hw_ani_control(ah,  in ath9k_hw_ani_lower_immunity()
441 				if (ath9k_hw_ani_control(ah,  in ath9k_hw_ani_lower_immunity()
450 		if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,  in ath9k_hw_ani_lower_immunity()
456 		(void) ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,  in ath9k_hw_ani_lower_immunity()
463 ath9k_hw_ani_get_listen_time(struct ath_hal *ah)  in ath9k_hw_ani_get_listen_time()  argument
465 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_get_listen_time()
470 	txFrameCount = REG_READ(ah, AR_TFCNT);  in ath9k_hw_ani_get_listen_time()
471 	rxFrameCount = REG_READ(ah, AR_RFCNT);  in ath9k_hw_ani_get_listen_time()
472 	cycleCount = REG_READ(ah, AR_CCCNT);  in ath9k_hw_ani_get_listen_time()
493 ath9k_ani_reset(struct ath_hal *ah)  in ath9k_ani_reset()  argument
495 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_ani_reset()
497 	struct ath9k_channel *chan = ah->ah_curchan;  in ath9k_ani_reset()
503 	if (!DO_ANI(ah))  in ath9k_ani_reset()
506 	index = ath9k_hw_get_ani_channel_idx(ah, chan);  in ath9k_ani_reset()
510 	if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA &&  in ath9k_ani_reset()
511 	    ah->ah_opmode != ATH9K_M_IBSS) {  in ath9k_ani_reset()
513 		    "Reset ANI state opmode %u\n", ah->ah_opmode));  in ath9k_ani_reset()
516 		(void) ath9k_hw_ani_control(ah,  in ath9k_ani_reset()
518 		(void) ath9k_hw_ani_control(ah,  in ath9k_ani_reset()
520 		(void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);  in ath9k_ani_reset()
522 		    (ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,  in ath9k_ani_reset()
524 		(void) ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,  in ath9k_ani_reset()
527 		ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |  in ath9k_ani_reset()
530 		if (ah->ah_opmode == ATH9K_M_HOSTAP) {  in ath9k_ani_reset()
532 			    ah->ah_config.ofdm_trig_high;  in ath9k_ani_reset()
534 			    ah->ah_config.ofdm_trig_low;  in ath9k_ani_reset()
536 			    ah->ah_config.cck_trig_high;  in ath9k_ani_reset()
538 			    ah->ah_config.cck_trig_low;  in ath9k_ani_reset()
540 		ath9k_ani_restart(ah);  in ath9k_ani_reset()
545 		(void) ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,  in ath9k_ani_reset()
548 		(void) ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,  in ath9k_ani_reset()
552 		    (ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,  in ath9k_ani_reset()
555 		(void) ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,  in ath9k_ani_reset()
558 		(void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,  in ath9k_ani_reset()
561 		ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &  in ath9k_ani_reset()
563 		ath9k_ani_restart(ah);  in ath9k_ani_reset()
564 		REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);  in ath9k_ani_reset()
565 		REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);  in ath9k_ani_reset()
568 		ath9k_ani_restart(ah);  in ath9k_ani_reset()
569 		ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |  in ath9k_ani_reset()
576 ath9k_hw_ani_monitor(struct ath_hal *ah, const struct ath9k_node_stats *stats,  in ath9k_hw_ani_monitor()  argument
579 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_monitor()
586 	listenTime = ath9k_hw_ani_get_listen_time(ah);  in ath9k_hw_ani_monitor()
589 		ath9k_ani_restart(ah);  in ath9k_hw_ani_monitor()
599 		ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);  in ath9k_hw_ani_monitor()
601 		phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);  in ath9k_hw_ani_monitor()
602 		phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);  in ath9k_hw_ani_monitor()
612 				REG_WRITE(ah, AR_PHY_ERR_1,  in ath9k_hw_ani_monitor()
614 				REG_WRITE(ah, AR_PHY_ERR_MASK_1,  in ath9k_hw_ani_monitor()
623 				REG_WRITE(ah, AR_PHY_ERR_2,  in ath9k_hw_ani_monitor()
625 				REG_WRITE(ah, AR_PHY_ERR_MASK_2,  in ath9k_hw_ani_monitor()
642 	if (!DO_ANI(ah))  in ath9k_hw_ani_monitor()
650 			ath9k_hw_ani_lower_immunity(ah);  in ath9k_hw_ani_monitor()
651 		ath9k_ani_restart(ah);  in ath9k_hw_ani_monitor()
655 			ath9k_hw_ani_ofdm_err_trigger(ah);  in ath9k_hw_ani_monitor()
656 			ath9k_ani_restart(ah);  in ath9k_hw_ani_monitor()
659 			ath9k_hw_ani_cck_err_trigger(ah);  in ath9k_hw_ani_monitor()
660 			ath9k_ani_restart(ah);  in ath9k_hw_ani_monitor()
666 ath9k_hw_phycounters(struct ath_hal *ah)  in ath9k_hw_phycounters()  argument
668 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_phycounters()
674 ath9k_enable_mib_counters(struct ath_hal *ah)  in ath9k_enable_mib_counters()  argument
676 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_enable_mib_counters()
681 	ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);  in ath9k_enable_mib_counters()
683 	REG_WRITE(ah, AR_FILT_OFDM, 0);  in ath9k_enable_mib_counters()
684 	REG_WRITE(ah, AR_FILT_CCK, 0);  in ath9k_enable_mib_counters()
685 	REG_WRITE(ah, AR_MIBC,  in ath9k_enable_mib_counters()
687 	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);  in ath9k_enable_mib_counters()
688 	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);  in ath9k_enable_mib_counters()
692 ath9k_hw_disable_mib_counters(struct ath_hal *ah)  in ath9k_hw_disable_mib_counters()  argument
694 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_disable_mib_counters()
700 	REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);  in ath9k_hw_disable_mib_counters()
702 	ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);  in ath9k_hw_disable_mib_counters()
704 	REG_WRITE(ah, AR_FILT_OFDM, 0);  in ath9k_hw_disable_mib_counters()
705 	REG_WRITE(ah, AR_FILT_CCK, 0);  in ath9k_hw_disable_mib_counters()
709 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, uint32_t *rxc_pcnt,  in ath9k_hw_GetMibCycleCountsPct()  argument
715 	uint32_t rc = REG_READ(ah, AR_RCCNT);  in ath9k_hw_GetMibCycleCountsPct()
716 	uint32_t rf = REG_READ(ah, AR_RFCNT);  in ath9k_hw_GetMibCycleCountsPct()
717 	uint32_t tf = REG_READ(ah, AR_TFCNT);  in ath9k_hw_GetMibCycleCountsPct()
718 	uint32_t cc = REG_READ(ah, AR_CCCNT);  in ath9k_hw_GetMibCycleCountsPct()
754 ath9k_hw_procmibevent(struct ath_hal *ah,  in ath9k_hw_procmibevent()  argument
757 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_procmibevent()
761 	REG_WRITE(ah, AR_FILT_OFDM, 0);  in ath9k_hw_procmibevent()
762 	REG_WRITE(ah, AR_FILT_CCK, 0);  in ath9k_hw_procmibevent()
763 	if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))  in ath9k_hw_procmibevent()
764 		REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);  in ath9k_hw_procmibevent()
767 	ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);  in ath9k_hw_procmibevent()
770 	if (!DO_ANI(ah))  in ath9k_hw_procmibevent()
774 	phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);  in ath9k_hw_procmibevent()
775 	phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);  in ath9k_hw_procmibevent()
799 			ath9k_hw_ani_ofdm_err_trigger(ah);  in ath9k_hw_procmibevent()
801 			ath9k_hw_ani_cck_err_trigger(ah);  in ath9k_hw_procmibevent()
803 		ath9k_ani_restart(ah);  in ath9k_hw_procmibevent()
808 ath9k_hw_ani_setup(struct ath_hal *ah)  in ath9k_hw_ani_setup()  argument
810 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_setup()
827 ath9k_hw_ani_attach(struct ath_hal *ah)  in ath9k_hw_ani_attach()  argument
829 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_attach()
869 		REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);  in ath9k_hw_ani_attach()
870 		REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);  in ath9k_hw_ani_attach()
871 		ath9k_enable_mib_counters(ah);  in ath9k_hw_ani_attach()
874 	if (ah->ah_config.enable_ani)  in ath9k_hw_ani_attach()
879 ath9k_hw_ani_detach(struct ath_hal *ah)  in ath9k_hw_ani_detach()  argument
881 	struct ath_hal_5416 *ahp = AH5416(ah);  in ath9k_hw_ani_detach()
887 		ath9k_hw_disable_mib_counters(ah);  in ath9k_hw_ani_detach()
888 		REG_WRITE(ah, AR_PHY_ERR_1, 0);  in ath9k_hw_ani_detach()
889 		REG_WRITE(ah, AR_PHY_ERR_2, 0);  in ath9k_hw_ani_detach()