Lines Matching +full:vdd +full:- +full:3
21 * Standard JESD400-5A.01 DDR5 Serial Presence Detect (SPD) Contents. Release
27 * o Base Configuration and DRAM parameters (0x00-0x7f)
28 * o Common Module Parameters (0xc0-0xef)
29 * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something
31 * o A CRC check for the first 510 bytes (0x1fe-0x1ff)
32 * o Manufacturing Information (0x200-0x27f)
33 * o Optional end-user programmable regions (0x280-0x3ff)
54 #define SPD_DDR5_NBYTES_TOTAL_1024 3
56 #define SPD_DDR5_NBYTES_BETA(r) bitx8(r, 3, 0)
64 #define SPD_DDR5_SPD_REV_ADD(r) bitx8(r, 3, 0)
83 #define SPD_DDR5_MOD_TYPE_TYPE(r) bitx8(r, 3, 0)
86 #define SPD_DDR5_MOD_TYPE_TYPE_SODIMM 3
105 #define SPD_DDR5_DENPKG_DPP_4H3DS 3
111 #define SPD_DDR5_DENPKG_DPD_12Gb 3
141 #define SPD_DDR5_WIDTH_X32 3
153 #define SPD_DDR5_BANKS_NBG_BITS_MAX 3
182 #define SPD_DDR5_FLT_WIDE_TS(r) bitx8(r, 3, 3)
190 * S8.1.17 SDRAM Nominal Voltage, VDD
201 #define SPD_DDR5_DRAM_VOLT_OPER(r) bitx8(r, 3, 2)
252 * S8.1.34 SDRAM Normal Refresh Recovery Time, 3DS Different Logical Rank
254 * S8.1.35 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank
256 * S8.1.36 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank
293 #define SPD_DDR5_RFM0_RAAMMT_NORM_MIN 3
314 #define SPD_DDR5_RFM1_BRC_SUP(r)bitx8(r, 3, 3)
407 * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which
408 * includes both the common area and type-specific areas.
415 * JEDS316-5.
423 * S11.3 Common: Module Device Information. This contains a series of four
432 #define SPD_DDR5_COM_INFO_TYPE(r) bitx8(r, 3, 0)
447 #define SPD_DDR5_COM_INFO_TYPE_PMIC5020 3
470 #define SPD_DDR5_COM_INFO_TYPE_TS5210 3
485 #define SPD_DDR5_COM_THICK_FRONT(r) bitx8(r, 3, 0)
504 #define SPD_DDR5_COM_ATTR_OTR_IT 3
523 #define SPD_DDR5_COM_ORG_NRANK(r) bitx8(r, 5, 3)
528 * terms of sub-channels.
533 #define SPD_DDR5_COM_BUS_WIDTH_EXT(r) bitx8(r, 4, 3)
541 #define SPD_DDR5_COM_BUS_WIDTH_PRI_64b 3
554 * bytes. See the discussion of S11.3. Revision 1.0 only defined the CLK
564 * S13.2 UDIMM v1.1: CKD-RW00 CKD Configuration
573 * S13.3 UDIMM v1.1: CKD-RW02 QCK Driver Characteristics
578 #define SPD_DDR5_UDIMM_CKD_DRV_CHAQCK1_DRIVE(r) bitx8(r, 3, 2)
583 #define SPD_DDR5_UDIMM_CKD_DRV_WEAK 3
586 * S13.4 UDIMM v1.1: CKD-RW03 QCK Output Differential Slew Rate
595 * Annex A.3: Module Specific Bytes for Registered (RDIMM) and Load Reduced
610 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD04 3
622 * S14.3 RDIMM: RCD-RW08 Clock Driver Enable
626 #define SPD_DDR5_RDIMM_CLKEN_QDCK(r) bitx8(r, 3, 3)
632 * S14.4 RDIMM: RCD-RW09 Output Address and Control Enable
638 #define SPD_DDR5_RDIMM_RW09_BCS(r) bitx8(r, 3, 3)
644 * S14.5 RDIMM: RCD-RW0A QCK Driver Characteristics
645 * S14.7 RDIMM: RCD-RW0C QxCA and QxCS_n Driver Characteristics
646 * S14.8 LRDIMM: RCD-RW0D Data Buffer Interface Driver Characteristics
655 #define SPD_DDR5_RDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2)
666 #define SPD_DDR5_LRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3)
670 * S14.9 RDIMM: RCD-RW0E QCK, QCA, and QCS Output Slew Rate
671 * S14.10 LRDIMM: RCD-RW0F BCK, BCOM, and BCS Output Slew Rate
681 #define SPD_DDR5_RDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2)
685 #define SPD_DDR5_LRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2)
689 * S14.11 DB-RW86 DQS RTT Park Termination
696 #define SPD_DDR5_LDRIMM_PARK_80R 3
722 * S15.3 MRDIMM v1.1: MRCD-RW08 Clock Driver Enable
726 #define SPD_DDR5_MRDIMM_CDEN_QDCK(r) bitx8(r, 3, 3)
732 * S15.3 MRDIMM v1.1: MRCD-RW09 Output Address and Control Enable
739 #define SPD_DDR5_MRDIMM_CDEN_BCS(r) bitx8(r, 3, 3)
745 * S15.4 MRDIMM v1.1: MRCD-RW0A QCK Driver Characteristics
746 * S15.6 MRDIMM v1.1: MRCD-RW0C QxCA and QxCS_n Driver Characteristics
747 * S15.7 MRDIMM v1.1: MRCD-RW0D Data Buffer Interface Driver Characteristics
755 #define SPD_DDR5_MRDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2)
770 #define SPD_DDR5_MRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3)
774 * S15.8 MRDIMM v1.1: MRCD-RW0E QCK, QCA, and QCS Output Slew Rate
775 * S15.9 MRDIMM v1.1: MRCD-RW0F BCK, BCOM, and BCS Output Slew Rate
785 #define SPD_DDR5_MRDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2)
789 #define SPD_DDR5_MRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2)
793 * S15.10 MRDIMM v1.1: MDB-PG[C]RWE0 Duty Cycle Adjuster Configuration
799 * S15.11 MRDIMM v1.1: MDB-PG[70]RWE1 DRAM Interface Receiver Type
832 * S7.4 CRC. DDR5 modules have a single CRC calculation that covers bytes 0-509.
857 * S20.3 module Manufacturing Date. Encoded as two BCD bytes for the year and
880 * Bytes 0x22b-0x27f are left for manufacturer specific data.