Lines Matching +full:fast +full:- +full:clk
21 * Standard JESD400-5A.01 DDR5 Serial Presence Detect (SPD) Contents. Release
27 * o Base Configuration and DRAM parameters (0x00-0x7f)
28 * o Common Module Parameters (0xc0-0xef)
29 * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something
31 * o A CRC check for the first 510 bytes (0x1fe-0x1ff)
32 * o Manufacturing Information (0x200-0x27f)
33 * o Optional end-user programmable regions (0x280-0x3ff)
407 * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which
408 * includes both the common area and type-specific areas.
415 * JEDS316-5.
528 * terms of sub-channels.
554 * bytes. See the discussion of S11.3. Revision 1.0 only defined the CLK
564 * S13.2 UDIMM v1.1: CKD-RW00 CKD Configuration
573 * S13.3 UDIMM v1.1: CKD-RW02 QCK Driver Characteristics
586 * S13.4 UDIMM v1.1: CKD-RW03 QCK Output Differential Slew Rate
622 * S14.3 RDIMM: RCD-RW08 Clock Driver Enable
632 * S14.4 RDIMM: RCD-RW09 Output Address and Control Enable
644 * S14.5 RDIMM: RCD-RW0A QCK Driver Characteristics
645 * S14.7 RDIMM: RCD-RW0C QxCA and QxCS_n Driver Characteristics
646 * S14.8 LRDIMM: RCD-RW0D Data Buffer Interface Driver Characteristics
670 * S14.9 RDIMM: RCD-RW0E QCK, QCA, and QCS Output Slew Rate
671 * S14.10 LRDIMM: RCD-RW0F BCK, BCOM, and BCS Output Slew Rate
674 * and fast; however, they all have different voltage ranges.
689 * S14.11 DB-RW86 DQS RTT Park Termination
722 * S15.3 MRDIMM v1.1: MRCD-RW08 Clock Driver Enable
732 * S15.3 MRDIMM v1.1: MRCD-RW09 Output Address and Control Enable
745 * S15.4 MRDIMM v1.1: MRCD-RW0A QCK Driver Characteristics
746 * S15.6 MRDIMM v1.1: MRCD-RW0C QxCA and QxCS_n Driver Characteristics
747 * S15.7 MRDIMM v1.1: MRCD-RW0D Data Buffer Interface Driver Characteristics
774 * S15.8 MRDIMM v1.1: MRCD-RW0E QCK, QCA, and QCS Output Slew Rate
775 * S15.9 MRDIMM v1.1: MRCD-RW0F BCK, BCOM, and BCS Output Slew Rate
793 * S15.10 MRDIMM v1.1: MDB-PG[C]RWE0 Duty Cycle Adjuster Configuration
799 * S15.11 MRDIMM v1.1: MDB-PG[70]RWE1 DRAM Interface Receiver Type
832 * S7.4 CRC. DDR5 modules have a single CRC calculation that covers bytes 0-509.
880 * Bytes 0x22b-0x27f are left for manufacturer specific data.