Lines Matching +full:vdd +full:- +full:3
21 * Standard 21-C Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules
26 * o Base Configuration and DRAM parameters (bytes 0x00-0x7f)
27 * o Standard Module Parameters (bytes 0x80-0xbf) these vary on whether
29 * o Hybrid Module Parameters (bytes 0xc0-0xff)
30 * o Hybrid Module Extended Parameters (bytes 0x100-0x13f).
31 * o Manufacturing Information (bytes 0x140-0x17f)
32 * o End User Programmable data (0x180-0x1ff).
52 #define SPD_DDR4_NBYTES_USED(r) bitx8(r, 3, 0)
56 #define SPD_DDR4_NBYTES_USED_384 3
60 * S8.1.2: SPD Revision. The SPD revision is split into two 4-bit fields. There
62 * like a major and minor version. The upper 4-bit encoding level tells us
71 #define SPD_DDR4_SPD_REV_ADD(r) bitx8(r, 3, 0)
83 * module it is, which tell us what the module-specific section contents are.
92 #define SPD_DDR4_MOD_TYPE_HYBRID_NVDIMM_H 3
93 #define SPD_DDR4_MOD_TYPE_TYPE(r) bitx8(r, 3, 0)
97 #define SPD_DDR4_MOD_TYPE_TYPE_SODIMM 3
114 #define SPD_DDR4_DENSITY_NBA_BITS_MAX 3
115 #define SPD_DDR4_DENSITY_DENSITY(r) bitx8(r, 3, 0)
119 #define SPD_DDR4_DENSITY_DENSITY_2Gb 3
131 #define SPD_DDR4_ADDR_NROWS(r) bitx8(r, 5, 3)
145 * 3:2 must be 0 in the primary. As such, we try to reuse definitions. In the
156 #define SPD_DDR4_SEC_PKG_RATIO(r) bitx8(r, 3, 2)
173 #define SPD_DDR4_OPT_FEAT_MAC(r) bitx8(r, 3, 0)
177 #define SPD_DDR4_OPT_FEAT_MAC_500K 3
201 * S8.1.12 Module Nominal Voltage, VDD.
214 #define SPD_DDR4_MOD_ORG_NPKG_RANK(r) bitx8(r, 5, 3)
220 #define SPD_DDR4_MOD_ORG_WIDTH_32b 3
227 #define SPD_DDR4_MOD_BUS_WIDTH_EXT(r) bitx8(r, 4, 3)
234 #define SPD_DDR4_MOD_BUS_WIDTH_PRI_64b 3
243 * S8.1.16 Extended Module Type. This contains a 4-bit extended module type;
261 #define SPD_DDR4_TIMEBASE_MTB(r) bitx8(r, 3, 2)
322 #define SPD_DDR4_RAS_RC_UPPER_RAS(r) bitx8(r, 3, 0)
346 * This is another 12-bit MTB-unit field.
349 #define SPD_DDR4_TFAW_UPPER_FAW(r) bitx8(r, 3, 0)
376 #define SPD_DDR4_TWR_MIN_UPPER_TWR(r) bitx8(r, 3, 0)
389 #define SPD_DDR4_TWRT_UPPER_TWRS(r) bitx8(r, 3, 0)
428 * Bytes 0x4e-0x74 are reserved. Bytes 75-7D are fine offsets that are laid out
445 * S8.5.1 Module Manufacturer ID Code. This is a two byte JEP-108 style MFG ID.
482 * Bytes 0x161-0x17d are left for Manufacturer specific data while bytes
483 * 0x17e-0x17f are reserved.
487 * The next region of bytes in the range 0x80-0xbf. We have specific definitions
493 * S9.2.1 RDIMM: Raw Card Extension, Module Nominal Height. Bits 7-5 here have a
495 * value of the normal reference card used in byte 0x82 is set to 0b11 (3).
509 #define SPD_DDR4_RDIMM_THICK_FRONT(r) bitx8(r, 3, 0)
514 * for bits 4-0. We do not define each meaning of these bit combinations in this
515 * header, that is left for tables in the library. When bits 6:5 are 0b11 (3)
521 #define SPD_DDR4_RDIMM_REV_USE_HEIGHT 3
531 #define SPD_DDR4_RDIMM_ATTR_NROWS(r) bitx8(r, 3, 2)
558 * register maps ranks 1 and 3 between the register and the actual modules.
573 #define SPD_DDR4_RDIMM_ODS0_ODT(r) bitx8(r, 3, 2)
578 #define SPD_DDR4_RDIMM_ODS0_VERY_STRONG 3
581 #define SPD_DDR4_RDIMM_ODS1_Y1(r) bitx8(r, 3, 2)
631 #define SPD_DDR4_LRDIMM_ATTR_NROWS(r) bitx8(r, 3, 2)
671 * two use the same two-bit version as RDIMMs.
673 #define SPD_DDR4_RDIMM_ODS1_Y1(r) bitx8(r, 3, 2)
685 * S9.3.15 LRDIMM: DRAM VrefDQ for Package Rank 3
687 * These are all encoded with a value from MR6 in JESD79-4 apparently.
722 #define SPD_DDR4_LRDIMM_MDQ_RTT_40R 3
734 #define SPD_DDR4_LRDIMM_DRAM_DS_2400(r) bitx8(r, 3, 2)
747 #define SPD_DDR4_LRDIMM_ODT_WR(r) bitx8(r, 5, 3)
751 #define SPD_DDR4_LRDIMM_ODT_WR_HIZ 3
757 #define SPD_DDR4_LRDIMM_ODT_NOM_40R 3
771 #define SPD_DDR4_LRDIMM_PARK_R23(r) bitx8(r, 5, 3)
776 #define SPD_DDR4_LRDIMM_PARK_40R 3
787 #define SPD_DDR4_LRDIMM_VREFDQ_RNG_R3(r) bitx8(r, 3, 3)