Lines Matching +full:vdd +full:- +full:3
21 * based on JEDEC Standard 21-C Section Annex K: Serial Presence Detect
26 * o Base Configuration and DRAM parameters (bytes 0x00-0x3b)
27 * o Standard Module Parameters (bytes 0x40-0x74) these vary on whether
29 * o Manufacturing Information (bytes 0x75-0xaf)
30 * o End User Programmable data (0xb0-0xff).
50 #define SPD_DDR3_NBYTES_USED(r) bitx8(r, 3, 0)
54 #define SPD_DDR3_NBYTES_USED_256 3
62 #define SPD_DDR3_SPD_REV_ADD(r) bitx8(r, 3, 0)
74 * is, which tells us what the module-specific section contents are. These bits,
78 #define SPD_DDR3_MOD_TYPE_TYPE(r) bitx8(r, 3, 0)
82 #define SPD_DDR3_MOD_TYPE_TYPE_SODIMM 3
99 #define SPD_DDR3_DENSITY_NBA_BITS_BASE 3
101 #define SPD_DDR3_DENSITY_DENSITY(r) bitx8(r, 3, 0)
105 #define SPD_DDR3_DENSITY_DENSITY_2Gb 3
117 #define SPD_DDR3_ADDR_NROWS(r) bitx8(r, 5, 3)
125 * Module Nominal Voltage, VDD
136 #define SPD_DDR3_MOD_ORG_NRANKS(r) bitx(r, 5, 3)
140 #define SPD_DDR3_MOD_ORG_NRANKS_4 3
150 #define SPD_DDR3_BUS_WIDTH_EXT(r) bitx8(r, 4, 3)
154 #define SPD_DDR3_BUS_WIDTH_PRI_BASE 3
164 #define SPD_DDR3_FTB_DIVISOR(r) bitx8(r, 3, 0)
233 #define SPD_DDR3_RAS_RC_UPPER_RAS(r) bitx8(r, 3, 0)
260 #define SPD_DDR3_TFAB_NIB_UPPER_TFAW(r) bitx8(r, 3, 0)
276 #define SPD_DDR3_REFRESH_ODTS_SUP(r) bitx8(r, 3, 3)
315 #define SPD_DDR3_MAC_MAC(r) bitx8(r, 3, 0)
319 #define SPD_DDR3_MAC_MAC_500K 3
335 * UDIMM: Raw Card Extension, Module Nominal Height. Bits 7-5 here have a raw
337 * value of the normal reference card used in byte 0x3e is set to 0b11 (3).
351 #define SPD_DDR3_UDIMM_THICK_FRONT(r) bitx8(r, 3, 0)
356 * bit for bits 4-0. We do not define each meaning of these bit combinations in
358 * (3) then we must add in the reference card value in byte 0x80 to bits 6:5.
363 #define SPD_DDR3_UDIMM_REV_USE_HEIGHT 3
393 #define SPD_DDR3_RDIMM_ATTR_NROWS(r) bitx8(r, 3, 2)
430 * RDIMM: SSTE32882: RC3 / RC2 - Drive Strength, Command/Address. The lower
438 #define SPD_DDR3_RDIMM_DS_VERY_STRONG 3 /* LRDIMMs only */
442 * RDIMM: SSTE32882: RC5 / RC4 - Drive Strength, Control and Clock
447 #define SPD_DDR3_RDIMM_CCDS_CTLB(r) bitx8(r, 3, 2)
451 * Bytes 72-76 have definitions but must be written as zero and are all
457 * Annex K.3: Module Specific Bytes for Clocked Memory Module Types
495 #define SPD_DDR3_LRDIMM_ATTR_NROWS(r) bitx8(r, 3, 2)
509 * LRDIMM: F0RC3 / F0RC2 - Timing Control & Drive Strength, Address/Command &
525 * LRDIMM: F0RC5 / F0RC4 - Drive Strength, QxODT & QxCKE and Clock
530 #define SPD_DDR3_LRDIMM_CKDS_CKE(r) bitx8(r, 3, 2)
534 * LRDIMM: F1RC11 / F1RC8 - Extended Delay for Clocks, QxCS_n and QxODT & QxCKE
541 #define SPD_DDR3_LRDIMM_EXTD_CS(r) bitx8(r, 3, 2)
545 * LRDIMM: F1RC13 / F1RC12 - Additive Delay for QxCS and QxCA
557 * LRDIMM: F1RC15 / F1RC14 - Additive Delay for QxODT and QxCKE
562 #define SPD_DDR3_LRDIMM_ADDD_ODT_ODT_EN(r) bitx8(r, 3, 3)
573 * LRDIMM: F3RC9 / F3RC8 - DRAM Interface MDQ Termination and Drive Strength
575 * LRDIMM: F3RC9 / F3RC8 - DRAM Interface MDQ Termination and Drive Strength
577 * LRDIMM: F3RC9 / F3RC8 - DRAM Interface MDQ Termination and Drive Strength
587 #define SPD_DDR3_LRDIMM_MDQ_DS_27R 3
593 #define SPD_DDR3_LRDIMM_MDQ_ODT_40R 3
599 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 0/1 R/W QxODT Control <= 1066
600 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 2/3 R/W QxODT Control <= 1066
601 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 4/5 R/W QxODT Control <= 1066
602 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 6/7 R/W QxODT Control <= 1066
603 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 0/1 R/W QxODT Control >= 1333 <= 1600
604 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 2/3 R/W QxODT Control >= 1333 <= 1600
605 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 4/5 R/W QxODT Control >= 1333 <= 1600
606 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 6/7 R/W QxODT Control >= 1333 <= 1600
607 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 0/1 R/W QxODT Control >= 1866 <= 2133
608 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 2/3 R/W QxODT Control >= 1866 <= 2133
609 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 4/5 R/W QxODT Control >= 1866 <= 2133
610 * LRDIMM: F[3,4]RC11 / F[3,4]RC10 - Rank 6/7 R/W QxODT Control >= 1866 <= 2133
630 #define SPD_DDR3_LRDIMM_ODT_R1_ODT1_RD(r) bitx8(r, 3, 3)
651 #define SPD_DDR3_LRDIMM_RTT_NOM_40R 3
681 * S2.3 Unique Module ID Bytes. This is a two byte JEP-108 style ID.
722 * DRAM Manufacturer ID Code. This is a two byte JEP-108 style ID.