Lines Matching +full:slew +full:- +full:rate
23 * o JEDEC JEP-106 vendor data
25 * (JESD402-1)
47 * JEDEC operating temperature ranges. These are defined in JESD402-1B
127 * parse the overall SPD data structure. These represent a top-level failure and
162 * categories. Fatal errors set a value in the spd_error_t below. Non-fatal
166 * The keys are all dot delineated to create a few different top-level
169 * "meta" -- Which includes information about the SPD, encoding, and things like
172 * "dram" -- Parameters that are specific to the SDRAM dies present. What one
177 * "channel" -- Parameters that are tied to an implementation of a channel. DDR4
179 * sub-channels.
181 * "ddr4", "ddr5" -- These include information which is specific to the general
185 * "lp" -- These are parameters that are currently specific to one of the
186 * low-power DDR specifications such as LPDDR5.
188 * "module" -- Parameters that are specific to the broader module and PCB
191 * "ddr4.rdimm", "ddr4.lrdimm", "ddr5.rdimm", etc. -- These are parameter that
196 * "ddr3.mb", "ddr4.rcd", etc. -- These are generation-specific parameters that
200 * "mfg" -- Manufacturing related information.
202 * "errors" -- The key for the errors nvlist_t. See the spd_error_kind_t
219 #define SPD_KEY_NBYTES_TOTAL "meta.total-bytes" /* uint32_t */
220 #define SPD_KEY_NBYTES_USED "meta.used-bytes" /* uint32_t */
221 #define SPD_KEY_REV_ENC "meta.revision-encoding" /* uint32_t */
222 #define SPD_KEY_REV_ADD "meta.revision-additions" /* uint32_t */
223 #define SPD_KEY_BETA "meta.beta-version" /* uint32_t */
224 #define SPD_KEY_MOD_REV_ENC "meta.module-revision-encoding" /* uint32_t */
225 #define SPD_KEY_MOD_REV_ADD "meta.module-revision-additions" /* uint32_t */
254 #define SPD_KEY_DRAM_TYPE "meta.dram-type" /* uint32_t (enum) */
278 #define SPD_KEY_MOD_TYPE "meta.module-type" /* uint32_t (enum) */
283 #define SPD_KEY_MOD_HYBRID_TYPE "meta.hybrid-type" /* uint32_t */
290 #define SPD_KEY_MOD_NVDIMM_TYPE "meta.nvdimm-type" /* uint32_t */
294 * by the CRCs also vary. We end up with per-spec keys. All data types for these
302 #define SPD_KEY_CRC_DDR3 "meta.crc-ddr3" /* uint32_t */
303 #define SPD_KEY_CRC_DDR3_LEN "meta.crc-ddr3-len" /* uint32_t */
304 #define SPD_KEY_CRC_DDR4_BASE "meta.crc-ddr4-base" /* uint32_t */
305 #define SPD_KEY_CRC_DDR4_BLK1 "meta.crc-ddr4-block1" /* uint32_t */
306 #define SPD_KEY_CRC_DDR5 "meta.crc-ddr5" /* uint32_t */
316 #define SPD_KEY_HASH_SEQ "meta.hash-sequence-algorithm" /* uint32_t */
327 #define SPD_KEY_NROW_BITS "dram.num-row-bits" /* uint32_t */
328 #define SPD_KEY_NCOL_BITS "dram.num-column-bits" /* uint32_t */
329 #define SPD_KEY_NBANK_BITS "dram.num-bank-bits" /* uint32_t */
330 #define SPD_KEY_NBGRP_BITS "dram.num-bank-group-bits" /* uint32_t */
331 #define SPD_KEY_SEC_NROW_BITS "dram.sec-num-row-bits" /* uint32_t */
332 #define SPD_KEY_SEC_NCOL_BITS "dram.sec-num-column-bits" /* uint32_t */
333 #define SPD_KEY_SEC_NBANK_BITS "dram.sec-num-bank-bits" /* uint32_t */
334 #define SPD_KEY_SEC_NBGRP_BITS "dram.sec-num-bank-group-bits" /* uint32_t */
339 #define SPD_KEY_DIE_SIZE "dram.die-bit-size" /* uint64_t */
340 #define SPD_KEY_SEC_DIE_SIZE "dram.sec-die-bit-size" /* uint64_t */
351 #define SPD_KEY_PKG_NOT_MONO "meta.non-monolithic-package" /* key only */
352 #define SPD_KEY_PKG_NDIE "dram.package-die-count" /* uint32_t */
353 #define SPD_KEY_SEC_PKG_NDIE "dram.sec-package-die-count" /* uint32_t */
359 #define SPD_KEY_PKG_SL "dram.package-sig-loading" /* uint32_t */
360 #define SPD_KEY_SEC_PKG_SL "dram.sec-package-sig-loading" /* uint32_t */
363 * Post-package Repair. PPR is supported in DDR4, DDR5. LPDDR4, and LPDDR5. PPR
379 #define SPD_KEY_PPR "dram.ppr-flags" /* uint32_t (enum) */
380 #define SPD_KEY_PPR_GRAN "dram.ppr-gran" /* uint32_t (enum) */
388 #define SPD_KEY_NOM_VDD "dram.nominal-vdd" /* uint32_t[] */
389 #define SPD_KEY_NOM_VDDQ "dram.nominal-vddq" /* uint32_t[] */
390 #define SPD_KEY_NOM_VPP "dram.nominal-vpp" /* uint32_t[] */
395 * This describes the number of ranks that exist on a per-channel basis. In
397 * module. In DDR5 and LPDDR there are multiple channels or sub-channels. The
401 #define SPD_KEY_RANK_ASYM "dram.asymmetrical-ranks" /* key */
402 #define SPD_KEY_NRANKS "channel.num-ranks" /* uint32_t */
409 * entire 72-bit (64-bit data, 8-bit ECC) bus. In DDR5 and LPDDR5 this is made
410 * up of a pair of sub-channels. In LPDDR3/4 the device exposed a number of
411 * channels, that are effecitvely similar in spirit to the DDR5 sub-channel. The
414 * channels in the SPD spec and for DDR5 and LPDDR5 these are sub-channels. The
418 * is stored in the num-channels calculation and otherwise set to 1 for all
426 #define SPD_KEY_SEC_DRAM_WIDTH "dram.sec-width" /* uint32_t */
427 #define SPD_KEY_DRAM_NCHAN "dram.num-channels" /* uint32_t */
428 #define SPD_KEY_NSUBCHAN "module.num-subchan" /* uint32_t */
429 #define SPD_KEY_DATA_WIDTH "channel.data-width" /* uint32_t */
430 #define SPD_KEY_ECC_WIDTH "channel.ecc-width" /* uint32_t */
436 #define SPD_KEY_LP_BYTE_MODE "lp.byte-mode" /* key */
439 * LPDDR3-5 have a signal loading matrix that indicates the amount of load that
443 #define SPD_KEY_LP_LOAD_DSM "lp.load-data-strobe-mask"
444 #define SPD_KEY_LP_LOAD_CAC "lp.load-command-address-clock"
445 #define SPD_KEY_LP_LOAD_CS "lp.load-chip-select"
448 * DDR3, DDR4, and LPDDR3-5/x specify specific timebases in the SPD data. DDR5
452 #define SPD_KEY_MTB "dram.median-time-base" /* uint32_t */
453 #define SPD_KEY_FTB "dram.fine-time-base" /* uint32_t */
459 #define SPD_KEY_CAS "dram.cas-latencies" /* uint32_t [] */
523 #define SPD_KEY_TRFC1_DLR "dram.3ds-t~RFC1_dlr~"
524 #define SPD_KEY_TRFC2_DLR "dram.3ds-t~RFC2_dlr~"
525 #define SPD_KEY_TRFCSB_DLR "dram.3ds-t~RFCsb_dlr~"
528 * The following times are only used by LPDDR3-5, but like other variable timing
529 * entries, we still use the "dram" prefix. These are per-bank and all bank row
556 #define SPD_KEY_LP_RWLAT "lp.read-write-latency" /* uint32_t */
559 * Partial Automatic self-refresh (PASR) was introduced in DDR3 and continued in
560 * DDR5. Automatic self-refresh (ASR) was only in DDR3. We treat it as a part of
562 * extended temperature fresh rate.
572 #define SPD_KEY_DDR3_XTRR "ddr3.xt-refresh-rate" /* uint32_t */
588 #define SPD_KEY_DDR5_WIDE_TS "ddr5.wide-temp-sense" /* key */
594 #define SPD_KEY_DDR5_FLT "ddr5.fault-handling" /* uint32_t */
597 * DDR5 allows for non-standard core timing options. This is indicated by a
600 #define SPD_KEY_DDR5_NONSTD_TIME "ddr5.non-standard-timing" /* key */
618 #define SPD_KEY_DDR5_RFM_RAAIMT_FGR_PRI "ddr5.rfm.raaimt-fgr"
620 #define SPD_KEY_DDR5_RFM_RAAMMT_FGR_PRI "ddr5.rfm.raammt-fgr"
621 #define SPD_KEY_DDR5_RFM_BRC_CFG_PRI "ddr5.rfm.brc-config"
628 #define SPD_KEY_DDR5_RFM_BRC_SUP_PRI "ddr5.rfm.brc-level"
629 #define SPD_KEY_DDR5_RFM_RAA_DEC_PRI "ddr5.rfm.raa-dec"
630 #define SPD_KEY_DDR5_RFM_FLAGS_SEC "ddr5.rfm.sec-flags"
631 #define SPD_KEY_DDR5_RFM_RAAIMT_SEC "ddr5.rfm.sec-raaimt"
632 #define SPD_KEY_DDR5_RFM_RAAIMT_FGR_SEC "ddr5.rfm.sec-raaimt-fgr"
633 #define SPD_KEY_DDR5_RFM_RAAMMT_SEC "ddr5.rfm.sec-raammt"
634 #define SPD_KEY_DDR5_RFM_RAAMMT_FGR_SEC "ddr5.rfm.sec-raammt-fgr"
635 #define SPD_KEY_DDR5_RFM_BRC_CFG_SEC "ddr5.rfm.sec-brc-config"
636 #define SPD_KEY_DDR5_RFM_BRC_SUP_SEC "ddr5.rfm.sec-brc-level"
637 #define SPD_KEY_DDR5_RFM_RAA_DEC_SEC "ddr5.rfm.sec-raa-dec"
639 #define SPD_KEY_DDR5_ARFMA_FLAGS_PRI "ddr5.arfm-a.flags"
640 #define SPD_KEY_DDR5_ARFMA_RAAIMT_PRI "ddr5.arfm-a.raaimt"
641 #define SPD_KEY_DDR5_ARFMA_RAAIMT_FGR_PRI "ddr5.arfm-a.raaimt-fgr"
642 #define SPD_KEY_DDR5_ARFMA_RAAMMT_PRI "ddr5.arfm-a.raammt"
643 #define SPD_KEY_DDR5_ARFMA_RAAMMT_FGR_PRI "ddr5.arfm-a.raammt-fgr"
644 #define SPD_KEY_DDR5_ARFMA_BRC_CFG_PRI "ddr5.arfm-a.brc-config"
645 #define SPD_KEY_DDR5_ARFMA_BRC_SUP_PRI "ddr5.arfm-a.brc-level"
646 #define SPD_KEY_DDR5_ARFMA_RAA_DEC_PRI "ddr5.arfm-a.raa-dec"
647 #define SPD_KEY_DDR5_ARFMA_FLAGS_SEC "ddr5.arfm-a.sec-flags"
648 #define SPD_KEY_DDR5_ARFMA_RAAIMT_SEC "ddr5.arfm-a.sec-raaimt"
649 #define SPD_KEY_DDR5_ARFMA_RAAIMT_FGR_SEC "ddr5.arfm-a.sec-raaimt-fgr"
650 #define SPD_KEY_DDR5_ARFMA_RAAMMT_SEC "ddr5.arfm-a.sec-raammt"
651 #define SPD_KEY_DDR5_ARFMA_RAAMMT_FGR_SEC "ddr5.arfm-a.sec-raammt-fgr"
652 #define SPD_KEY_DDR5_ARFMA_BRC_CFG_SEC "ddr5.arfm-a.sec-brc-config"
653 #define SPD_KEY_DDR5_ARFMA_BRC_SUP_SEC "ddr5.arfm-a.sec-brc-level"
654 #define SPD_KEY_DDR5_ARFMA_RAA_DEC_SEC "ddr5.arfm-a.sec-raa-dec"
656 #define SPD_KEY_DDR5_ARFMB_FLAGS_PRI "ddr5.arfm-b.flags"
657 #define SPD_KEY_DDR5_ARFMB_RAAIMT_PRI "ddr5.arfm-b.raaimt"
658 #define SPD_KEY_DDR5_ARFMB_RAAIMT_FGR_PRI "ddr5.arfm-b.raaimt-fgr"
659 #define SPD_KEY_DDR5_ARFMB_RAAMMT_PRI "ddr5.arfm-b.raammt"
660 #define SPD_KEY_DDR5_ARFMB_RAAMMT_FGR_PRI "ddr5.arfm-b.raammt-fgr"
661 #define SPD_KEY_DDR5_ARFMB_BRC_CFG_PRI "ddr5.arfm-b.brc-config"
662 #define SPD_KEY_DDR5_ARFMB_BRC_SUP_PRI "ddr5.arfm-b.brc-level"
663 #define SPD_KEY_DDR5_ARFMB_RAA_DEC_PRI "ddr5.arfm-b.raa-dec"
664 #define SPD_KEY_DDR5_ARFMB_FLAGS_SEC "ddr5.arfm-b.sec-flags"
665 #define SPD_KEY_DDR5_ARFMB_RAAIMT_SEC "ddr5.arfm-b.sec-raaimt"
666 #define SPD_KEY_DDR5_ARFMB_RAAIMT_FGR_SEC "ddr5.arfm-b.sec-raaimt-fgr"
667 #define SPD_KEY_DDR5_ARFMB_RAAMMT_SEC "ddr5.arfm-b.sec-raammt"
668 #define SPD_KEY_DDR5_ARFMB_RAAMMT_FGR_SEC "ddr5.arfm-b.sec-raammt-fgr"
669 #define SPD_KEY_DDR5_ARFMB_BRC_CFG_SEC "ddr5.arfm-b.sec-brc-config"
670 #define SPD_KEY_DDR5_ARFMB_BRC_SUP_SEC "ddr5.arfm-b.sec-brc-level"
671 #define SPD_KEY_DDR5_ARFMB_RAA_DEC_SEC "ddr5.arfm-b.sec-raa-dec"
673 #define SPD_KEY_DDR5_ARFMC_FLAGS_PRI "ddr5.arfm-c.flags"
674 #define SPD_KEY_DDR5_ARFMC_RAAIMT_PRI "ddr5.arfm-c.raaimt"
675 #define SPD_KEY_DDR5_ARFMC_RAAIMT_FGR_PRI "ddr5.arfm-c.raaimt-fgr"
676 #define SPD_KEY_DDR5_ARFMC_RAAMMT_PRI "ddr5.arfm-c.raammt"
677 #define SPD_KEY_DDR5_ARFMC_RAAMMT_FGR_PRI "ddr5.arfm-c.raammt-fgr"
678 #define SPD_KEY_DDR5_ARFMC_BRC_CFG_PRI "ddr5.arfm-c.brc-config"
679 #define SPD_KEY_DDR5_ARFMC_BRC_SUP_PRI "ddr5.arfm-c.brc-level"
680 #define SPD_KEY_DDR5_ARFMC_RAA_DEC_PRI "ddr5.arfm-c.raa-dec"
681 #define SPD_KEY_DDR5_ARFMC_FLAGS_SEC "ddr5.arfm-c.sec-flags"
682 #define SPD_KEY_DDR5_ARFMC_RAAIMT_SEC "ddr5.arfm-c.sec-raaimt"
683 #define SPD_KEY_DDR5_ARFMC_RAAIMT_FGR_SEC "ddr5.arfm-c.sec-raaimt-fgr"
684 #define SPD_KEY_DDR5_ARFMC_RAAMMT_SEC "ddr5.arfm-c.sec-raammt"
685 #define SPD_KEY_DDR5_ARFMC_RAAMMT_FGR_SEC "ddr5.arfm-c.sec-raammt-fgr"
686 #define SPD_KEY_DDR5_ARFMC_BRC_CFG_SEC "ddr5.arfm-c.sec-brc-config"
687 #define SPD_KEY_DDR5_ARFMC_BRC_SUP_SEC "ddr5.arfm-c.sec-brc-level"
688 #define SPD_KEY_DDR5_ARFMC_RAA_DEC_SEC "ddr5.arfm-c.sec-raa-dec"
690 * Module-type specific keys and values. These are often the intersection of
693 * that are drive strengths and slew rates. These kinds of items fall into two
713 * are all on the RCD. There is also a key for whether or not slew-control is
721 #define SPD_KEY_DDR3_RCD_DS_CAA "ddr3.rcd.ca-a-drive-strength"
722 #define SPD_KEY_DDR3_RCD_DS_CAB "ddr3.rcd.ca-b-drive-strength"
723 #define SPD_KEY_DDR3_RCD_DS_CTLA "ddr3.rcd.cs-a-drive-strength"
724 #define SPD_KEY_DDR3_RCD_DS_CTLB "ddr3.rcd.cs-b-drive-strength"
725 #define SPD_KEY_DDR3_RCD_DS_Y0 "ddr3.rcd.y0-drive-strength"
726 #define SPD_KEY_DDR3_RCD_DS_Y1 "ddr3.rcd.y1-drive-strength"
728 #define SPD_KEY_DDR3_MB_DS_Y0 "ddr3.mb.y0-drive-strength"
729 #define SPD_KEY_DDR3_MB_DS_Y1 "ddr3.mb.y1-drive-strength"
730 #define SPD_KEY_DDR3_MB_DS_CKE "ddr3.mb.cke-drive-strength"
731 #define SPD_KEY_DDR3_MB_DS_ODT "ddr3.mb.cke-drive-strength"
732 #define SPD_KEY_DDR3_MB_DS_CS "ddr3.mb.cs-drive-strength"
733 #define SPD_KEY_DDR3_MB_DS_CA "ddr3.mb.ca-drive-strength"
735 #define SPD_KEY_DDR4_RCD_SLEW "ddr4.rcd.rcd-slew-control" /* key */
736 #define SPD_KEY_DDR4_RCD_DS_CKE "ddr4.rcd.cke-drive-strength"
737 #define SPD_KEY_DDR4_RCD_DS_ODT "ddr4.rcd.odt-drive-strength"
738 #define SPD_KEY_DDR4_RCD_DS_CA "ddr4.rcd.ca-drive-strength"
739 #define SPD_KEY_DDR4_RCD_DS_CS "ddr4.rcd.cs-drive-strength"
740 #define SPD_KEY_DDR4_RCD_DS_Y0 "ddr4.rcd.y0-drive-strength"
741 #define SPD_KEY_DDR4_RCD_DS_Y1 "ddr4.rcd.y1-drive-strength"
742 #define SPD_KEY_DDR4_RCD_DS_BCOM "ddr4.rcd.bcom-drive-strength"
743 #define SPD_KEY_DDR4_RCD_DS_BCK "ddr4.rcd.bck-drive-strength"
763 #define SPD_KEY_DDR3_MB_EXTD_Y "ddr4.mb.y-extended-delay"
764 #define SPD_KEY_DDR3_MB_EXTD_CS "ddr4.mb.cs-extended-delay"
765 #define SPD_KEY_DDR3_MB_EXTD_ODT "ddr4.mb.odt-extended-delay"
766 #define SPD_KEY_DDR3_MB_EXTD_CKE "ddr4.mb.cke-extended-delay"
767 #define SPD_KEY_DDR3_MB_ADDD_Y "ddr4.mb.y-additive-delay"
768 #define SPD_KEY_DDR3_MB_ADDD_CS "ddr4.mb.cs-additive-delay"
769 #define SPD_KEY_DDR3_MB_ADDD_ODT "ddr4.mb.odt-additive-delay"
770 #define SPD_KEY_DDR3_MB_ADDD_CKE "ddr4.mb.cke-additive-delay"
779 #define SPD_KEY_DDR3_MB_R0_ODT0_RD "ddr3.mb.r0-qxodt0-read-assert"
780 #define SPD_KEY_DDR3_MB_R0_ODT1_RD "ddr3.mb.r0-qxodt1-read-assert"
781 #define SPD_KEY_DDR3_MB_R0_ODT0_WR "ddr3.mb.r0-qxodt0-write-assert"
782 #define SPD_KEY_DDR3_MB_R0_ODT1_WR "ddr3.mb.r0-qxodt1-write-assert"
783 #define SPD_KEY_DDR3_MB_R1_ODT0_RD "ddr3.mb.r1-qxodt0-read-assert"
784 #define SPD_KEY_DDR3_MB_R1_ODT1_RD "ddr3.mb.r1-qxodt1-read-assert"
785 #define SPD_KEY_DDR3_MB_R1_ODT0_WR "ddr3.mb.r1-qxodt0-write-assert"
786 #define SPD_KEY_DDR3_MB_R1_ODT1_WR "ddr3.mb.r1-qxodt1-write-assert"
787 #define SPD_KEY_DDR3_MB_R2_ODT0_RD "ddr3.mb.r2-qxodt0-read-assert"
788 #define SPD_KEY_DDR3_MB_R2_ODT1_RD "ddr3.mb.r2-qxodt1-read-assert"
789 #define SPD_KEY_DDR3_MB_R2_ODT0_WR "ddr3.mb.r2-qxodt0-write-assert"
790 #define SPD_KEY_DDR3_MB_R2_ODT1_WR "ddr3.mb.r2-qxodt1-write-assert"
791 #define SPD_KEY_DDR3_MB_R3_ODT0_RD "ddr3.mb.r3-qxodt0-read-assert"
792 #define SPD_KEY_DDR3_MB_R3_ODT1_RD "ddr3.mb.r3-qxodt1-read-assert"
793 #define SPD_KEY_DDR3_MB_R3_ODT0_WR "ddr3.mb.r3-qxodt0-write-assert"
794 #define SPD_KEY_DDR3_MB_R3_ODT1_WR "ddr3.mb.r3-qxodt1-write-assert"
795 #define SPD_KEY_DDR3_MB_R4_ODT0_RD "ddr3.mb.r4-qxodt0-read-assert"
796 #define SPD_KEY_DDR3_MB_R4_ODT1_RD "ddr3.mb.r4-qxodt1-read-assert"
797 #define SPD_KEY_DDR3_MB_R4_ODT0_WR "ddr3.mb.r4-qxodt0-write-assert"
798 #define SPD_KEY_DDR3_MB_R4_ODT1_WR "ddr3.mb.r4-qxodt1-write-assert"
799 #define SPD_KEY_DDR3_MB_R5_ODT0_RD "ddr3.mb.r5-qxodt0-read-assert"
800 #define SPD_KEY_DDR3_MB_R5_ODT1_RD "ddr3.mb.r5-qxodt1-read-assert"
801 #define SPD_KEY_DDR3_MB_R5_ODT0_WR "ddr3.mb.r5-qxodt0-write-assert"
802 #define SPD_KEY_DDR3_MB_R5_ODT1_WR "ddr3.mb.r5-qxodt1-write-assert"
803 #define SPD_KEY_DDR3_MB_R6_ODT0_RD "ddr3.mb.r6-qxodt0-read-assert"
804 #define SPD_KEY_DDR3_MB_R6_ODT1_RD "ddr3.mb.r6-qxodt1-read-assert"
805 #define SPD_KEY_DDR3_MB_R6_ODT0_WR "ddr3.mb.r6-qxodt0-write-assert"
806 #define SPD_KEY_DDR3_MB_R6_ODT1_WR "ddr3.mb.r6-qxodt1-write-assert"
807 #define SPD_KEY_DDR3_MB_R7_ODT0_RD "ddr3.mb.r7-qxodt0-read-assert"
808 #define SPD_KEY_DDR3_MB_R7_ODT1_RD "ddr3.mb.r7-qxodt1-read-assert"
809 #define SPD_KEY_DDR3_MB_R7_ODT0_WR "ddr3.mb.r7-qxodt0-write-assert"
810 #define SPD_KEY_DDR3_MB_R7_ODT1_WR "ddr3.mb.r7-qxodt1-write-assert"
821 #define SPD_KEY_DDR4_VREFDQ_R0 "ddr4.lrdimm.VrefDQ-rank0"
822 #define SPD_KEY_DDR4_VREFDQ_R1 "ddr4.lrdimm.VrefDQ-rank1"
823 #define SPD_KEY_DDR4_VREFDQ_R2 "ddr4.lrdimm.VrefDQ-rank2"
824 #define SPD_KEY_DDR4_VREFDQ_R3 "ddr4.lrdimm.VrefDQ-rank3"
825 #define SPD_KEY_DDR4_VREFDQ_DB "ddr4.lrdimm.VrefDQ-db"
829 * of various data rate ranges. Specifically (0, 1866], (1866, 2400], and (2400,
833 * cases where they are disabled or high-impedance.
840 #define SPD_KEY_DDR4_MDQ_RTT "ddr4.lrdimm.mdq-read-termination"
841 #define SPD_KEY_DDR4_MDQ_DS "ddr4.lrdimm.mdq-drive-strength"
842 #define SPD_KEY_DDR4_DRAM_DS "ddr4.lrdimm.dram-drive-strength"
843 #define SPD_KEY_DDR4_RTT_WR "ddr4.lrdimm.odt-read-termination-wr"
844 #define SPD_KEY_DDR4_RTT_NOM "ddr4.lrdimm.odt-read-termination-nom"
845 #define SPD_KEY_DDR4_RTT_PARK_R0 "ddr4.lrdimm.odt-r0_1-rtt-park"
846 #define SPD_KEY_DDR4_RTT_PARK_R2 "ddr4.lrdimm.odt-r2_3-rtt-park"
848 #define SPD_KEY_DDR3_MDQ_DS "ddr3.lrdimm.mdq-drive-strength"
849 #define SPD_KEY_DDR3_MDQ_ODT "ddr3.lrdimm.mdq-odt-strength"
850 #define SPD_KEY_DDR3_RTT_WRT "ddr3.lrdimm.mdq-odt-read-termination-wr"
851 #define SPD_KEY_DDR3_RTT_NOM "ddr3.lrdimm.mdq-odt-read-termination-nom"
852 #define SPD_KEY_DDR3_DRAM_DS "ddr3.lrdimm.dram-drive-strength"
859 #define SPD_KEY_DDR3_MOD_MIN_DELAY "ddr3.lrdimm.minimum-module-delay"
860 #define SPD_KEY_DDR3_MOD_MAX_DELAY "ddr3.lrdimm.maximum-module-delay"
872 #define SPD_KEY_DDR4_DB_GAIN "ddr4.lrdimm.db-gain-adjustment"
873 #define SPD_KEY_DDR4_DB_DFE "ddr4.lrdimm.decision-feedback-eq"
880 * there are slew rates, those use the spd_slew_t. Because these use different
883 #define SPD_KEY_DDR5_RCD_QACK_EN "ddr5.rcd.qack-enabled"
884 #define SPD_KEY_DDR5_RCD_QBCK_EN "ddr5.rcd.qbck-enabled"
885 #define SPD_KEY_DDR5_RCD_QCCK_EN "ddr5.rcd.qcck-enabled"
886 #define SPD_KEY_DDR5_RCD_QDCK_EN "ddr5.rcd.qdck-enabled"
887 #define SPD_KEY_DDR5_RCD_BCK_EN "ddr5.rcd.bck-enabled"
888 #define SPD_KEY_DDR5_RCD_QACA_EN "ddr5.rcd.qaca-enabled"
889 #define SPD_KEY_DDR5_RCD_QBCA_EN "ddr5.rcd.qbca-enabled"
890 #define SPD_KEY_DDR5_RCD_QxCS_EN "ddr5.rcd.qxcs-enabled"
891 #define SPD_KEY_DDR5_RCD_QxCA13_EN "ddr5.rcd.qxca13-enabled"
892 #define SPD_KEY_DDR5_RCD_QACS_EN "ddr5.rcd.qacs-enabled"
893 #define SPD_KEY_DDR5_RCD_QBCS_EN "ddr5.rcd.qbcs-enabled"
896 #define SPD_KEY_DDR5_RCD_QACK_DS "ddr5.rcd.qack-drive-strength"
897 #define SPD_KEY_DDR5_RCD_QBCK_DS "ddr5.rcd.qbck-drive-strength"
898 #define SPD_KEY_DDR5_RCD_QCCK_DS "ddr5.rcd.qcck-drive-strength"
899 #define SPD_KEY_DDR5_RCD_QDCK_DS "ddr5.rcd.qdck-drive-strength"
900 #define SPD_KEY_DDR5_RCD_QxCS_DS "ddr5.rcd.qxcs-drive-strength"
901 #define SPD_KEY_DDR5_RCD_CA_DS "ddr5.rcd.ca-drive-strength"
903 /* Slew rates use the spd_rate_t encoded as a uint32_t */
904 #define SPD_KEY_DDR5_RCD_QCK_SLEW "ddr5.rcd.qck-slew"
905 #define SPD_KEY_DDR5_RCD_QCA_SLEW "ddr5.rcd.qca-slew"
906 #define SPD_KEY_DDR5_RCD_QCS_SLEW "ddr5.rcd.qcs-slew"
913 #define SPD_KEY_DDR5_RCD_BCS_EN "ddr5.rcd.bcs-enabled" /* key */
914 #define SPD_KEY_DDR5_RCD_BCOM_DS "ddr5.rcd.bcom-drive-strength"
915 #define SPD_KEY_DDR5_RCD_BCK_DS "ddr5.rcd.bck-drive-strength"
916 #define SPD_KEY_DDR5_RCD_RTT_TERM "ddr5.rcd.dqs-rtt"
917 #define SPD_KEY_DDR5_RCD_BCOM_SLEW "ddr5.rcd.bcom-slew"
918 #define SPD_KEY_DDR5_RCD_BCK_SLEW "ddr5.rcd.bck-slew"
926 * Unbuffered clock configuration, drivers, and slew rates. The various -enabled
927 * values are keys. The drive strengths and slew rates use the spd_drive_t and
930 #define SPD_KEY_DDR5_CKD_CHAQCK0_EN "ddr5.ckd.cha-qck0_A-enabled"
931 #define SPD_KEY_DDR5_CKD_CHAQCK1_EN "ddr5.ckd.cha-qck1_A-enabled"
932 #define SPD_KEY_DDR5_CKD_CHBQCK0_EN "ddr5.ckd.chb-qck0_B-enabled"
933 #define SPD_KEY_DDR5_CKD_CHBQCK1_EN "ddr5.ckd.chb-qck1_B-enabled"
934 #define SPD_KEY_DDR5_CKD_CHAQCK0_DS "ddr5.ckd.cha-qck0_A-drive-strength"
935 #define SPD_KEY_DDR5_CKD_CHAQCK1_DS "ddr5.ckd.cha-qck1_A-drive-strength"
936 #define SPD_KEY_DDR5_CKD_CHBQCK0_DS "ddr5.ckd.chb-qck0_B-drive-strength"
937 #define SPD_KEY_DDR5_CKD_CHBQCK1_DS "ddr5.ckd.chb-qck1_B-drive-strength"
938 #define SPD_KEY_DDR5_CKD_CHAQCK_SLEW "ddr5.ckd.cha-qck_slew"
939 #define SPD_KEY_DDR5_CKD_CHBQCK_SLEW "ddr5.ckd.chb-qck_slew"
947 #define SPD_KEY_DDR5_MRCD_QACK_EN "ddr5.mrcd.qack-enabled"
948 #define SPD_KEY_DDR5_MRCD_QBCK_EN "ddr5.mrcd.qbck-enabled"
949 #define SPD_KEY_DDR5_MRCD_QCCK_EN "ddr5.mrcd.qcck-enabled"
950 #define SPD_KEY_DDR5_MRCD_QDCK_EN "ddr5.mrcd.qdck-enabled"
951 #define SPD_KEY_DDR5_MRCD_BCK_EN "ddr5.mrcd.bck-enabled"
952 #define SPD_KEY_DDR5_MRCD_QACA_EN "ddr5.mrcd.qaca-enabled"
953 #define SPD_KEY_DDR5_MRCD_QBCA_EN "ddr5.mrcd.qbca-enabled"
954 #define SPD_KEY_DDR5_MRCD_BCS_EN "ddr5.mrcd.bcs-enabled"
955 #define SPD_KEY_DDR5_MRCD_QxCS_EN "ddr5.mrcd.qxcs-enabled"
956 #define SPD_KEY_DDR5_MRCD_QxCA13_EN "ddr5.mrcd.qxca13-enabled"
957 #define SPD_KEY_DDR5_MRCD_QACS_EN "ddr5.mrcd.qacs-enabled"
958 #define SPD_KEY_DDR5_MRCD_QBCS_EN "ddr5.mrcd.qbcs-enabled"
959 #define SPD_KEY_DDR5_MRCD_DCS1_EN "ddr5.mrcd.dcs1-enabled"
962 #define SPD_KEY_DDR5_MRCD_QACK_DS "ddr5.mrcd.qack-drive-strength"
963 #define SPD_KEY_DDR5_MRCD_QBCK_DS "ddr5.mrcd.qbck-drive-strength"
964 #define SPD_KEY_DDR5_MRCD_QCCK_DS "ddr5.mrcd.qcck-drive-strength"
965 #define SPD_KEY_DDR5_MRCD_QDCK_DS "ddr5.mrcd.qdck-drive-strength"
966 #define SPD_KEY_DDR5_MRCD_QxCS_DS "ddr5.mrcd.qxcs-drive-strength"
967 #define SPD_KEY_DDR5_MRCD_CA_DS "ddr5.mrcd.ca-drive-strength"
968 #define SPD_KEY_DDR5_MRCD_BCOM_DS "ddr5.mrcd.bcom-drive-strength"
969 #define SPD_KEY_DDR5_MRCD_BCK_DS "ddr5.mrcd.bck-drive-strength"
971 /* Slew rates use the spd_rate_t encoded as a uint32_t */
972 #define SPD_KEY_DDR5_MRCD_QCK_SLEW "ddr5.mrcd.qck-slew"
973 #define SPD_KEY_DDR5_MRCD_QCA_SLEW "ddr5.mrcd.qca-slew"
974 #define SPD_KEY_DDR5_MRCD_QCS_SLEW "ddr5.mrcd.qcs-slew"
975 #define SPD_KEY_DDR5_MRCD_BCOM_SLEW "ddr5.mrcd.bcom-slew"
976 #define SPD_KEY_DDR5_MRCD_BCK_SLEW "ddr5.mrcd.bck-slew"
983 #define SPD_KEY_DDR5_MRCD_QxCS_OUT "ddr5.mrcd.qxcs-output-control"
989 #define SPD_KEY_DDR5_MRCD_DCA_CFG "ddr5.mrcd.dca-configuration"
995 #define SPD_KEY_DDR5_MRDIMM_IRXT "ddr5.mrdimm.interface-rx-type"
1006 * be flipped between packages. These exist for all 64-bits of DQ and 8 bits of
1012 #define SPD_KEY_DDR4_MAP_DQ0 "module.dq0-map" /* uint32_t [4] */
1013 #define SPD_KEY_DDR4_MAP_DQ4 "module.dq4-map" /* uint32_t [4] */
1014 #define SPD_KEY_DDR4_MAP_DQ8 "module.dq8-map" /* uint32_t [4] */
1015 #define SPD_KEY_DDR4_MAP_DQ12 "module.dq12-map" /* uint32_t [4] */
1016 #define SPD_KEY_DDR4_MAP_DQ16 "module.dq16-map" /* uint32_t [4] */
1017 #define SPD_KEY_DDR4_MAP_DQ20 "module.dq20-map" /* uint32_t [4] */
1018 #define SPD_KEY_DDR4_MAP_DQ24 "module.dq24-map" /* uint32_t [4] */
1019 #define SPD_KEY_DDR4_MAP_DQ28 "module.dq28-map" /* uint32_t [4] */
1020 #define SPD_KEY_DDR4_MAP_DQ32 "module.dq32-map" /* uint32_t [4] */
1021 #define SPD_KEY_DDR4_MAP_DQ36 "module.dq36-map" /* uint36_t [4] */
1022 #define SPD_KEY_DDR4_MAP_DQ40 "module.dq40-map" /* uint32_t [4] */
1023 #define SPD_KEY_DDR4_MAP_DQ44 "module.dq44-map" /* uint32_t [4] */
1024 #define SPD_KEY_DDR4_MAP_DQ48 "module.dq48-map" /* uint32_t [4] */
1025 #define SPD_KEY_DDR4_MAP_DQ52 "module.dq52-map" /* uint32_t [4] */
1026 #define SPD_KEY_DDR4_MAP_DQ56 "module.dq56-map" /* uint32_t [4] */
1027 #define SPD_KEY_DDR4_MAP_DQ60 "module.dq60-map" /* uint32_t [4] */
1028 #define SPD_KEY_DDR4_MAP_CB0 "module.cb0-map" /* uint32_t [4] */
1029 #define SPD_KEY_DDR4_MAP_CB4 "module.cb4-map" /* uint32_t [4] */
1036 #define SPD_KEY_MOD_EDGE_MIRROR "module.edge-odd-mirror" /* key */
1157 #define SPD_KEY_DEV_TEMP_MFG "module.temp.mfg-id" /* uint32_t [2] */
1158 #define SPD_KEY_DEV_TEMP_MFG_NAME "module.temp.mfg-name" /* string */
1162 #define SPD_KEY_DEV_PMIC0_MFG "module.pmic0.mfg-id" /* uint32_t [2] */
1163 #define SPD_KEY_DEV_PMIC0_MFG_NAME "module.pmic0.mfg-name" /* string */
1166 #define SPD_KEY_DEV_PMIC1_MFG "module.pmic1.mfg-id" /* uint32_t [2] */
1167 #define SPD_KEY_DEV_PMIC1_MFG_NAME "module.pmic1.mfg-name" /* string */
1170 #define SPD_KEY_DEV_PMIC2_MFG "module.pmic2.mfg-id" /* uint32_t [2] */
1171 #define SPD_KEY_DEV_PMIC2_MFG_NAME "module.pmic2.mfg-name" /* string */
1175 #define SPD_KEY_DEV_CD0_MFG "module.cd0.mfg-id" /* uint32_t [2] */
1176 #define SPD_KEY_DEV_CD0_MFG_NAME "module.cd0.mfg-name" /* string */
1179 #define SPD_KEY_DEV_CD1_MFG "module.cd1.mfg-id" /* uint32_t [2] */
1180 #define SPD_KEY_DEV_CD1_MFG_NAME "module.cd1.mfg-name" /* string */
1184 #define SPD_KEY_DEV_RCD_MFG "module.rcd.mfg-id" /* uint32_t [2] */
1185 #define SPD_KEY_DEV_RCD_MFG_NAME "module.rcd.mfg-name" /* string */
1189 #define SPD_KEY_DEV_DB_MFG "module.db.mfg-id" /* uint32_t [2] */
1190 #define SPD_KEY_DEV_DB_MFG_NAME "module.db.mfg-name" /* string */
1194 #define SPD_KEY_DEV_MRCD_MFG "module.mrcd.mfg-id" /* uint32_t [2] */
1195 #define SPD_KEY_DEV_MRCD_MFG_NAME "module.mrcd.mfg-name" /* string */
1199 #define SPD_KEY_DEV_MDB_MFG "module.mdb.mfg-id" /* uint32_t [2] */
1200 #define SPD_KEY_DEV_MDB_MFG_NAME "module.mdb.mfg-name" /* string */
1204 #define SPD_KEY_DEV_DMB_MFG "module.dmb.mfg-id" /* uint32_t [2] */
1205 #define SPD_KEY_DEV_DMB_MFG_NAME "module.dmb.mfg-name" /* string */
1209 #define SPD_KEY_DEV_SPD_MFG "module.spd.mfg-id" /* uint32_t [2] */
1210 #define SPD_KEY_DEV_SPD_MFG_NAME "module.spd.mfg-name" /* string */
1232 #define SPD_KEY_MOD_FRONT_THICK "module.front-thickness" /* uint32_t */
1233 #define SPD_KEY_MOD_BACK_THICK "module.back-thickness" /* uint32_t */
1240 #define SPD_KEY_MOD_NROWS "module.dram-die-rows" /* uint32_t */
1241 #define SPD_KEY_MOD_NREGS "module.total-registers" /* uint32_t */
1248 #define SPD_KEY_MOD_OPER_TEMP "module.operating-temperature" /* uint32_t */
1254 #define SPD_KEY_MOD_REF_DESIGN "module.reference-design" /* string */
1255 #define SPD_KEY_MOD_DESIGN_REV "module.design-revision" /* uint32_t */
1259 * information is made available. This space is not DIMM-revision specific. All
1264 #define SPD_KEY_MFG_MOD_MFG_ID "mfg.module-mfg-id" /* uint32[2] */
1265 #define SPD_KEY_MFG_MOD_MFG_NAME "mfg.module-mfg-name" /* string */
1266 #define SPD_KEY_MFG_DRAM_MFG_ID "mfg.dram-mfg-id" /* uint32[2] */
1267 #define SPD_KEY_MFG_DRAM_MFG_NAME "mfg.dram-mfg-name" /* string */
1268 #define SPD_KEY_MFG_MOD_LOC_ID "mfg.module-loc-id" /* uint32 */
1269 #define SPD_KEY_MFG_MOD_YEAR "mfg.module-year" /* string */
1270 #define SPD_KEY_MFG_MOD_WEEK "mfg.module-week" /* string */
1271 #define SPD_KEY_MFG_MOD_PN "mfg.module-pn" /* string */
1272 #define SPD_KEY_MFG_MOD_SN "mfg.module-sn" /* string */
1273 #define SPD_KEY_MFG_MOD_REV "mfg.module-rev" /* string */
1274 #define SPD_KEY_MFG_DRAM_STEP "mfg.dram-step" /* string */
1282 * There is currently an additional top-level special key. This is the
1299 * This indicates that we encountered an non-ASCII or unprintable