86 #define	USall_EVENTS_0(v)					\  argument
87 	{v,		0x0,	"Cycle_cnt"},			\
88 	{v,		0x1,	"Instr_cnt"},			\
89 	{v,		0x2,	"Dispatch0_IC_miss"},		\
90 	{v,		0x8,	"IC_ref"},			\
91 	{v,		0x9,	"DC_rd"},			\
92 	{v,		0xa,	"DC_wr"},			\
93 	{v,		0xc,	"EC_ref"},			\
94 	{v,		0xe,	"EC_snoop_inv"}
105 #define	US3all_EVENTS_0(v)					\  argument
106 	{v,		0x3,	"Dispatch0_br_target"},		\
107 	{v,		0x4,	"Dispatch0_2nd_br"},		\
108 	{v,		0x5,	"Rstall_storeQ"},		\
109 	{v,		0x6,	"Rstall_IU_use"},		\
110 	{v,		0xd,	"EC_write_hit_RTO"},		\
111 	{v,		0xf,	"EC_rd_miss"},			\
112 	{v,		0x10,	"PC_port0_rd"},			\
113 	{v,		0x11,	"SI_snoop"},			\
114 	{v,		0x12,	"SI_ciq_flow"},			\
115 	{v,		0x13,	"SI_owned"},			\
116 	{v,		0x14,	"SW_count_0"},			\
117 	{v,		0x15,	"IU_Stat_Br_miss_taken"},	\
118 	{v,		0x16,	"IU_Stat_Br_count_taken"},	\
119 	{v,		0x17,	"Dispatch_rs_mispred"},		\
120 	{v,		0x18,	"FA_pipe_completion"}
122 #define	US3_MC_EVENTS_0(v)					\  argument
123 	{v,		0x20,	"MC_reads_0"},			\
124 	{v,		0x21,	"MC_reads_1"},			\
125 	{v,		0x22,	"MC_reads_2"},			\
126 	{v,		0x23,	"MC_reads_3"},			\
127 	{v,		0x24,	"MC_stalls_0"},			\
128 	{v,		0x25,	"MC_stalls_2"}
130 #define	US3_I_MC_EVENTS_0(v)					\  argument
131 	{v,		0x20,	"MC_read_dispatched"},		\
132 	{v,		0x21,	"MC_write_dispatched"},		\
133 	{v,		0x22,	"MC_read_returned_to_JBU"},	\
134 	{v,		0x23,	"MC_msl_busy_stall"},		\
135 	{v,		0x24,	"MC_mdb_overflow_stall"},	\
136 	{v,		0x25,	"MC_miu_spec_request"}
223 #define	USall_EVENTS_1(v)					\  argument
224 	{v,		0x0,	"Cycle_cnt"},			\
225 	{v,		0x1,	"Instr_cnt"},			\
226 	{v,		0x2,	"Dispatch0_mispred"},		\
227 	{v,		0xd,	"EC_wb"},			\
228 	{v,		0xe,	"EC_snoop_cb"}
242 #define	US3all_EVENTS_1(v)					\  argument
243 	{v,		0x3,	"IC_miss_cancelled"},		\
244 	{v,		0x5,	"Re_FPU_bypass"},		\
245 	{v,		0x6,	"Re_DC_miss"},			\
246 	{v,		0x7,	"Re_EC_miss"},			\
247 	{v,		0x8,	"IC_miss"},			\
248 	{v,		0x9,	"DC_rd_miss"},			\
249 	{v,		0xa,	"DC_wr_miss"},			\
250 	{v,		0xb,	"Rstall_FP_use"},		\
251 	{v,		0xc,	"EC_misses"},			\
252 	{v,		0xf,	"EC_ic_miss"},			\
253 	{v,		0x10,	"Re_PC_miss"},			\
254 	{v,		0x11,	"ITLB_miss"},			\
255 	{v,		0x12,	"DTLB_miss"},			\
256 	{v,		0x13,	"WC_miss"},			\
257 	{v,		0x14,	"WC_snoop_cb"},			\
258 	{v,		0x15,	"WC_scrubbed"},			\
259 	{v,		0x16,	"WC_wb_wo_read"},		\
260 	{v,		0x18,	"PC_soft_hit"},			\
261 	{v,		0x19,	"PC_snoop_inv"},		\
262 	{v,		0x1a,	"PC_hard_hit"},			\
263 	{v,		0x1b,	"PC_port1_rd"},			\
264 	{v,		0x1c,	"SW_count_1"},			\
265 	{v,		0x1d,	"IU_Stat_Br_miss_untaken"},	\
266 	{v,		0x1e,	"IU_Stat_Br_count_untaken"},	\
267 	{v,		0x1f,	"PC_MS_misses"},		\
268 	{v,		0x26,	"Re_RAW_miss"},			\
269 	{v,		0x27,	"FM_pipe_completion"}
271 #define	US3_MC_EVENTS_1(v)					\  argument
272 	{v,		0x20,	"MC_writes_0"},			\
273 	{v,		0x21,	"MC_writes_1"},			\
274 	{v,		0x22,	"MC_writes_2"},			\
275 	{v,		0x23,	"MC_writes_3"},			\
276 	{v,		0x24,	"MC_stalls_1"},			\
277 	{v,		0x25,	"MC_stalls_3"}
279 #define	US3_I_MC_EVENTS_1(v)					\  argument
280 	{v,		0x20,	"MC_open_bank_cmds"},		\
281 	{v,		0x21,	"MC_reads"},			\
282 	{v,		0x22,	"MC_writes"},			\
283 	{v,		0x23,	"MC_page_close_stall"}