57 #define	V_US12		(1u << 0)	/* specific to UltraSPARC 1 and 2 */
83  * Definitions for counter 0
87 	{v,		0x0,	"Cycle_cnt"},			\
88 	{v,		0x1,	"Instr_cnt"},			\
89 	{v,		0x2,	"Dispatch0_IC_miss"},		\
90 	{v,		0x8,	"IC_ref"},			\
91 	{v,		0x9,	"DC_rd"},			\
92 	{v,		0xa,	"DC_wr"},			\
93 	{v,		0xc,	"EC_ref"},			\
94 	{v,		0xe,	"EC_snoop_inv"}
98 	{V_US12,	0x3,	"Dispatch0_storeBuf"},
99 	{V_US12,	0xb,	"Load_use"},
100 	{V_US12,	0xd,	"EC_write_hit_RDO"},
101 	{V_US12,	0xf,	"EC_rd_hit"},
106 	{v,		0x3,	"Dispatch0_br_target"},		\
107 	{v,		0x4,	"Dispatch0_2nd_br"},		\
108 	{v,		0x5,	"Rstall_storeQ"},		\
109 	{v,		0x6,	"Rstall_IU_use"},		\
110 	{v,		0xd,	"EC_write_hit_RTO"},		\
111 	{v,		0xf,	"EC_rd_miss"},			\
112 	{v,		0x10,	"PC_port0_rd"},			\
113 	{v,		0x11,	"SI_snoop"},			\
114 	{v,		0x12,	"SI_ciq_flow"},			\
115 	{v,		0x13,	"SI_owned"},			\
116 	{v,		0x14,	"SW_count_0"},			\
117 	{v,		0x15,	"IU_Stat_Br_miss_taken"},	\
118 	{v,		0x16,	"IU_Stat_Br_count_taken"},	\
119 	{v,		0x17,	"Dispatch_rs_mispred"},		\
120 	{v,		0x18,	"FA_pipe_completion"}
123 	{v,		0x20,	"MC_reads_0"},			\
124 	{v,		0x21,	"MC_reads_1"},			\
125 	{v,		0x22,	"MC_reads_2"},			\
126 	{v,		0x23,	"MC_reads_3"},			\
127 	{v,		0x24,	"MC_stalls_0"},			\
128 	{v,		0x25,	"MC_stalls_2"}
131 	{v,		0x20,	"MC_read_dispatched"},		\
132 	{v,		0x21,	"MC_write_dispatched"},		\
133 	{v,		0x22,	"MC_read_returned_to_JBU"},	\
134 	{v,		0x23,	"MC_msl_busy_stall"},		\
135 	{v,		0x24,	"MC_mdb_overflow_stall"},	\
136 	{v,		0x25,	"MC_miu_spec_request"}
146 	{V_US4_PLUS,	0x0,   "Cycle_cnt"},
147 	{V_US4_PLUS,	0x1,   "Instr_cnt"},
148 	{V_US4_PLUS,	0x2,   "Dispatch0_IC_miss"},
149 	{V_US4_PLUS,	0x3,   "IU_stat_jmp_correct_pred"},
150 	{V_US4_PLUS,	0x4,   "Dispatch0_2nd_br"},
151 	{V_US4_PLUS,	0x5,   "Rstall_storeQ"},
152 	{V_US4_PLUS,	0x6,   "Rstall_IU_use"},
153 	{V_US4_PLUS,	0x7,   "IU_stat_ret_correct_pred"},
154 	{V_US4_PLUS,	0x8,   "IC_ref"},
155 	{V_US4_PLUS,	0x9,   "DC_rd"},
156 	{V_US4_PLUS,	0xa,   "Rstall_FP_use"},
157 	{V_US4_PLUS,	0xb,   "SW_pf_instr"},
158 	{V_US4_PLUS,	0xc,   "L2_ref"},
159 	{V_US4_PLUS,	0xd,   "L2_write_hit_RTO"},
160 	{V_US4_PLUS,	0xe,   "L2_snoop_inv_sh"},
161 	{V_US4_PLUS,	0xf,   "L2_rd_miss"},
162 	{V_US4_PLUS,	0x10,  "PC_rd"},
163 	{V_US4_PLUS,	0x11,  "SI_snoop_sh"},
164 	{V_US4_PLUS,	0x12,  "SI_ciq_flow_sh"},
165 	{V_US4_PLUS,	0x13,  "Re_DC_miss"},
166 	{V_US4_PLUS,	0x14,  "SW_count_NOP"},
167 	{V_US4_PLUS,	0x15,  "IU_stat_br_miss_taken"},
168 	{V_US4_PLUS,	0x16,  "IU_stat_br_count_untaken"},
169 	{V_US4_PLUS,	0x17,  "HW_pf_exec"},
170 	{V_US4_PLUS,	0x18,  "FA_pipe_completion"},
171 	{V_US4_PLUS,	0x19,  "SSM_L3_wb_remote"},
172 	{V_US4_PLUS,	0x1a,  "SSM_L3_miss_local"},
173 	{V_US4_PLUS,	0x1b,  "SSM_L3_miss_mtag_remote"},
174 	{V_US4_PLUS,	0x1c,  "SW_pf_str_trapped"},
175 	{V_US4_PLUS,	0x1d,  "SW_pf_PC_installed"},
176 	{V_US4_PLUS,	0x1e,  "IPB_to_IC_fill"},
177 	{V_US4_PLUS,	0x1f,  "L2_write_miss"},
178 	{V_US4_PLUS,	0x20,  "MC_reads_0_sh"},
179 	{V_US4_PLUS,	0x21,  "MC_reads_1_sh"},
180 	{V_US4_PLUS,	0x22,  "MC_reads_2_sh"},
181 	{V_US4_PLUS,	0x23,  "MC_reads_3_sh"},
182 	{V_US4_PLUS,	0x24,  "MC_stalls_0_sh"},
183 	{V_US4_PLUS,	0x25,  "MC_stalls_2_sh"},
184 	{V_US4_PLUS,	0x26,  "L2_hit_other_half"},
185 	{V_US4_PLUS,	0x28,  "L3_rd_miss"},
186 	{V_US4_PLUS,	0x29,  "Re_L2_miss"},
187 	{V_US4_PLUS,	0x2a,  "IC_miss_cancelled"},
188 	{V_US4_PLUS,	0x2b,  "DC_wr_miss"},
189 	{V_US4_PLUS,	0x2c,  "L3_hit_I_state_sh"},
190 	{V_US4_PLUS,	0x2d,  "SI_RTS_src_data"},
191 	{V_US4_PLUS,	0x2e,  "L2_IC_miss"},
192 	{V_US4_PLUS,	0x2f,  "SSM_new_transaction_sh"},
193 	{V_US4_PLUS,	0x30,  "L2_SW_pf_miss"},
194 	{V_US4_PLUS,	0x31,  "L2_wb"},
195 	{V_US4_PLUS,	0x32,  "L2_wb_sh"},
196 	{V_US4_PLUS,	0x33,  "L2_snoop_cb_sh"},
204 	{V_US3_PLUS,	0x19,	"EC_wb_remote"},
205 	{V_US3_PLUS,	0x1a,	"EC_miss_local"},
206 	{V_US3_PLUS,	0x1b,	"EC_miss_mtag_remote"},
214 	{V_US3_PLUS,	0x19,	"EC_wb_remote"},
215 	{V_US3_PLUS,	0x1a,	"EC_miss_local"},
216 	{V_US3_PLUS,	0x1b,	"EC_miss_mtag_remote"},
224 	{v,		0x0,	"Cycle_cnt"},			\
225 	{v,		0x1,	"Instr_cnt"},			\
226 	{v,		0x2,	"Dispatch0_mispred"},		\
227 	{v,		0xd,	"EC_wb"},			\
228 	{v,		0xe,	"EC_snoop_cb"}
232 	{V_US12,	0x3,	"Dispatch0_FP_use"},
233 	{V_US12,	0x8,	"IC_hit"},
234 	{V_US12,	0x9,	"DC_rd_hit"},
235 	{V_US12,	0xa,	"DC_wr_hit"},
236 	{V_US12,	0xb,	"Load_use_RAW"},
237 	{V_US12,	0xc,	"EC_hit"},
238 	{V_US12,	0xf,	"EC_ic_hit"},
243 	{v,		0x3,	"IC_miss_cancelled"},		\
244 	{v,		0x5,	"Re_FPU_bypass"},		\
245 	{v,		0x6,	"Re_DC_miss"},			\
246 	{v,		0x7,	"Re_EC_miss"},			\
247 	{v,		0x8,	"IC_miss"},			\
248 	{v,		0x9,	"DC_rd_miss"},			\
249 	{v,		0xa,	"DC_wr_miss"},			\
250 	{v,		0xb,	"Rstall_FP_use"},		\
251 	{v,		0xc,	"EC_misses"},			\
252 	{v,		0xf,	"EC_ic_miss"},			\
253 	{v,		0x10,	"Re_PC_miss"},			\
254 	{v,		0x11,	"ITLB_miss"},			\
255 	{v,		0x12,	"DTLB_miss"},			\
256 	{v,		0x13,	"WC_miss"},			\
257 	{v,		0x14,	"WC_snoop_cb"},			\
258 	{v,		0x15,	"WC_scrubbed"},			\
259 	{v,		0x16,	"WC_wb_wo_read"},		\
260 	{v,		0x18,	"PC_soft_hit"},			\
261 	{v,		0x19,	"PC_snoop_inv"},		\
262 	{v,		0x1a,	"PC_hard_hit"},			\
263 	{v,		0x1b,	"PC_port1_rd"},			\
264 	{v,		0x1c,	"SW_count_1"},			\
265 	{v,		0x1d,	"IU_Stat_Br_miss_untaken"},	\
266 	{v,		0x1e,	"IU_Stat_Br_count_untaken"},	\
267 	{v,		0x1f,	"PC_MS_misses"},		\
268 	{v,		0x26,	"Re_RAW_miss"},			\
269 	{v,		0x27,	"FM_pipe_completion"}
272 	{v,		0x20,	"MC_writes_0"},			\
273 	{v,		0x21,	"MC_writes_1"},			\
274 	{v,		0x22,	"MC_writes_2"},			\
275 	{v,		0x23,	"MC_writes_3"},			\
276 	{v,		0x24,	"MC_stalls_1"},			\
277 	{v,		0x25,	"MC_stalls_3"}
280 	{v,		0x20,	"MC_open_bank_cmds"},		\
281 	{v,		0x21,	"MC_reads"},			\
282 	{v,		0x22,	"MC_writes"},			\
283 	{v,		0x23,	"MC_page_close_stall"}
289 	{V_US3,		0x4,	"Re_endian_miss"},
297 	{V_US3_PLUS,	0x4,	"Re_DC_missovhd"},
298 	{V_US3_PLUS,	0x28,	"EC_miss_mtag_remote"},
299 	{V_US3_PLUS,	0x29,	"EC_miss_remote"},
307 	{V_US3_I,	0x4,	"Re_DC_missovhd"},
312 	{V_US4_PLUS,	0x0,   "Cycle_cnt"},
313 	{V_US4_PLUS,	0x1,   "Instr_cnt"},
314 	{V_US4_PLUS,	0x2,   "Dispatch0_other"},
315 	{V_US4_PLUS,	0x3,   "DC_wr"},
316 	{V_US4_PLUS,	0x4,   "Re_DC_missovhd"},
317 	{V_US4_PLUS,	0x5,   "Re_FPU_bypass"},
318 	{V_US4_PLUS,	0x6,   "L3_write_hit_RTO"},
319 	{V_US4_PLUS,	0x7,   "L2L3_snoop_inv_sh"},
320 	{V_US4_PLUS,	0x8,   "IC_L2_req"},
321 	{V_US4_PLUS,	0x9,   "DC_rd_miss"},
322 	{V_US4_PLUS,	0xa,   "L2_hit_I_state_sh"},
323 	{V_US4_PLUS,	0xb,   "L3_write_miss_RTO"},
324 	{V_US4_PLUS,	0xc,   "L2_miss"},
325 	{V_US4_PLUS,	0xd,   "SI_owned_sh"},
326 	{V_US4_PLUS,	0xe,   "SI_RTO_src_data"},
327 	{V_US4_PLUS,	0xf,   "SW_pf_duplicate"},
328 	{V_US4_PLUS,	0x10,  "IU_stat_jmp_mispred"},
329 	{V_US4_PLUS,	0x11,  "ITLB_miss"},
330 	{V_US4_PLUS,	0x12,  "DTLB_miss"},
331 	{V_US4_PLUS,	0x13,  "WC_miss"},
332 	{V_US4_PLUS,	0x14,  "IC_fill"},
333 	{V_US4_PLUS,	0x15,  "IU_stat_ret_mispred"},
334 	{V_US4_PLUS,	0x16,  "Re_L3_miss"},
335 	{V_US4_PLUS,	0x17,  "Re_PFQ_full"},
336 	{V_US4_PLUS,	0x18,  "PC_soft_hit"},
337 	{V_US4_PLUS,	0x19,  "PC_inv"},
338 	{V_US4_PLUS,	0x1a,  "PC_hard_hit"},
339 	{V_US4_PLUS,	0x1b,  "IC_pf"},
340 	{V_US4_PLUS,	0x1c,  "SW_count_NOP"},
341 	{V_US4_PLUS,	0x1d,  "IU_stat_br_miss_untaken"},
342 	{V_US4_PLUS,	0x1e,  "IU_stat_br_count_taken"},
343 	{V_US4_PLUS,	0x1f,  "PC_miss"},
344 	{V_US4_PLUS,	0x20,  "MC_writes_0_sh"},
345 	{V_US4_PLUS,	0x21,  "MC_writes_1_sh"},
346 	{V_US4_PLUS,	0x22,  "MC_writes_2_sh"},
347 	{V_US4_PLUS,	0x23,  "MC_writes_3_sh"},
348 	{V_US4_PLUS,	0x24,  "MC_stalls_1_sh"},
349 	{V_US4_PLUS,	0x25,  "MC_stalls_3_sh"},
350 	{V_US4_PLUS,	0x26,  "Re_RAW_miss"},
351 	{V_US4_PLUS,	0x27,  "FM_pipe_completion"},
352 	{V_US4_PLUS,	0x28,  "SSM_L3_miss_mtag_remote"},
353 	{V_US4_PLUS,	0x29,  "SSM_L3_miss_remote"},
354 	{V_US4_PLUS,	0x2a,  "SW_pf_exec"},
355 	{V_US4_PLUS,	0x2b,  "SW_pf_str_exec"},
356 	{V_US4_PLUS,	0x2c,  "SW_pf_dropped"},
357 	{V_US4_PLUS,	0x2d,  "SW_pf_L2_installed"},
358 	{V_US4_PLUS,	0x2f,  "L2_HW_pf_miss"},
359 	{V_US4_PLUS,	0x31,  "L3_miss"},
360 	{V_US4_PLUS,	0x32,  "L3_IC_miss"},
361 	{V_US4_PLUS,	0x33,  "L3_SW_pf_miss"},
362 	{V_US4_PLUS,	0x34,  "L3_hit_other_half"},
363 	{V_US4_PLUS,	0x35,  "L3_wb"},
364 	{V_US4_PLUS,	0x36,  "L3_wb_sh"},
365 	{V_US4_PLUS,	0x37,  "L2L3_snoop_cb_sh"},
402 	if (regno < 0 || regno > 1)  in validargs()
403 		return (0);  in validargs()
405 	if (cpuver < 0 ||  in validargs()
406 	    cpuver >= sizeof (cpuvermap) / sizeof (cpuvermap[0]))  in validargs()
407 		return (0);  in validargs()
416 		return (0);  in versionmatch()
491 		if (strcmp(name, n->name) == 0 &&  in __cpc_name_to_reg()
494 			return (0);  in __cpc_name_to_reg()
497 	value = strtol(name, &eptr, 0);  in __cpc_name_to_reg()
498 	if (name != eptr && value >= 0 && value <= UINT8_MAX) {  in __cpc_name_to_reg()
500 		return (0);  in __cpc_name_to_reg()
509 	if (validargs(cpuver, 0))  in cpc_getcciname()
533 	if (validargs(cpuver, 0))  in cpc_getcpuref()
578 		return (sizeof (event->ce_pic) / sizeof (event->ce_pic[0]));  in cpc_getnpic()
580 		return (0);  in cpc_getnpic()
592 	if (strcmp(node, "SUNW,UltraSPARC") == 0 ||  in node2ver()
593 	    strcmp(node, "SUNW,UltraSPARC-II") == 0 ||  in node2ver()
594 	    strcmp(node, "SUNW,UltraSPARC-IIi") == 0 ||  in node2ver()
595 	    strcmp(node, "SUNW,UltraSPARC-IIe") == 0) {  in node2ver()
597 	} else if (strcmp(node, "SUNW,UltraSPARC-III") == 0)  in node2ver()
599 	else if (strcmp(node, "SUNW,UltraSPARC-III+") == 0 ||  in node2ver()
600 	    strcmp(node, "SUNW,UltraSPARC-IV") == 0)  in node2ver()
602 	else if (strcmp(node, "SUNW,UltraSPARC-IIIi") == 0 ||  in node2ver()
603 	    strcmp(node, "SUNW,UltraSPARC-IIIi+") == 0)  in node2ver()
605 	else if (strcmp(node, "SUNW,UltraSPARC-IV+") == 0)  in node2ver()
615 	int		n_names, i, found = 0;  in cpc_get_cpu_ver()
622 		else if (strncmp(node_name, "cpu", 4) == 0) {  in cpc_get_cpu_ver()
629 			    &compatible_array)) > 0) {  in cpc_get_cpu_ver()
630 				for (i = 0; i < n_names; i++) {  in cpc_get_cpu_ver()
643 	if (found == 0)  in cpc_get_cpu_ver()