Lines Matching refs:V_P5mmx
48 #define V_P5mmx (1u << 1) /* " MMX instructions */ macro
58 V_P5 | V_P5mmx, /* CPC_PENTIUM_MMX */
114 {V_P5mmx, 0x2a, "bus_ownership_latency"},
115 {V_P5mmx, 0x2b, "mmx_instr_upipe"},
116 {V_P5mmx, 0x2c, "cache_M_line_sharing"},
117 {V_P5mmx, 0x2d, "emms_instr"},
118 {V_P5mmx, 0x2e, "bus_util_processor"},
119 {V_P5mmx, 0x2f, "sat_mmx_instr"},
120 {V_P5mmx, 0x30, "clks_not_HLT"},
121 {V_P5mmx, 0x31, "mmx_data_read"},
122 {V_P5mmx, 0x32, "clks_fp_stall"},
123 {V_P5mmx, 0x33, "d1_starv_fifo_0"},
124 {V_P5mmx, 0x34, "mmx_data_write"},
125 {V_P5mmx, 0x35, "pipe_flush_wbp"},
126 {V_P5mmx, 0x36, "mmx_misalign_data_refs"},
127 {V_P5mmx, 0x37, "rets_pred_incorrect"},
128 {V_P5mmx, 0x38, "mmx_multiply_unit_interlock"},
129 {V_P5mmx, 0x39, "rets"},
130 {V_P5mmx, 0x3a, "btb_false_entries"},
131 {V_P5mmx, 0x3b, "clocks_stall_full_wb"},
137 {V_P5mmx, 0x2a, "bus_ownership_transfers"},
138 {V_P5mmx, 0x2b, "mmx_instr_vpipe"},
139 {V_P5mmx, 0x2c, "cache_lint_sharing"},
140 {V_P5mmx, 0x2d, "mmx_fp_transitions"},
141 {V_P5mmx, 0x2e, "writes_noncache_mem"},
142 {V_P5mmx, 0x2f, "sats_performed"},
143 {V_P5mmx, 0x30, "clks_dcache_tlb_miss"},
144 {V_P5mmx, 0x31, "mmx_data_read_miss"},
145 {V_P5mmx, 0x32, "taken_br"},
146 {V_P5mmx, 0x33, "d1_starv_fifo_1"},
147 {V_P5mmx, 0x34, "mmx_data_write_miss"},
148 {V_P5mmx, 0x35, "pipe_flush_wbp_wb"},
149 {V_P5mmx, 0x36, "mmx_pipe_stall_data_read"},
150 {V_P5mmx, 0x37, "rets_pred"},
151 {V_P5mmx, 0x38, "movd_movq_stall"},
152 {V_P5mmx, 0x39, "rsb_overflow"},
153 {V_P5mmx, 0x3a, "btb_mispred_nt"},
154 {V_P5mmx, 0x3b, "mmx_stall_write_ME"},
323 case V_P5 | V_P5mmx: in versionmatch()
363 case V_P5 | V_P5mmx: in getnametable()
439 case V_P5 | V_P5mmx: in cpc_getcciname()
457 case V_P5 | V_P5mmx: in cpc_getcpuref()