158 #undef writel
164 #define writel outl  macro
309     writel(0x00000001, ioaddr + PCIBusCfg);  in w89c840_reset()
313     writel(virt_to_bus(w840private.rx_ring), ioaddr + RxRingPtr);  in w89c840_reset()
314     writel(virt_to_bus(w840private.tx_ring), ioaddr + TxRingPtr);  in w89c840_reset()
331     writel(0xE010, ioaddr + PCIBusCfg);  in w89c840_reset()
333     writel(0, ioaddr + RxStartDemand);  in w89c840_reset()
356         writel(intr_stat & 0x001ffff, ioaddr + IntrStatus);
370             writel(0, ioaddr + RxStartDemand);
522     writel(0, ioaddr + TxStartDemand);  in w89c840_transmit()
591     writel(w840private.csr6 &= ~0x20FA, ioaddr + NetworkConfig);  in w89c840_disable()
672     writel(0x00000001, ioaddr + PCIBusCfg);  in w89c840_probe()
737     writel(EE_ChipSelect, ee_addr);  in eeprom_read()
742         writel(dataval, ee_addr);  in eeprom_read()
744         writel(dataval | EE_ShiftClk, ee_addr);  in eeprom_read()
747     writel(EE_ChipSelect, ee_addr);  in eeprom_read()
750         writel(EE_ChipSelect | EE_ShiftClk, ee_addr);  in eeprom_read()
753         writel(EE_ChipSelect, ee_addr);  in eeprom_read()
758     writel(0, ee_addr);  in eeprom_read()
787         writel(MDIO_WRITE1, mdio_addr);  in mdio_sync()
789         writel(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);  in mdio_sync()
807         writel(dataval, mdio_addr);  in mdio_read()
809         writel(dataval | MDIO_ShiftClk, mdio_addr);  in mdio_read()
814         writel(MDIO_EnbIn, mdio_addr);  in mdio_read()
817         writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);  in mdio_read()
840         writel(dataval, mdio_addr);
842         writel(dataval | MDIO_ShiftClk, mdio_addr);
847         writel(MDIO_EnbIn, mdio_addr);
849         writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
893     writel(mc_filter[0], ioaddr + MulticastFilter0);  in set_rx_mode()
894     writel(mc_filter[1], ioaddr + MulticastFilter1);  in set_rx_mode()
897     writel(w840private.csr6, ioaddr + NetworkConfig);  in set_rx_mode()