Lines Matching +full:edp +full:- +full:phy
3 Adapted 09-jan-2000 by Paolo Marini (paolom@prisma-eng.it)
16 This driver is designed for the VIA VT86C100A Rhine-II PCI Fast Ethernet
21 static const char *version = "rhine.c v1.0.1 2003-02-06\n";
23 /* A few user-configurable values. */
25 /* Size of the in-memory receive ring. */
29 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
37 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024. */
110 /*--------------------- Exioaddr Definitions -------------------------*/
414 #define NIC_LB_PHY 0x02 /* MII or Internal-10BaseT loopback */
461 unsigned long edp:1; member
489 unsigned long edp:1; member
492 unsigned long phy:1; member
540 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
543 II. Board-specific settings
545 Boards with this chip are functional only in a bus-master PCI slot.
556 This driver uses two statically allocated fixed-size descriptor lists
562 This driver attempts to use a zero-copy receive and transmit scheme.
568 open() time and passes the skb->data field to the chip as receive data
575 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
576 using a full-sized skbuff for small frames vs. the copying costs of larger
587 has the beneficial effect of 16-byte aligning the IP header.
591 The driver runs as two independent, single-threaded flows of control. One
592 is the send-packet routine, which enforces single-threaded use by the
593 dev->tbusy flag. The other thread is the interrupt handler, which is single
596 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
599 the 'lp->tx_full' flag.
603 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
643 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
648 unsigned int full_duplex:1; /* Full-duplex operation requested. */
649 unsigned int default_port:4; /* Last dev->if_port value. */
673 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; in rhine_init_ring()
676 tp->tx_full = 0; in rhine_init_ring()
677 tp->cur_rx = tp->cur_tx = 0; in rhine_init_ring()
678 tp->dirty_rx = tp->dirty_tx = 0; in rhine_init_ring()
683 tp->rx_ring[i].rx_status.bits.own_bit = 1; in rhine_init_ring()
684 tp->rx_ring[i].rx_ctrl.bits.rx_buf_size = 1536; in rhine_init_ring()
686 tp->rx_ring[i].buf_addr_1 = virt_to_bus (tp->rx_buffs[i]); in rhine_init_ring()
687 tp->rx_ring[i].buf_addr_2 = virt_to_bus (&tp->rx_ring[i + 1]); in rhine_init_ring()
688 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->rx_ring[i].buf_addr_1,tp->rx_ring[i].buf_addr_2); */ in rhine_init_ring()
691 /* tp->rx_ring[i-1].rx_ctrl.bits.rx_buf_size =1518; */ in rhine_init_ring()
692 tp->rx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->rx_ring[0]); in rhine_init_ring()
693 … /*printf("[%d]buf1=%hX,buf2=%hX",i-1,tp->rx_ring[i-1].buf_addr_1,tp->rx_ring[i-1].buf_addr_2); */ in rhine_init_ring()
701 tp->tx_ring[i].tx_status.lw = 0; in rhine_init_ring()
702 tp->tx_ring[i].tx_ctrl.lw = 0x00e08000; in rhine_init_ring()
703 tp->tx_ring[i].buf_addr_1 = virt_to_bus (tp->tx_buffs[i]); in rhine_init_ring()
704 tp->tx_ring[i].buf_addr_2 = virt_to_bus (&tp->tx_ring[i + 1]); in rhine_init_ring()
705 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i].buf_addr_1,tp->tx_ring[i].buf_addr_2); */ in rhine_init_ring()
708 tp->tx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->tx_ring[0]); in rhine_init_ring()
709 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i-1].buf_addr_1,tp->tx_ring[i-1].buf_addr_2); */ in rhine_init_ring()
885 IRQ - PXE IRQ Handler
888 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; in rhine_irq()
895 intr_status = inw(nic->ioaddr + IntrStatus); in rhine_irq()
896 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ in rhine_irq()
897 if (tp->chip_id == 0x3065) in rhine_irq()
898 intr_status |= inb(nic->ioaddr + IntrStatus2) << 16; in rhine_irq()
902 outw(intr_status, nic->ioaddr + IntrEnable); in rhine_irq()
905 outw(0x0010, nic->ioaddr + 0x84); in rhine_irq()
915 if (!pci->ioaddr) in rhine_probe()
917 rhine_probe1 (nic, pci->ioaddr, pci->dev_id, -1); in rhine_probe()
922 dev->disable = rhine_disable; in rhine_probe()
923 nic->poll = rhine_poll; in rhine_probe()
924 nic->transmit = rhine_transmit; in rhine_probe()
925 nic->irqno = pci->irq; in rhine_probe()
926 nic->irq = rhine_irq; in rhine_probe()
927 nic->ioaddr = tp->ioaddr; in rhine_probe()
934 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; in set_rx_mode()
936 int ioaddr = tp->ioaddr; in set_rx_mode()
959 /* D-Link provided reset code (with comment additions) */ in rhine_probe1()
972 /* disable force PME-enable */ in rhine_probe1()
974 /* disable power-event config bit */ in rhine_probe1()
983 nic->node_addr[i] = inb (byPAR0 + i); in rhine_probe1()
984 printf ("IO address %hX Ethernet Address: %!\n", ioaddr, nic->node_addr); in rhine_probe1()
986 /* restart MII auto-negotiation */ in rhine_probe1()
991 /* need to wait 1 millisecond - we will round it up to 50-100ms */ in rhine_probe1()
1054 nic->priv_data = &rhine; in rhine_probe1()
1056 tp->chip_id = chip_id; in rhine_probe1()
1057 tp->ioaddr = ioaddr; in rhine_probe1()
1058 tp->phys[0] = -1; in rhine_probe1()
1063 tp->full_duplex = (options & 16) ? 1 : 0; in rhine_probe1()
1064 tp->default_port = options & 15; in rhine_probe1()
1065 if (tp->default_port) in rhine_probe1()
1066 tp->medialock = 1; in rhine_probe1()
1075 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; in rhine_disable()
1076 int ioaddr = tp->ioaddr; in rhine_disable()
1089 ETH_RESET - Reset adapter
1094 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; in rhine_reset()
1095 int ioaddr = tp->ioaddr; in rhine_reset()
1121 tp->rx_ring = (struct rhine_rx_desc *) bus_to_virt (j); in rhine_reset()
1125 tp->tx_ring = (struct rhine_tx_desc *) bus_to_virt (j); in rhine_reset()
1141 tp->rx_buffs[i] = (char *) rx_bufs_tmp; in rhine_reset()
1142 /* printf("r[%X]",tp->rx_buffs[i]); */ in rhine_reset()
1148 tp->tx_buffs[i] = (char *) tx_bufs_tmp; in rhine_reset()
1149 /* printf("t[%X]",tp->tx_buffs[i]); */ in rhine_reset()
1160 outl (virt_to_bus (tp->rx_ring), dwCurrentRxDescAddr); in rhine_reset()
1161 outl (virt_to_bus (tp->tx_ring), dwCurrentTxDescAddr); in rhine_reset()
1191 #define IOSYNC do { readb(nic->ioaddr + StationAddr); } while (0)
1196 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; in rhine_poll()
1199 if (tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit == 0) in rhine_poll()
1206 intr_status = inw(nic->ioaddr + IntrStatus); in rhine_poll()
1207 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ in rhine_poll()
1209 if (tp->chip_id == 0x3065) in rhine_poll()
1210 intr_status |= inb(nic->ioaddr + IntrStatus2) << 16; in rhine_poll()
1214 outb(0x08, nic->ioaddr + IntrStatus2); in rhine_poll()
1215 outw(intr_status & 0xffff, nic->ioaddr + IntrStatus); in rhine_poll()
1218 rxstatus = tp->rx_ring[tp->cur_rx].rx_status.lw; in rhine_poll()
1232 nic->packetlen = tp->rx_ring[tp->cur_rx].rx_status.bits.frame_length; in rhine_poll()
1233 memcpy (nic->packet, tp->rx_buffs[tp->cur_rx], nic->packetlen); in rhine_poll()
1236 tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit = 1; in rhine_poll()
1237 tp->cur_rx++; in rhine_poll()
1238 tp->cur_rx = tp->cur_rx % RX_RING_SIZE; in rhine_poll()
1241 outw(DEFAULT_INTR & ~IntrRxDone, nic->ioaddr + IntrStatus); in rhine_poll()
1252 struct rhine_private *tp = (struct rhine_private *) nic->priv_data; in rhine_transmit()
1253 int ioaddr = tp->ioaddr; in rhine_transmit()
1262 entry = tp->cur_tx % TX_RING_SIZE; in rhine_transmit()
1264 memcpy (tp->tx_buffs[entry], d, ETH_ALEN); /* dst */ in rhine_transmit()
1265 memcpy (tp->tx_buffs[entry] + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */ in rhine_transmit()
1266 *((char *) tp->tx_buffs[entry] + 12) = t >> 8; /* type */ in rhine_transmit()
1267 *((char *) tp->tx_buffs[entry] + 13) = t; in rhine_transmit()
1268 memcpy (tp->tx_buffs[entry] + ETH_HLEN, p, s); in rhine_transmit()
1271 *((char *) tp->tx_buffs[entry] + ETH_HLEN + (s++)) = 0; in rhine_transmit()
1273 tp->tx_ring[entry].tx_ctrl.bits.tx_buf_size = s; in rhine_transmit()
1275 tp->tx_ring[entry].tx_status.bits.own_bit = 1; in rhine_transmit()
1281 /*printf("tdsw=[%X]",tp->tx_ring[entry].tx_status.lw); */ in rhine_transmit()
1282 /*printf("tdcw=[%X]",tp->tx_ring[entry].tx_ctrl.lw); */ in rhine_transmit()
1283 /*printf("tdbuf1=[%X]",tp->tx_ring[entry].buf_addr_1); */ in rhine_transmit()
1284 /*printf("tdbuf2=[%X]",tp->tx_ring[entry].buf_addr_2); */ in rhine_transmit()
1292 while (tp->tx_ring[entry].tx_status.bits.own_bit != 0) in rhine_transmit()
1294 tp->cur_tx++; in rhine_transmit()
1297 /*dev_kfree_skb(tp->tx_skbuff[entry], FREE_WRITE); */ in rhine_transmit()
1298 /*tp->tx_skbuff[entry] = 0; */ in rhine_transmit()
1302 PCI_ROM(0x1106, 0x3065, "dlink-530tx", "VIA 6102"),
1303 PCI_ROM(0x1106, 0x3106, "via-rhine-6105", "VIA 6105"),
1304 PCI_ROM(0x1106, 0x3043, "dlink-530tx-old", "VIA 3043"), /* Rhine-I 86c100a */
1306 PCI_ROM(0x1106, 0x6100, "via-rhine-old", "VIA 86C100A"), /* Rhine-II */
1318 /* EOF via-rhine.c */