Lines Matching +full:0 +full:x0b00
58 support LNE100TX v2.0 cards, which use a different controller.
115 static int tulip_debug = 2; /* 1 normal messages, 0 quiet .. 7 verbose. */
135 #define TULIP_SIZE 0x80
141 #define FULL_DUPLEX_MAGIC 0x6969
143 static const int csr0 = 0x01A00000 | 0x8000;
157 DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3,
166 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
167 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
168 PCI_UNUSED_IRQ=0x800,
183 { "Digital DC21040 Tulip", { 0x00021011, 0xffffffff, 0, 0, 0, 0 },
184 TULIP_IOTYPE, 0x80, DC21040 },
185 { "Digital DC21041 Tulip", { 0x00141011, 0xffffffff, 0, 0, 0, 0 },
186 TULIP_IOTYPE, 0x80, DC21041 },
187 { "Digital DS21140A Tulip", { 0x00091011, 0xffffffff, 0,0, 0x20,0xf0 },
188 TULIP_IOTYPE, 0x80, DC21140 },
189 { "Digital DS21140 Tulip", { 0x00091011, 0xffffffff, 0, 0, 0, 0 },
190 TULIP_IOTYPE, 0x80, DC21140 },
191 { "Digital DS21143 Tulip", { 0x00191011, 0xffffffff, 0,0, 65,0xff },
193 { "Digital DS21142 Tulip", { 0x00191011, 0xffffffff, 0, 0, 0, 0 },
195 { "Kingston KNE110tx (PNIC)", { 0x000211AD, 0xffffffff, 0xf0022646, 0xffffffff, 0, 0 },
197 { "Lite-On 82c168 PNIC", { 0x000211AD, 0xffffffff, 0, 0, 0, 0 },
199 { "Macronix 98713 PMAC", { 0x051210d9, 0xffffffff, 0, 0, 0, 0 },
201 { "Macronix 98715 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 },
203 { "Macronix 98725 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 },
205 { "ASIX AX88141", { 0x1400125B, 0xffffffff, 0,0, 0x10, 0xf0 },
207 { "ASIX AX88140", { 0x1400125B, 0xffffffff, 0, 0, 0, 0 },
209 { "Lite-On LC82C115 PNIC-II", { 0xc11511AD, 0xffffffff, 0, 0, 0, 0 },
211 { "ADMtek AN981 Comet", { 0x09811317, 0xffffffff, 0, 0, 0, 0 },
213 { "ADMTek AN983 Comet", { 0x12161113, 0xffffffff, 0, 0, 0, 0 },
215 { "ADMtek Centaur-P", { 0x09851317, 0xffffffff, 0, 0, 0, 0 },
217 { "ADMtek Centaur-C", { 0x19851317, 0xffffffff, 0, 0, 0, 0 },
219 { "Compex RL100-TX", { 0x988111F6, 0xffffffff, 0, 0, 0, 0 },
221 { "Intel 21145 Tulip", { 0x00398086, 0xffffffff, 0, 0, 0, 0 },
223 { "Xircom Tulip clone", { 0x0003115d, 0xffffffff, 0, 0, 0, 0 },
225 { "Davicom DM9102", { 0x91021282, 0xffffffff, 0, 0, 0, 0 },
226 TULIP_IOTYPE, 0x80, DC21140 },
227 { "Davicom DM9100", { 0x91001282, 0xffffffff, 0, 0, 0, 0 },
228 TULIP_IOTYPE, 0x80, DC21140 },
229 { "Macronix mxic-98715 (EN1217)", { 0x12171113, 0xffffffff, 0, 0, 0, 0 },
231 { 0, { 0, 0, 0, 0, 0, 0 }, 0, 0, 0 },
236 HAS_PWRDWN=0x10, MC_HASH_ONLY=0x20, /* Hash-only multicast filter. */
237 HAS_PNICNWAY=0x80, HAS_NWAY=0x40, /* Uses internal NWay xcvr. */
238 HAS_INTR_MITIGATION=0x100, IS_ASIX=0x200, HAS_8023X=0x400,
246 { "Digital DC21040 Tulip", 0},
266 { 0, 0 },
275 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 20,31,0,0, };
276 static u8 t21040_csr13[] = {2,0x0C,8,4, 4,0,0,0, 0,0,0,0, 4,0,0,0};
279 static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, };
280 static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
281 static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
284 static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
286 static u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
288 static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
294 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
295 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
296 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
301 TimerInt=0x800, TPLnkFail=0x1000, TPLnkPass=0x10,
302 NormalIntr=0x10000, AbnormalIntr=0x8000,
303 RxJabber=0x200, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40,
304 TxFIFOUnderflow=0x20, TxJabber=0x08, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01,
309 TxOn=0x2000, RxOn=0x0002, FullDuplex=0x0200,
310 AcceptBroadcast=0x0100, AcceptAllMulticast=0x0080,
311 AcceptAllPhys=0x0040, AcceptRunt=0x0008,
316 DescOwnded=0x80000000, RxDescFatalErr=0x8000, RxWholePkt=0x0300,
330 struct medialeaf mleaf[0];
350 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
351 #define EE_CS 0x01 /* EEPROM chip select. */
352 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
353 #define EE_WRITE_0 0x01
354 #define EE_WRITE_1 0x05
355 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
356 #define EE_ENB (0x4800 | EE_CS)
367 0x01000000 means chain on buffer2 address,
368 0x02000000 means use the ring start address in CSR2/3.
373 #define DESC_RING_WRAP 0x02000000
444 {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c,
445 0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }},
446 {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f,
447 0x0000, 0x009E, /* 10baseT */
448 0x0004, 0x009E, /* 10baseT-FD */
449 0x0903, 0x006D, /* 100baseTx */
450 0x0905, 0x006D, /* 100baseTx-FD */ }},
451 {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f,
452 0x0107, 0x8021, /* 100baseFx */
453 0x0108, 0x8021, /* 100baseFx-FD */
454 0x0100, 0x009E, /* 10baseT */
455 0x0104, 0x009E, /* 10baseT-FD */
456 0x0103, 0x006D, /* 100baseTx */
457 0x0105, 0x006D, /* 100baseTx-FD */ }},
458 {"Maxtech NX-110", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x0513,
459 0x1001, 0x009E, /* 10base2, CSR12 0x10*/
460 0x0000, 0x009E, /* 10baseT */
461 0x0004, 0x009E, /* 10baseT-FD */
462 0x0303, 0x006D, /* 100baseTx, CSR12 0x03 */
463 0x0305, 0x006D, /* 100baseTx-FD CSR12 0x03 */}},
464 {"Accton EN1207", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x051F,
465 0x1B01, 0x0000, /* 10base2, CSR12 0x1B */
466 0x0B00, 0x009E, /* 10baseT, CSR12 0x0B */
467 0x0B04, 0x009E, /* 10baseT-FD,CSR12 0x0B */
468 0x1B03, 0x006D, /* 100baseTx, CSR12 0x1B */
469 0x1B05, 0x006D, /* 100baseTx-FD CSR12 0x1B */
471 {0, 0, 0, 0, {}}};
554 #define MDIO_SHIFT_CLK 0x10000
555 #define MDIO_DATA_WRITE0 0x00000
556 #define MDIO_DATA_WRITE1 0x20000
557 #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
558 #define MDIO_ENB_IN 0x40000
559 #define MDIO_DATA_READ 0x80000
569 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; in mdio_read()
570 int retval = 0; in mdio_read()
579 outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0); in mdio_read()
580 inl(ioaddr + 0xA0); in mdio_read()
581 inl(ioaddr + 0xA0); in mdio_read()
582 while (--i > 0) in mdio_read()
583 if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000)) in mdio_read()
584 return retval & 0xffff; in mdio_read()
585 return 0xffff; in mdio_read()
591 return inl(ioaddr + 0xB4 + (location<<2)); in mdio_read()
593 return inl(ioaddr + 0xD0); in mdio_read()
595 return inl(ioaddr + 0xD4 + ((location-29)<<2)); in mdio_read()
597 return 0xffff; in mdio_read()
601 for (i = 32; i >= 0; i--) { in mdio_read()
608 for (i = 15; i >= 0; i--) { in mdio_read()
609 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; in mdio_read()
617 for (i = 19; i > 0; i--) { in mdio_read()
620 retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); in mdio_read()
624 return (retval>>1) & 0xffff; in mdio_read()
630 int cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value; in mdio_write()
639 outl(cmd, ioaddr + 0xA0); in mdio_write()
641 if ( ! (inl(ioaddr + 0xA0) & 0x80000000)) in mdio_write()
643 while (--i > 0); in mdio_write()
651 outl(value, ioaddr + 0xB4 + (location<<2)); in mdio_write()
653 outl(value, ioaddr + 0xD0); in mdio_write()
655 outl(value, ioaddr + 0xD4 + ((location-29)<<2)); in mdio_write()
660 for (i = 32; i >= 0; i--) { in mdio_write()
667 for (i = 31; i >= 0; i--) { in mdio_write()
668 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; in mdio_write()
675 for (i = 2; i > 0; i--) { in mdio_write()
693 unsigned short retval = 0; in read_eeprom()
705 for (i = 4 + addr_len; i >= 0; i--) { in read_eeprom()
706 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; in read_eeprom()
714 for (i = 16; i > 0; i--) { in read_eeprom()
717 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); in read_eeprom()
733 int new_advertise = 0; in parse_eeprom()
740 tp->mtable = 0; in parse_eeprom()
743 for (i = 0; i < 8; i ++) in parse_eeprom()
748 for (i = 0; eeprom_fixups[i].name; i++) { in parse_eeprom()
749 if (nic->node_addr[0] == eeprom_fixups[i].addr0 in parse_eeprom()
752 if (nic->node_addr[2] == 0xE8 && ee_data[0x1a] == 0x55) in parse_eeprom()
781 if (ee_data[27] == 0) { /* No valid media table. */ in parse_eeprom()
795 media & 0x0800 ? "Autosense" : medianame[media & 15]); in parse_eeprom()
796 for (i = 0; i < count; i++) { in parse_eeprom()
799 if (media_block & 0x40) in parse_eeprom()
802 case 0: new_advertise |= 0x0020; break; in parse_eeprom()
803 case 4: new_advertise |= 0x0040; break; in parse_eeprom()
809 unsigned char csr12dir = 0; in parse_eeprom()
819 tp->mtable = mtable = (struct mediatable *)&tp->media_table_storage[0]; in parse_eeprom()
824 mtable->has_nonmii = mtable->has_mii = mtable->has_reset = 0; in parse_eeprom()
825 mtable->csr15dir = mtable->csr15val = 0; in parse_eeprom()
828 media & 0x0800 ? "Autosense" : medianame[media & MEDIA_MASK]); in parse_eeprom()
830 for (i = 0; i < count; i++) { in parse_eeprom()
833 if ((p[0] & 0x80) == 0) { /* 21140 Compact block. */ in parse_eeprom()
834 leaf->type = 0; in parse_eeprom()
835 leaf->media = p[0] & 0x3f; in parse_eeprom()
837 if ((p[2] & 0x61) == 0x01) /* Bogus, but Znyx boards do it. */ in parse_eeprom()
844 leaf->media = p[2] & 0x0f; in parse_eeprom()
851 if ((p[2] & 0x3f) == 0) { in parse_eeprom()
852 u32 base15 = (p[2] & 0x40) ? get_u16(p + 7) : 0x0008; in parse_eeprom()
853 u16 *p1 = (u16 *)(p + (p[2] & 0x40 ? 9 : 3)); in parse_eeprom()
854 mtable->csr15dir = (get_unaligned(p1 + 0)<<16) + base15; in parse_eeprom()
858 case 0: case 4: in parse_eeprom()
862 case 0: new_advertise |= 0x0020; break; in parse_eeprom()
863 case 4: new_advertise |= 0x0040; break; in parse_eeprom()
864 case 3: new_advertise |= 0x0080; break; in parse_eeprom()
865 case 5: new_advertise |= 0x0100; break; in parse_eeprom()
866 case 6: new_advertise |= 0x0200; break; in parse_eeprom()
873 p += (p[0] & 0x3f) + 1; in parse_eeprom()
879 tp->nic_name, bp[0], bp[1], bp[2 + bp[1]*2], in parse_eeprom()
905 tp->cur_rx = 0; in tulip_init_ring()
907 for (i = 0; i < RX_RING_SIZE; i++) { in tulip_init_ring()
908 rx_ring[i].status = cpu_to_le32(0x80000000); in tulip_init_ring()
915 rx_ring[i-1].buffer2 = virt_to_le32desc(&rx_ring[0]); in tulip_init_ring()
920 tx_ring[0].status = 0x00000000; in tulip_init_ring()
921 tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]); in tulip_init_ring()
922 tx_ring[0].buffer2 = virt_to_le32desc(&tx_ring[1]); in tulip_init_ring()
925 by the machine (status will always == 0) */ in tulip_init_ring()
926 tx_ring[1].status = 0x00000000; in tulip_init_ring()
927 tx_ring[1].buffer1 = virt_to_le32desc(&txb[0]); in tulip_init_ring()
928 tx_ring[1].buffer2 = virt_to_le32desc(&tx_ring[0]); in tulip_init_ring()
935 int csr6 = inl(ioaddr + CSR6) & ~0x00D5; in set_rx_mode()
937 tp->csr6 &= ~0x00D5; in set_rx_mode()
962 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); in tulip_reset()
966 outl(0x814C0000, ioaddr + CSR6); in tulip_reset()
969 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ in tulip_reset()
970 outl(0x00000001, ioaddr + CSR0); in tulip_reset()
983 u32 addr_high = (nic->node_addr[1]<<8) + (nic->node_addr[0]<<0); in tulip_reset()
987 ioaddr + 0xB0); in tulip_reset()
988 outl(addr_high + (addr_high<<16), ioaddr + 0xB8); in tulip_reset()
998 outl(0, ioaddr + CSR13); in tulip_reset()
1003 outl(0, ioaddr + CSR14); in tulip_reset()
1005 outl(0, ioaddr + CSR14); in tulip_reset()
1007 outl(addr_low, ioaddr + 0xA4); in tulip_reset()
1008 outl(addr_high, ioaddr + 0xA8); in tulip_reset()
1009 outl(0, ioaddr + 0xAC); in tulip_reset()
1010 outl(0, ioaddr + 0xB0); in tulip_reset()
1015 u32 tx_flags = 0x08000000 | 192; in tulip_reset()
1019 for (i=0; i<192; i++) in tulip_reset()
1020 txb[i] = 0xFF; in tulip_reset()
1021 txb[0] = nic->node_addr[0]; in tulip_reset()
1028 tx_ring[0].length = cpu_to_le32(tx_flags); in tulip_reset()
1029 tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]); in tulip_reset()
1030 tx_ring[0].status = cpu_to_le32(0x80000000); in tulip_reset()
1034 outl(virt_to_le32desc(&rx_ring[0]), ioaddr + CSR3); in tulip_reset()
1035 outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4); in tulip_reset()
1040 outl((tp->csr6 & ~0x00002002), ioaddr + CSR6); in tulip_reset()
1045 outl(tp->csr6 | 0x00002000, ioaddr + CSR6); in tulip_reset()
1047 outl(0, ioaddr + CSR1); in tulip_reset()
1050 while ((tx_ring[0].status & 0x80000000) && (currticks() < to)) in tulip_reset()
1064 outl(tp->csr6 | 0x00002002, ioaddr + CSR6); in tulip_reset()
1082 outl(csr6 & ~0x00002000, ioaddr + CSR6); in tulip_transmit()
1091 s &= 0x0FFF; in tulip_transmit()
1095 txb[s++] = '\0'; in tulip_transmit()
1103 /* 0x60000000 = no interrupt on completion */ in tulip_transmit()
1104 tx_ring[0].length = cpu_to_le32(0x60000000 | s); in tulip_transmit()
1105 tx_ring[0].status = cpu_to_le32(0x80000000); in tulip_transmit()
1108 outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4); in tulip_transmit()
1111 outl(csr6 | 0x00002000, ioaddr + CSR6); in tulip_transmit()
1113 outl(0, ioaddr + CSR1); in tulip_transmit()
1116 while ((tx_ring[0].status & 0x80000000) && (currticks() < to)) in tulip_transmit()
1124 outl(csr6 & ~0x00002000, ioaddr + CSR6); in tulip_transmit()
1138 if (rx_ring[tp->cur_rx].status & 0x80000000) in tulip_poll()
1139 return 0; in tulip_poll()
1147 nic->packetlen = (rx_ring[tp->cur_rx].status & 0x3FFF0000) >> 16; in tulip_poll()
1150 if (rx_ring[tp->cur_rx].status & 0x00008000) { in tulip_poll()
1152 rx_ring[tp->cur_rx].status = 0x80000000; in tulip_poll()
1154 return 0; in tulip_poll()
1161 rx_ring[tp->cur_rx].status = 0x80000000; in tulip_poll()
1181 outl(0x00000000, ioaddr + CSR7); in tulip_disable()
1184 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); in tulip_disable()
1216 static unsigned char last_phys_addr[ETH_ALEN] = {0x00, 'L', 'i', 'n', 'u', 'x'}; in tulip_probe()
1218 if (pci->ioaddr == 0) in tulip_probe()
1219 return 0; in tulip_probe()
1223 nic->irqno = 0; in tulip_probe()
1232 tp->if_port = 0; in tulip_probe()
1233 tp->default_port = 0; in tulip_probe()
1238 outl(0x00000000, ioaddr + CSR7); in tulip_probe()
1241 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); in tulip_probe()
1258 i = 0; in tulip_probe()
1273 return 0; in tulip_probe()
1291 pcibios_write_config_dword(pci->bus, pci->devfn, 0x40, 0x00000000); in tulip_probe()
1293 if (inl(ioaddr + CSR5) == 0xFFFFFFFF) { in tulip_probe()
1296 return 0; in tulip_probe()
1305 if (chip_idx == DC21041 && inl(ioaddr + CSR9) & 0x8000) { in tulip_probe()
1313 sum = 0; in tulip_probe()
1315 outl(0, ioaddr + CSR9); /* Reset the pointer with a dummy write. */ in tulip_probe()
1316 for (i = 0; i < ETH_ALEN; i++) { in tulip_probe()
1320 while (value < 0 && --boguscnt > 0); in tulip_probe()
1322 sum += value & 0xff; in tulip_probe()
1325 for (i = 0; i < 3; i++) { in tulip_probe()
1327 outl(0x600 | i, ioaddr + 0x98); in tulip_probe()
1330 while (value < 0 && --boguscnt > 0); in tulip_probe()
1332 sum += value & 0xffff; in tulip_probe()
1336 put_unaligned(inl(ioaddr + 0xA4), (u32 *)nic->node_addr); in tulip_probe()
1337 put_unaligned(inl(ioaddr + 0xA8), (u16 *)(nic->node_addr + 4)); in tulip_probe()
1338 for (i = 0; i < ETH_ALEN; i ++) in tulip_probe()
1342 int sa_offset = 0; in tulip_probe()
1343 int ee_addr_size = read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; in tulip_probe()
1345 for (i = 0; i < sizeof(ee_data)/2; i++) in tulip_probe()
1352 for (i = 0; i < 8; i ++) in tulip_probe()
1355 if (ee_data[0] == 0xff && ee_data[1] == 0xff && ee_data[2] == 0) { in tulip_probe()
1358 for (i = 0; i < ETH_ALEN; i ++) { in tulip_probe()
1364 if ((nic->node_addr[0] == 0xA0 || nic->node_addr[0] == 0xC0) in tulip_probe()
1365 && nic->node_addr[1] == 0x00) in tulip_probe()
1366 for (i = 0; i < ETH_ALEN; i+=2) { in tulip_probe()
1372 if (sum == 0 || sum == ETH_ALEN*0xff) { in tulip_probe()
1374 for (i = 0; i < ETH_ALEN-1; i++) in tulip_probe()
1379 for (i = 0; i < ETH_ALEN; i++) in tulip_probe()
1391 tp->csr0 &= ~0x01000000; in tulip_probe()
1393 tp->csr0 |= 0x2000; in tulip_probe()
1396 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 }; in tulip_probe()
1437 for (i = 0; i < tp->mtable->leafcount; i++) in start_link()
1448 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys); in start_link()
1451 if ((mii_status & 0x8301) == 0x8001 || in start_link()
1452 ((mii_status & 0x8000) == 0 && (mii_status & 0x7800) != 0)) { in start_link()
1453 int mii_reg0 = mdio_read(nic, phy, 0); in start_link()
1474 mdio_write(nic, phy, 0, mii_reg0 | in start_link()
1475 (tp->full_duplex ? 0x1100 : 0x1000) | in start_link()
1476 (media_cap[tp->default_port]&MediaIs100 ? 0x2000:0)); in start_link()
1480 if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) { in start_link()
1483 tp->phys[0] = 1; in start_link()
1490 outl(0x00000000, ioaddr + CSR13); in start_link()
1491 outl(0x00000004, ioaddr + CSR13); in start_link()
1495 if (tp->sym_advertise == 0) in start_link()
1496 tp->sym_advertise = 0x0061; in start_link()
1497 outl(0x00000000, ioaddr + CSR13); in start_link()
1498 outl(0xFFFFFFFF, ioaddr + CSR14); in start_link()
1499 outl(0x00000008, ioaddr + CSR15); /* Listen on AUI also. */ in start_link()
1500 outl(inl(ioaddr + CSR6) | 0x0200, ioaddr + CSR6); in start_link()
1501 outl(0x0000EF01, ioaddr + CSR13); in start_link()
1505 outl(tp->mtable->csr12dir | 0x100, ioaddr + CSR12); in start_link()
1510 outl(0x82020000, ioaddr + CSR6); in start_link()
1511 outl(0x0000, ioaddr + CSR13); in start_link()
1512 outl(0x0000, ioaddr + CSR14); in start_link()
1513 outl(0x820E0000, ioaddr + CSR6); in start_link()
1520 tp->nwayset = 0; in start_link()
1521 outl(0x00420000, ioaddr + CSR6); in start_link()
1522 outl(0x30, ioaddr + CSR12); in start_link()
1523 outl(0x0001F078, ioaddr + 0xB8); in start_link()
1524 outl(0x0201F078, ioaddr + 0xB8); /* Turn on autonegotiation. */ in start_link()
1528 outl(0x00000000, ioaddr + CSR6); in start_link()
1529 outl(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */ in start_link()
1530 outl(0x00000001, ioaddr + CSR13); in start_link()
1533 outl(0x01a80000, ioaddr + CSR6); in start_link()
1534 outl(0xFFFFFFFF, ioaddr + CSR14); in start_link()
1535 outl(0x00001000, ioaddr + CSR12); in start_link()
1545 int csr14 = ((tp->sym_advertise & 0x0780) << 9) | in nway_start()
1546 ((tp->sym_advertise&0x0020)<<1) | 0xffbf; in nway_start()
1552 tp->if_port = 0; in nway_start()
1554 tp->nwayset = tp->lpar = 0; in nway_start()
1556 tp->csr6 = 0x01000000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0); in nway_start()
1564 outl(0x0001, ioaddr + CSR13); in nway_start()
1566 tp->csr6 = 0x82420000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0); in nway_start()
1572 outw(0x0008, ioaddr + CSR15); in nway_start()
1574 outl(0xEF01, ioaddr + CSR12); in nway_start()
1576 outl(0x1301, ioaddr + CSR12); in nway_start()
1588 if (tp->if_port == 0) in init_media()
1592 i = 0; in init_media()
1597 (tp->if_port == 12 ? 0 : tp->if_port); in init_media()
1598 for (i = 0; i < tp->mtable->leafcount; i++) in init_media()
1605 if ((tp->mtable->defaultmedia & 0x0800) == 0) { in init_media()
1607 for (i = 0; i < tp->mtable->leafcount; i++) in init_media()
1616 (media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--) in init_media()
1620 tp->csr6 = 0; in init_media()
1622 tp->nwayset = 0; in init_media()
1627 outl(0x0000, ioaddr + CSR13); in init_media()
1628 outl(0x0000, ioaddr + CSR14); in init_media()
1629 outl(0x0008, ioaddr + CSR15); in init_media()
1645 tp->nic_name, tp->phys[0], mdio_read(nic, tp->phys[0], 1)); in init_media()
1647 outl(0x82020000, ioaddr + CSR6); in init_media()
1648 tp->csr6 = 0x820E0000; in init_media()
1650 outl(0x0000, ioaddr + CSR13); in init_media()
1651 outl(0x0000, ioaddr + CSR14); in init_media()
1661 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0); in init_media()
1662 outl(0x0001, ioaddr + CSR15); in init_media()
1667 outl(0x32, ioaddr + CSR12); in init_media()
1668 tp->csr6 = 0x00420000; in init_media()
1669 outl(0x0001B078, ioaddr + 0xB8); in init_media()
1670 outl(0x0201B078, ioaddr + 0xB8); in init_media()
1674 tp->if_port = 0; in init_media()
1675 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0); in init_media()
1676 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80); in init_media()
1680 tp->if_port = 0; in init_media()
1681 tp->csr6 = 0x01a80200; in init_media()
1682 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80); in init_media()
1683 outl(0x11000 | inw(ioaddr + 0xa0), ioaddr + 0xa0); in init_media()
1686 tp->if_port = 0; in init_media()
1687 tp->csr6 = 0x00040000; in init_media()
1690 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100; in init_media()
1699 u32 phy_reg = inl(ioaddr + 0xB8); in pnic_do_nway()
1700 u32 new_csr6 = tp->csr6 & ~0x40C40200; in pnic_do_nway()
1706 if (phy_reg & 0x78000000) { /* Ignore baseT4 */ in pnic_do_nway()
1707 if (phy_reg & 0x20000000) tp->if_port = 5; in pnic_do_nway()
1708 else if (phy_reg & 0x40000000) tp->if_port = 3; in pnic_do_nway()
1709 else if (phy_reg & 0x10000000) tp->if_port = 4; in pnic_do_nway()
1710 else if (phy_reg & 0x08000000) tp->if_port = 0; in pnic_do_nway()
1712 new_csr6 = (tp->if_port & 1) ? 0x01860000 : 0x00420000; in pnic_do_nway()
1713 outl(0x32 | (tp->if_port & 1), ioaddr + CSR12); in pnic_do_nway()
1715 outl(0x1F868, ioaddr + 0xB8); in pnic_do_nway()
1716 if (phy_reg & 0x30000000) { in pnic_do_nway()
1718 new_csr6 |= 0x00000200; in pnic_do_nway()
1727 outl(tp->csr6 | 0x0002, ioaddr + CSR6); /* Restart Tx */ in pnic_do_nway()
1728 outl(tp->csr6 | 0x2002, ioaddr + CSR6); in pnic_do_nway()
1748 case 0: /* 21140 non-MII xcvr. */ in select_media()
1755 tp->if_port = p[0]; in select_media()
1757 outl(mtable->csr12dir | 0x100, ioaddr + CSR12); in select_media()
1759 new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18); in select_media()
1764 for (i = 0; i < 5; i++) in select_media()
1767 tp->if_port = p[0] & 15; in select_media()
1779 for (i = 0; i < rst[0]; i++) in select_media()
1786 tp->nic_name, medianame[tp->if_port], setup[0], setup[1]); in select_media()
1788 if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */ in select_media()
1789 csr13val = setup[0]; in select_media()
1793 outl(0, ioaddr + CSR13); in select_media()
1800 csr14val = 0x0003FF7F; in select_media()
1801 csr15dir = (setup[0]<<16) | 0x0008; in select_media()
1802 csr15val = (setup[1]<<16) | 0x0008; in select_media()
1806 outl(0, ioaddr + CSR13); in select_media()
1819 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18); in select_media()
1821 new_csr6 = 0x82420000; in select_media()
1825 int phy_num = p[0]; in select_media()
1830 new_csr6 = 0x020E0000; in select_media()
1837 for (i = 0; i < reset_length; i++) in select_media()
1839 for (i = 0; i < init_length; i++) in select_media()
1847 outl(mtable->csr12dir | 0x100, ioaddr + CSR12); in select_media()
1848 for (i = 0; i < reset_length; i++) in select_media()
1851 for (i = 0; i < init_length; i++) in select_media()
1856 if (tp->mii_advertise == 0) in select_media()
1870 new_csr6 = 0x020E0000; in select_media()
1876 inl(ioaddr + CSR12) & 0xff); in select_media()
1879 int port = tp->if_port <= 4 ? tp->if_port : 0; in select_media()
1886 outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */ in select_media()
1890 new_csr6 = 0x80020000; in select_media()
1893 tp->if_port = tp->mii_cnt ? 11 : 0; in select_media()
1897 tp->nic_name, inl(ioaddr + 0xB8), medianame[tp->if_port]); in select_media()
1900 new_csr6 = 0x810C0000; in select_media()
1901 outl(0x0001, ioaddr + CSR15); in select_media()
1902 outl(0x0201B07A, ioaddr + 0xB8); in select_media()
1905 outl(0x32, ioaddr + CSR12); in select_media()
1906 new_csr6 = 0x00420000; in select_media()
1907 outl(0x0001B078, ioaddr + 0xB8); in select_media()
1908 outl(0x0201B078, ioaddr + 0xB8); in select_media()
1910 outl(0x33, ioaddr + CSR12); in select_media()
1911 new_csr6 = 0x01860000; in select_media()
1913 outl(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8); in select_media()
1915 outl(0x32, ioaddr + CSR12); in select_media()
1916 new_csr6 = 0x00420000; in select_media()
1917 outl(0x1F078, ioaddr + 0xB8); in select_media()
1929 new_csr6 = 0x20000; in select_media()
1932 outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */ in select_media()
1934 outl(0x0705, ioaddr + CSR14); in select_media()
1935 outl(0x0006, ioaddr + CSR15); in select_media()
1937 outl(0xffff, ioaddr + CSR14); in select_media()
1938 outl(0x0000, ioaddr + CSR15); in select_media()
1940 outl(0x8f01 | t21040_csr13[tp->if_port], ioaddr + CSR13); in select_media()
1942 if (tp->default_port == 0) in select_media()
1945 new_csr6 = 0x020E0000; in select_media()
1947 new_csr6 = 0x028600000; in select_media()
1949 new_csr6 = 0x038600000; in select_media()
1959 tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0); in select_media()
1966 Return 0 if everything is OK.
1967 Return < 0 if the transceiver is missing or has no link beat.
1973 bmsr = mdio_read(nic, tp->phys[0], 1); in tulip_check_duplex()
1974 lpa = mdio_read(nic, tp->phys[0], 5); in tulip_check_duplex()
1982 if (bmsr == 0xffff) in tulip_check_duplex()
1984 if ((bmsr & 4) == 0) { in tulip_check_duplex()
1985 int new_bmsr = mdio_read(nic, tp->phys[0], 1); in tulip_check_duplex()
1986 if ((new_bmsr & 4) == 0) { in tulip_check_duplex()
1996 tp->full_duplex = lpa & 0x140; in tulip_check_duplex()
1999 negotiated = lpa & tp->advertising[0]; in tulip_check_duplex()
2001 if(negotiated & 0x380) new_csr6 &= ~0x400000; in tulip_check_duplex()
2002 else new_csr6 |= 0x400000; in tulip_check_duplex()
2003 if (tp->full_duplex) new_csr6 |= 0x200; in tulip_check_duplex()
2004 else new_csr6 &= ~0x200; in tulip_check_duplex()
2010 if (tulip_debug > 0) in tulip_check_duplex()
2015 tp->phys[0], lpa); in tulip_check_duplex()
2020 return 0; in tulip_check_duplex()
2024 PCI_ROM(0x1011, 0x0002, "dc21040", "Digital Tulip"),
2025 PCI_ROM(0x1011, 0x0009, "ds21140", "Digital Tulip Fast"),
2026 PCI_ROM(0x1011, 0x0014, "dc21041", "Digital Tulip+"),
2027 PCI_ROM(0x1011, 0x0019, "ds21142", "Digital Tulip 21142"),
2028 PCI_ROM(0x10b7, 0x9300, "3csoho100b-tx","3ComSOHO100B-TX"),
2029 PCI_ROM(0x10b9, 0x5261, "ali1563", "ALi 1563 integrated ethernet"),
2030 PCI_ROM(0x10d9, 0x0512, "mx98713", "Macronix MX987x3"),
2031 PCI_ROM(0x10d9, 0x0531, "mx98715", "Macronix MX987x5"),
2032 PCI_ROM(0x1113, 0x1217, "mxic-98715", "Macronix MX987x5"),
2033 PCI_ROM(0x11ad, 0xc115, "lc82c115", "LinkSys LNE100TX"),
2034 PCI_ROM(0x11ad, 0x0002, "82c168", "Netgear FA310TX"),
2035 PCI_ROM(0x1282, 0x9100, "dm9100", "Davicom 9100"),
2036 PCI_ROM(0x1282, 0x9102, "dm9102", "Davicom 9102"),
2037 PCI_ROM(0x1282, 0x9009, "dm9009", "Davicom 9009"),
2038 PCI_ROM(0x1282, 0x9132, "dm9132", "Davicom 9132"),
2039 PCI_ROM(0x1317, 0x0985, "centaur-p", "ADMtek Centaur-P"),
2040 PCI_ROM(0x1317, 0x0981, "an981", "ADMtek AN981 Comet"), /* ADMTek Centaur-P (stmicro) */
2041 PCI_ROM(0x1113, 0x1216, "an983", "ADMTek AN983 Comet"),
2042 PCI_ROM(0x1317, 0x9511, "an983b", "ADMTek Comet 983b"),
2043 PCI_ROM(0x1317, 0x1985, "centaur-c", "ADMTek Centaur-C"),
2044 PCI_ROM(0x8086, 0x0039, "intel21145", "Intel Tulip"),
2045 PCI_ROM(0x125b, 0x1400, "ax88140", "ASIX AX88140"),
2046 PCI_ROM(0x11f6, 0x9881, "rl100tx", "Compex RL100-TX"),
2047 PCI_ROM(0x115d, 0x0003, "xircomtulip", "Xircom Tulip"),
2048 PCI_ROM(0x104a, 0x0981, "tulip-0981", "Tulip 0x104a 0x0981"),
2049 PCI_ROM(0x104a, 0x2774, "tulip-2774", "Tulip 0x104a 0x2774"),
2050 PCI_ROM(0x1113, 0x9511, "tulip-9511", "Tulip 0x1113 0x9511"),
2051 PCI_ROM(0x1186, 0x1561, "tulip-1561", "Tulip 0x1186 0x1561"),
2052 PCI_ROM(0x1259, 0xa120, "tulip-a120", "Tulip 0x1259 0xa120"),
2053 PCI_ROM(0x13d1, 0xab02, "tulip-ab02", "Tulip 0x13d1 0xab02"),
2054 PCI_ROM(0x13d1, 0xab03, "tulip-ab03", "Tulip 0x13d1 0xab03"),
2055 PCI_ROM(0x13d1, 0xab08, "tulip-ab08", "Tulip 0x13d1 0xab08"),
2056 PCI_ROM(0x14f1, 0x1803, "lanfinity", "Conexant LANfinity"),
2057 PCI_ROM(0x1626, 0x8410, "tulip-8410", "Tulip 0x1626 0x8410"),
2058 PCI_ROM(0x1737, 0xab08, "tulip-1737-ab08","Tulip 0x1737 0xab08"),
2059 PCI_ROM(0x1737, 0xab09, "tulip-ab09", "Tulip 0x1737 0xab09"),
2067 .id_count = sizeof(tulip_nics)/sizeof(tulip_nics[0]),
2068 .class = 0,