108 #define tr32(reg)		readl(tg3.regs + (reg))  macro
115 	tr32(reg);  in tw32_carefully()
122 	tr32(reg);  in tw32_mailbox2()
154 	clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);  in tg3_switch_clocks()
192 		frame_val = tr32(MAC_MI_COM);  in tg3_readphy()
196 			frame_val = tr32(MAC_MI_COM);  in tg3_readphy()
231 		frame_val = tr32(MAC_MI_COM);  in tg3_writephy()
234 			frame_val = tr32(MAC_MI_COM);  in tg3_writephy()
971 	if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {  in tg3_fiber_aneg_smachine()
972 		rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);  in tg3_fiber_aneg_smachine()
1216 	    (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {  in tg3_setup_fiber_phy()
1257 	if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {  in tg3_setup_fiber_phy()
1312 				if ((tr32(MAC_STATUS) &  in tg3_setup_fiber_phy()
1318 			    (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {  in tg3_setup_fiber_phy()
1338 		if ((tr32(MAC_STATUS) &  in tg3_setup_fiber_phy()
1344 	if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)  in tg3_setup_fiber_phy()
1368 	if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {  in tg3_setup_fiber_phy()
1432 	val = tr32(ofs);  in tg3_stop_block()
1435 	tr32(ofs);  in tg3_stop_block()
1439 		val = tr32(ofs);  in tg3_stop_block()
1486 		if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))  in tg3_abort_hw()
1491 			tr32(MAC_TX_MODE));  in tg3_abort_hw()
1527 				if (tr32(NVRAM_SWARB) & SWARB_GNT1)  in tg3_chip_reset()
1589 		val = tr32(GRC_RX_CPU_EVENT);  in tg3_stop_fw()
1595 			if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))  in tg3_stop_fw()
1794 		val = tr32(TG3PCI_PCISTATE);  in tg3_setup_hw()
1869 		if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)  in tg3_setup_hw()
1881 		if (tr32(FTQ_RESET) == 0x00000000)  in tg3_setup_hw()
2002 			if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&  in tg3_setup_hw()
2012 		if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))  in tg3_setup_hw()
2028 	tr32(MAILBOX_INTERRUPT_0);  in tg3_setup_hw()
2040 		((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&  in tg3_setup_hw()
2047 		val = tr32(TG3PCI_X_CAPS);  in tg3_setup_hw()
2169 	tr32(MAC_LOW_WMARK_MAX_RX_FRAME);  in tg3_setup_hw()
2225 		tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);  in tg3_nvram_init()
2229 		uint32_t nvcfg1 = tr32(NVRAM_CFG1);  in tg3_nvram_init()
2257 	tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |  in tg3_nvram_read_using_eeprom()
2268 		tmp = tr32(GRC_EEPROM_ADDR);  in tg3_nvram_read_using_eeprom()
2278 	*val = tr32(GRC_EEPROM_DATA);  in tg3_nvram_read_using_eeprom()
2299 		if (tr32(NVRAM_SWARB) & SWARB_GNT1)  in tg3_nvram_read()
2314 		    !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))  in tg3_nvram_read()
2317 			 (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))  in tg3_nvram_read()
2325 	*val = bswap_32(tr32(NVRAM_RDDATA));  in tg3_nvram_read()
2764 	grc_misc_cfg = tr32(GRC_MISC_CFG);  in tg3_get_invariants()
2845 		hi = tr32(MAC_ADDR_0_HIGH);  in tg3_get_device_address()
2846 		lo = tr32(MAC_ADDR_0_LOW);  in tg3_get_device_address()
2893 			uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;  in tg3_setup_dma()
2950 	mac_stat = tr32(MAC_STATUS);  in tg3_poll_link()
2987 		tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);  in tg3_ack_irqs()