Lines Matching +full:queue +full:- +full:pkt +full:- +full:tx
30 LAN0 = 0x40, /* MAC address. (0x40-0x48) */
32 MC0 = 0x50, /* Multicast filter table. (0x50-0x5c) */
57 #define INTR_TX_IN_PROG (0x00100000) /* tx copy in progess. NI */
59 #define INTR_TXIDLE (0x00040000) /* tx idle. NI */
69 #define INTR_TXUNDERRUN (0x00000100) /* tx underrun. */
70 #define INTR_TXEMPTY (0x00000080) /* tx queue empty */
71 #define INTR_TX_CH_COMPLETE (0x00000040) /* tx chain complete */
72 #define INTR_TXDONE (0x00000020) /* tx complete (w or w/o err) */
75 #define INTR_RX_QUEUE_EMPTY (0x00000004) /* rx queue empty. */
99 * begins to empty the receive FIFO. Possible values: 0-3
164 /* description of tx descriptors status bits */
165 #define TRING_PKT_INTACT (0x0001) /* pkt transmitted. */
166 #define TRING_PKT_NONDEFER (0x0002) /* pkt xmitted w/o deferring */
167 #define TRING_COLL (0x0004) /* pkt xmitted w collisions */
174 #define TRING_COLL_EXCESS (0x1000) /* tx aborted: excessive colls */
181 /* description of the tx descriptors control bits */
184 #define TD_IAF (0x0004) /* Generate Interrupt after tx */