Lines Matching full:rx
386 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
582 #define E1000_RCTL 0x00100 /* RX Control - RW */
585 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
594 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
595 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
596 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
597 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
598 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
599 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
600 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
601 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
602 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
633 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
635 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
637 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
638 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
639 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
640 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
641 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
642 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
643 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
644 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
645 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
646 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
648 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
649 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
652 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
653 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
654 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
655 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
656 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
657 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
660 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
661 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
664 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
676 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
990 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1160 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1161 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1162 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1163 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1165 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1177 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1178 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1179 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1180 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1182 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1194 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1195 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1196 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1197 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1199 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1211 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1212 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1213 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1214 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1216 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1235 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1236 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1237 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1246 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1247 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1248 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1249 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1251 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1252 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1253 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1537 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1597 * status = the 8 bit status field of the RX descriptor with EOP set
1598 * error = the 8 bit error field of the RX descriptor with EOP set
1599 * length = the sum of all the length fields of the RX descriptors that
1606 * handler's Rx processing routine when RxErrors have been detected.
1773 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1872 * (Lower 10BASE-T RX Threshold)
1873 * 0=Normal 10BASE-T RX Threshold */