Lines Matching +full:mode +full:- +full:capable
4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
291 /* MAC decode size is 128K - This is the size of BAR0 */
309 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
311 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
355 * E1000_RAR_ENTRIES - 1 multicast addresses.
379 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
559 * RW - register is both readable and writable
560 * RO - register is read only
561 * WO - register is write only
562 * R/clr - register is read only and is cleared when read
563 * A - register array
565 #define E1000_CTRL 0x00000 /* Device Control - RW */
566 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
567 #define E1000_STATUS 0x00008 /* Device Status - RO */
568 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
569 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
570 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
571 #define E1000_FLA 0x0001C /* Flash Access - RW */
572 #define E1000_MDIC 0x00020 /* MDI Control - RW */
573 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
574 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
575 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
576 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
577 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
578 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
579 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
580 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
581 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
582 #define E1000_RCTL 0x00100 /* RX Control - RW */
583 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
584 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
585 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
586 #define E1000_TCTL 0x00400 /* TX Control - RW */
587 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
588 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
589 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
590 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
591 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
592 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
593 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
594 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
595 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
596 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
597 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
598 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
599 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
600 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
601 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
602 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
603 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
604 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
605 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
606 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
607 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
608 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
609 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
610 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
611 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
612 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
613 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
614 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
615 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
616 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
617 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
618 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
619 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
620 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
621 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
622 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
623 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
624 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
625 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
626 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
627 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
628 #define E1000_DC 0x04030 /* Defer Count - R/clr */
629 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
630 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
631 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
632 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
633 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
634 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
635 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
636 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
637 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
638 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
639 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
640 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
641 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
642 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
643 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
644 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
645 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
646 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
647 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
648 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
649 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
650 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
651 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
652 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
653 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
654 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
655 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
656 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
657 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
658 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
659 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
660 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
661 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
662 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
663 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
664 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
665 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
666 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
667 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
668 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
669 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
670 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
671 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
672 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
673 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
674 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
675 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
676 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
677 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
678 #define E1000_RA 0x05400 /* Receive Address - RW Array */
679 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
680 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
681 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
682 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
683 #define E1000_MANC 0x05820 /* Management Control - RW */
684 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
685 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
686 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
687 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
688 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
689 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
690 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
691 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
989 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
992 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
994 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
996 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1001 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1016 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1026 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1035 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1036 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1038 /* Constants used to intrepret the masked PCI-X bus speed. */
1039 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1040 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1041 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1057 * (0-small, 1-large) */
1058 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1231 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1232 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1233 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1234 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1298 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1307 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1318 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1319 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1368 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1369 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1370 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1397 /* EEPROM Commands - Microwire */
1404 /* EEPROM Commands - SPI */
1408 #define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */
1585 /* Number of milliseconds we wait for auto-negotiation to complete */
1613 * frame_length--;
1621 ((adapter)->tbi_compatibility_on && \
1625 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1626 ((length) <= ((adapter)->max_frame_size + 1))) : \
1627 (((length) > (adapter)->min_frame_size) && \
1628 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1656 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1657 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1687 /* IGP01E1000 AGC Registers - stores the cable length values*/
1713 /* IGP01E1000 PCS Initialization register - stores the polarity status when
1720 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1738 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1743 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1744 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1745 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1746 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1747 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1748 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1749 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1753 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1754 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1755 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1756 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1757 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1765 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1766 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1767 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1768 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1769 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1778 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1779 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1780 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1781 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1810 /* 1000BASE-T Control Register */
1826 /* 1000BASE-T Status Register */
1829 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1830 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1842 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
1843 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
1844 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
1845 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
1860 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1863 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1864 * 100BASE-TX/10BASE-T:
1865 * MDI Mode
1871 /* 1=Enable Extended 10BASE-T distance
1872 * (Lower 10BASE-T RX Threshold)
1873 * 0=Normal 10BASE-T RX Threshold */
1875 /* 1=5-Bit interface in 100BASE-TX
1876 * 0=MII interface in 100BASE-TX */
1890 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1891 * 3=110-140M;4=>140M */
1911 * within 1ms in 1000BASE-T
1931 /* IGP01E1000 Specific Port Config Register - R/W */
1939 /* IGP01E1000 Specific Port Status Register - R/O */
1953 /* IGP01E1000 Specific Port Control Register - R/W */
1959 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
1988 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
1990 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
1993 /* The precision of the length is +/- 10 meters */
2002 * on Link-Up */
2054 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */