Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
2 Etherboot - BOOTP/TFTP Bootstrap Program
4 Drivers are port from Intel's Linux driver e1000-4.3.15
10 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
24 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
71 * Some member variables of the hw struct have been eliminated
88 static struct e1000_hw hw; variable
100 static int e1000_setup_link(struct e1000_hw *hw);
101 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
102 static int e1000_setup_copper_link(struct e1000_hw *hw);
103 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
104 static void e1000_config_collision_dist(struct e1000_hw *hw);
105 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
106 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
107 static int e1000_check_for_link(struct e1000_hw *hw);
108 static int e1000_wait_autoneg(struct e1000_hw *hw);
109 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
111 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
113 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
114 static void e1000_phy_hw_reset(struct e1000_hw *hw);
115 static int e1000_phy_reset(struct e1000_hw *hw);
116 static int e1000_detect_gig_phy(struct e1000_hw *hw);
149 ((a)->mac_type >= e1000_82543) ? \
150 (writel((value), ((a)->hw_addr + E1000_##reg))) : \
151 (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
154 ((a)->mac_type >= e1000_82543) ? \
155 readl((a)->hw_addr + E1000_##reg) : \
156 readl((a)->hw_addr + E1000_82542_##reg))
159 ((a)->mac_type >= e1000_82543) ? \
160 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
161 writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
164 ((a)->mac_type >= e1000_82543) ? \
165 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
166 readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
171 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port) in e1000_io_read()
177 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value) in e1000_io_write()
182 static inline void e1000_pci_set_mwi(struct e1000_hw *hw) in e1000_pci_set_mwi() argument
184 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_pci_set_mwi()
187 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw) in e1000_pci_clear_mwi() argument
189 pci_write_config_word(hw->pdev, PCI_COMMAND, in e1000_pci_clear_mwi()
190 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); in e1000_pci_clear_mwi()
196 * hw - Struct containing variables accessed by shared code
197 * eecd - EECD's current value
200 e1000_raise_ee_clk(struct e1000_hw *hw, in e1000_raise_ee_clk() argument
207 E1000_WRITE_REG(hw, EECD, *eecd); in e1000_raise_ee_clk()
208 E1000_WRITE_FLUSH(hw); in e1000_raise_ee_clk()
209 udelay(hw->eeprom.delay_usec); in e1000_raise_ee_clk()
215 * hw - Struct containing variables accessed by shared code
216 * eecd - EECD's current value
219 e1000_lower_ee_clk(struct e1000_hw *hw, in e1000_lower_ee_clk() argument
226 E1000_WRITE_REG(hw, EECD, *eecd); in e1000_lower_ee_clk()
227 E1000_WRITE_FLUSH(hw); in e1000_lower_ee_clk()
228 udelay(hw->eeprom.delay_usec); in e1000_lower_ee_clk()
234 * hw - Struct containing variables accessed by shared code
235 * data - data to send to the EEPROM
236 * count - number of bits to shift out
239 e1000_shift_out_ee_bits(struct e1000_hw *hw, in e1000_shift_out_ee_bits() argument
243 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_shift_out_ee_bits()
251 mask = 0x01 << (count - 1); in e1000_shift_out_ee_bits()
252 eecd = E1000_READ_REG(hw, EECD); in e1000_shift_out_ee_bits()
253 if (eeprom->type == e1000_eeprom_microwire) { in e1000_shift_out_ee_bits()
255 } else if (eeprom->type == e1000_eeprom_spi) { in e1000_shift_out_ee_bits()
269 E1000_WRITE_REG(hw, EECD, eecd); in e1000_shift_out_ee_bits()
270 E1000_WRITE_FLUSH(hw); in e1000_shift_out_ee_bits()
272 udelay(eeprom->delay_usec); in e1000_shift_out_ee_bits()
274 e1000_raise_ee_clk(hw, &eecd); in e1000_shift_out_ee_bits()
275 e1000_lower_ee_clk(hw, &eecd); in e1000_shift_out_ee_bits()
283 E1000_WRITE_REG(hw, EECD, eecd); in e1000_shift_out_ee_bits()
289 * hw - Struct containing variables accessed by shared code
292 e1000_shift_in_ee_bits(struct e1000_hw *hw, in e1000_shift_in_ee_bits() argument
306 eecd = E1000_READ_REG(hw, EECD); in e1000_shift_in_ee_bits()
313 e1000_raise_ee_clk(hw, &eecd); in e1000_shift_in_ee_bits()
315 eecd = E1000_READ_REG(hw, EECD); in e1000_shift_in_ee_bits()
321 e1000_lower_ee_clk(hw, &eecd); in e1000_shift_in_ee_bits()
330 * hw - Struct containing variables accessed by shared code
336 e1000_acquire_eeprom(struct e1000_hw *hw) in e1000_acquire_eeprom() argument
338 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_acquire_eeprom()
341 eecd = E1000_READ_REG(hw, EECD); in e1000_acquire_eeprom()
344 if(hw->mac_type > e1000_82544) { in e1000_acquire_eeprom()
346 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
347 eecd = E1000_READ_REG(hw, EECD); in e1000_acquire_eeprom()
352 eecd = E1000_READ_REG(hw, EECD); in e1000_acquire_eeprom()
356 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
358 return -E1000_ERR_EEPROM; in e1000_acquire_eeprom()
364 if (eeprom->type == e1000_eeprom_microwire) { in e1000_acquire_eeprom()
367 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
371 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
372 } else if (eeprom->type == e1000_eeprom_spi) { in e1000_acquire_eeprom()
375 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
385 * hw - Struct containing variables accessed by shared code
388 e1000_standby_eeprom(struct e1000_hw *hw) in e1000_standby_eeprom() argument
390 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_standby_eeprom()
393 eecd = E1000_READ_REG(hw, EECD); in e1000_standby_eeprom()
395 if(eeprom->type == e1000_eeprom_microwire) { in e1000_standby_eeprom()
399 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
400 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
401 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
405 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
406 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
407 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
411 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
412 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
413 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
417 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
418 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
419 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
420 } else if(eeprom->type == e1000_eeprom_spi) { in e1000_standby_eeprom()
423 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
424 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
425 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
427 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
428 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
429 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
436 * hw - Struct containing variables accessed by shared code
439 e1000_release_eeprom(struct e1000_hw *hw) in e1000_release_eeprom() argument
443 eecd = E1000_READ_REG(hw, EECD); in e1000_release_eeprom()
445 if (hw->eeprom.type == e1000_eeprom_spi) { in e1000_release_eeprom()
449 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
451 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
452 } else if(hw->eeprom.type == e1000_eeprom_microwire) { in e1000_release_eeprom()
455 /* CS on Microwire is active-high */ in e1000_release_eeprom()
458 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
462 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
463 E1000_WRITE_FLUSH(hw); in e1000_release_eeprom()
464 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
468 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
469 E1000_WRITE_FLUSH(hw); in e1000_release_eeprom()
470 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
474 if(hw->mac_type > e1000_82544) { in e1000_release_eeprom()
476 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
483 * hw - Struct containing variables accessed by shared code
486 e1000_spi_eeprom_ready(struct e1000_hw *hw) in e1000_spi_eeprom_ready() argument
498 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, in e1000_spi_eeprom_ready()
499 hw->eeprom.opcode_bits); in e1000_spi_eeprom_ready()
500 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); in e1000_spi_eeprom_ready()
509 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and in e1000_spi_eeprom_ready()
510 * only 0-5mSec on 5V devices) in e1000_spi_eeprom_ready()
514 return -E1000_ERR_EEPROM; in e1000_spi_eeprom_ready()
523 * hw - Struct containing variables accessed by shared code
524 * offset - offset of word in the EEPROM to read
525 * data - word read from the EEPROM
526 * words - number of words to read
529 e1000_read_eeprom(struct e1000_hw *hw, in e1000_read_eeprom() argument
534 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_read_eeprom()
542 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) || in e1000_read_eeprom()
545 return -E1000_ERR_EEPROM; in e1000_read_eeprom()
549 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) in e1000_read_eeprom()
550 return -E1000_ERR_EEPROM; in e1000_read_eeprom()
552 if(eeprom->type == e1000_eeprom_spi) { in e1000_read_eeprom()
556 if(e1000_spi_eeprom_ready(hw)) { in e1000_read_eeprom()
557 e1000_release_eeprom(hw); in e1000_read_eeprom()
558 return -E1000_ERR_EEPROM; in e1000_read_eeprom()
561 e1000_standby_eeprom(hw); in e1000_read_eeprom()
564 if((eeprom->address_bits == 8) && (offset >= 128)) in e1000_read_eeprom()
568 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); in e1000_read_eeprom()
569 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); in e1000_read_eeprom()
573 * and tear-down. The address counter will roll over if reading beyond in e1000_read_eeprom()
577 word_in = e1000_shift_in_ee_bits(hw, 16); in e1000_read_eeprom()
580 } else if(eeprom->type == e1000_eeprom_microwire) { in e1000_read_eeprom()
583 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, in e1000_read_eeprom()
584 eeprom->opcode_bits); in e1000_read_eeprom()
585 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), in e1000_read_eeprom()
586 eeprom->address_bits); in e1000_read_eeprom()
589 * of eeprom setup and tear-down. */ in e1000_read_eeprom()
590 data[i] = e1000_shift_in_ee_bits(hw, 16); in e1000_read_eeprom()
591 e1000_standby_eeprom(hw); in e1000_read_eeprom()
596 e1000_release_eeprom(hw); in e1000_read_eeprom()
604 * hw - Struct containing variables accessed by shared code
611 e1000_validate_eeprom_checksum(struct e1000_hw *hw) in e1000_validate_eeprom_checksum() argument
619 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { in e1000_validate_eeprom_checksum()
621 return -E1000_ERR_EEPROM; in e1000_validate_eeprom_checksum()
630 return -E1000_ERR_EEPROM; in e1000_validate_eeprom_checksum()
638 * hw - Struct containing variables accessed by shared code
641 e1000_read_mac_addr(struct e1000_hw *hw) in e1000_read_mac_addr() argument
651 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { in e1000_read_mac_addr()
653 return -E1000_ERR_EEPROM; in e1000_read_mac_addr()
655 hw->mac_addr[i] = eeprom_data & 0xff; in e1000_read_mac_addr()
656 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff; in e1000_read_mac_addr()
658 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) && in e1000_read_mac_addr()
659 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) in e1000_read_mac_addr()
661 hw->mac_addr[5] ^= 1; in e1000_read_mac_addr()
668 * hw - Struct containing variables accessed by shared code
675 e1000_init_rx_addrs(struct e1000_hw *hw) in e1000_init_rx_addrs() argument
685 addr_low = (hw->mac_addr[0] | in e1000_init_rx_addrs()
686 (hw->mac_addr[1] << 8) | in e1000_init_rx_addrs()
687 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24)); in e1000_init_rx_addrs()
689 addr_high = (hw->mac_addr[4] | in e1000_init_rx_addrs()
690 (hw->mac_addr[5] << 8) | E1000_RAH_AV); in e1000_init_rx_addrs()
692 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); in e1000_init_rx_addrs()
693 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); in e1000_init_rx_addrs()
696 DEBUGOUT("Clearing RAR[1-15]\n"); in e1000_init_rx_addrs()
698 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); in e1000_init_rx_addrs()
699 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); in e1000_init_rx_addrs()
706 * hw - Struct containing variables accessed by shared code
709 e1000_clear_vfta(struct e1000_hw *hw) in e1000_clear_vfta() argument
714 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); in e1000_clear_vfta()
720 * hw - Struct containing variables accessed by shared code
721 * offset - offset to write to * value - value to write
723 void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){ in e1000_write_reg_io() argument
724 uint32_t io_addr = hw->io_base; in e1000_write_reg_io()
725 uint32_t io_data = hw->io_base + 4; in e1000_write_reg_io()
726 e1000_io_write(hw, io_addr, offset); in e1000_write_reg_io()
727 e1000_io_write(hw, io_data, value); in e1000_write_reg_io()
731 * Set the phy type member in the hw struct.
733 * hw - Struct containing variables accessed by shared code
736 e1000_set_phy_type(struct e1000_hw *hw) in e1000_set_phy_type() argument
740 switch(hw->phy_id) { in e1000_set_phy_type()
744 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
747 hw->phy_type = e1000_phy_igp; in e1000_set_phy_type()
751 hw->phy_type = e1000_phy_undefined; in e1000_set_phy_type()
752 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
759 * IGP phy init script - initializes the GbE PHY
761 * hw - Struct containing variables accessed by shared code
764 e1000_phy_init_script(struct e1000_hw *hw) argument
770 if(hw->phy_init_script) {
772 if((hw->mac_type == e1000_82541) ||
773 (hw->mac_type == e1000_82547) ||
774 (hw->mac_type == e1000_82541_rev_2) ||
775 (hw->mac_type == e1000_82547_rev_2)) {
779 e1000_write_phy_reg(hw,0x0000,0x0140);
783 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
784 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
786 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
788 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
790 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
792 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
794 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
796 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
798 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
800 e1000_write_phy_reg(hw, 0x2010, 0x0008);
802 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
805 e1000_write_phy_reg(hw, 0x0000, 0x3300);
808 if(hw->mac_type == e1000_82547) {
812 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
815 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
821 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
822 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
824 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
830 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
831 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
839 * Set the mac type member in the hw struct.
841 * hw - Struct containing variables accessed by shared code
844 e1000_set_mac_type(struct e1000_hw *hw) argument
848 switch (hw->device_id) {
850 switch (hw->revision_id) {
852 hw->mac_type = e1000_82542_rev2_0;
855 hw->mac_type = e1000_82542_rev2_1;
859 return -E1000_ERR_MAC_TYPE;
864 hw->mac_type = e1000_82543;
870 hw->mac_type = e1000_82544;
877 hw->mac_type = e1000_82540;
881 hw->mac_type = e1000_82545;
886 hw->mac_type = e1000_82545_rev_3;
891 hw->mac_type = e1000_82546;
896 hw->mac_type = e1000_82546_rev_3;
900 hw->mac_type = e1000_82541;
905 hw->mac_type = e1000_82541_rev_2;
908 hw->mac_type = e1000_82547;
911 hw->mac_type = e1000_82547_rev_2;
915 return -E1000_ERR_MAC_TYPE;
924 * hw - Struct containing variables accessed by shared code
927 e1000_set_media_type(struct e1000_hw *hw) argument
933 if(hw->mac_type != e1000_82543) {
935 hw->tbi_compatibility_en = FALSE;
938 switch (hw->device_id) {
941 hw->media_type = e1000_media_type_internal_serdes;
944 if(hw->mac_type >= e1000_82543) {
945 status = E1000_READ_REG(hw, STATUS);
947 hw->media_type = e1000_media_type_fiber;
949 hw->tbi_compatibility_en = FALSE;
951 hw->media_type = e1000_media_type_copper;
955 hw->media_type = e1000_media_type_fiber;
963 * hw - Struct containing variables accessed by shared code
966 e1000_reset_hw(struct e1000_hw *hw) argument
968 uint32_t ctrl; local
976 if(hw->mac_type == e1000_82542_rev2_0) {
978 e1000_pci_clear_mwi(hw);
983 E1000_WRITE_REG(hw, IMC, 0xffffffff);
989 E1000_WRITE_REG(hw, RCTL, 0);
990 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
991 E1000_WRITE_FLUSH(hw);
994 hw->tbi_compatibility_on = FALSE;
1001 ctrl = E1000_READ_REG(hw, CTRL);
1004 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1005 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1011 * the current PCI configuration. The global reset bit is self-
1016 switch(hw->mac_type) {
1023 /* These controllers can't ack the 64-bit write when issuing the
1024 * reset, so use IO-mapping as a workaround to issue the reset */
1025 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1030 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1033 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1037 /* After MAC reset, force reload of EEPROM to restore power-on settings to
1041 switch(hw->mac_type) {
1048 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1050 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1051 E1000_WRITE_FLUSH(hw);
1068 /* Disable HW ARPs on ASF enabled adapters */
1069 if(hw->mac_type >= e1000_82540) {
1070 manc = E1000_READ_REG(hw, MANC);
1072 E1000_WRITE_REG(hw, MANC, manc);
1075 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1076 e1000_phy_init_script(hw);
1081 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1084 icr = E1000_READ_REG(hw, ICR);
1087 if(hw->mac_type == e1000_82542_rev2_0) {
1089 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1091 e1000_pci_set_mwi(hw);
1098 * hw - Struct containing variables accessed by shared code
1101 * post-reset uninitialized state. Initializes the receive address registers,
1103 * configuration and flow control settings. Clears all on-chip counters. Leaves
1107 e1000_init_hw(struct e1000_hw *hw) argument
1109 uint32_t ctrl, status; local
1121 e1000_set_media_type(hw);
1125 E1000_WRITE_REG(hw, VET, 0);
1127 e1000_clear_vfta(hw);
1130 if(hw->mac_type == e1000_82542_rev2_0) {
1132 e1000_pci_clear_mwi(hw);
1133 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1134 E1000_WRITE_FLUSH(hw);
1139 * Address Registers (RARs 0 - 15).
1141 e1000_init_rx_addrs(hw);
1144 if(hw->mac_type == e1000_82542_rev2_0) {
1145 E1000_WRITE_REG(hw, RCTL, 0);
1146 E1000_WRITE_FLUSH(hw);
1149 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1151 e1000_pci_set_mwi(hw);
1157 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1160 /* Set the PCI priority bit correctly in the CTRL register. This
1164 if(hw->dma_fairness) {
1165 ctrl = E1000_READ_REG(hw, CTRL);
1166 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1170 switch(hw->mac_type) {
1175 if (hw->mac_type >= e1000_82543) {
1177 status = E1000_READ_REG(hw, STATUS);
1182 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1184 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
1185 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
1195 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
1201 /* Call a subroutine to configure the link and setup flow control. */
1202 ret_val = e1000_setup_link(hw);
1204 /* Set the transmit descriptor write-back policy */
1205 if(hw->mac_type > e1000_82544) {
1206 ctrl = E1000_READ_REG(hw, TXDCTL);
1207 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1208 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1217 e1000_clear_hw_cntrs(hw);
1226 * hw - Struct containing variables accessed by shared code.
1229 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) argument
1236 if(hw->media_type != e1000_media_type_internal_serdes)
1239 switch(hw->mac_type) {
1247 if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
1255 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1264 * Configures flow control and link settings.
1266 * hw - Struct containing variables accessed by shared code
1268 * Determines which flow control settings to use. Calls the apropriate media-
1269 * specific link configuration function. Configures the flow control settings.
1275 e1000_setup_link(struct e1000_hw *hw) argument
1284 * that determine the hardware's default PAUSE (flow control) mode,
1285 * a bit that determines whether the HW defaults to enabling or
1286 * disabling auto-negotiation, and the direction of the
1287 * SW defined pins. If there is no SW over-ride of the flow
1288 * control setting, then the variable hw->fc will
1291 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
1293 return -E1000_ERR_EEPROM;
1296 if(hw->fc == e1000_fc_default) {
1298 hw->fc = e1000_fc_none;
1301 hw->fc = e1000_fc_tx_pause;
1303 hw->fc = e1000_fc_full;
1306 /* We want to save off the original Flow Control configuration just
1308 * hub or switch with different Flow Control capabilities.
1310 if(hw->mac_type == e1000_82542_rev2_0)
1311 hw->fc &= (~e1000_fc_tx_pause);
1315 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1317 if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
1319 hw->fc &= (~e1000_fc_rx_pause);
1322 hw->original_fc = hw->fc;
1325 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1334 if(hw->mac_type == e1000_82543) {
1337 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1341 ret_val = (hw->media_type == e1000_media_type_copper) ?
1342 e1000_setup_copper_link(hw) :
1343 e1000_setup_fiber_serdes_link(hw);
1348 /* Initialize the flow control address, type, and PAUSE timer
1349 * registers to their default values. This is done even if flow
1353 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1355 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1356 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1357 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1359 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1361 E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
1364 /* Set the flow control receive threshold registers. Normally,
1370 if(!(hw->fc & e1000_fc_tx_pause)) {
1371 E1000_WRITE_REG(hw, FCRTL, 0);
1372 E1000_WRITE_REG(hw, FCRTH, 0);
1378 if(hw->fc_send_xon) {
1379 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1380 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1382 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1383 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1386 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
1387 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
1396 * hw - Struct containing variables accessed by shared code
1403 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) argument
1405 uint32_t ctrl; local
1420 ctrl = E1000_READ_REG(hw, CTRL);
1421 if(hw->media_type == e1000_media_type_fiber)
1422 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1424 if((ret_val = e1000_adjust_serdes_amplitude(hw)))
1428 ctrl &= ~(E1000_CTRL_LRST);
1432 if((ret_val = e1000_set_vco_speed(hw)))
1436 e1000_config_collision_dist(hw);
1438 /* Check for a software override of the flow control settings, and setup
1439 * the device accordingly. If auto-negotiation is enabled, then software
1441 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1442 * auto-negotiation is disabled, then software will have to manually
1443 * configure the two flow control enable bits in the CTRL register.
1446 * 0: Flow control is completely disabled
1447 * 1: Rx flow control is enabled (we can receive pause frames, but
1449 * 2: Tx flow control is enabled (we can send pause frames but we do
1451 * 3: Both Rx and TX flow control (symmetric) are enabled.
1453 switch (hw->fc) {
1455 /* Flow control is completely disabled by a software over-ride. */
1459 /* RX Flow control is enabled and TX Flow control is disabled by a
1460 * software over-ride. Since there really isn't a way to advertise
1468 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1469 * software over-ride.
1474 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1478 DEBUGOUT("Flow control param set incorrectly\n");
1479 return -E1000_ERR_CONFIG;
1483 /* Since auto-negotiation is enabled, take the link out of reset (the link
1485 * restart auto-negotiation. If auto-neogtiation is successful then the
1486 * link-up status bit will be set and the flow control enable bits (RFCE
1489 DEBUGOUT("Auto-negotiation enabled\n");
1491 E1000_WRITE_REG(hw, TXCW, txcw);
1492 E1000_WRITE_REG(hw, CTRL, ctrl);
1493 E1000_WRITE_FLUSH(hw);
1495 hw->txcw = txcw;
1498 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1499 * indication in the Device Status Register. Time-out if a link isn't
1500 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1504 if(hw->media_type == e1000_media_type_internal_serdes ||
1505 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1509 status = E1000_READ_REG(hw, STATUS);
1513 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1514 hw->autoneg_failed = 1;
1518 * non-autonegotiating link partners.
1520 if((ret_val = e1000_check_for_link(hw))) {
1524 hw->autoneg_failed = 0;
1526 hw->autoneg_failed = 0;
1538 * hw - Struct containing variables accessed by shared code
1541 e1000_setup_copper_link(struct e1000_hw *hw) argument
1543 uint32_t ctrl; local
1550 ctrl = E1000_READ_REG(hw, CTRL);
1555 if(hw->mac_type > e1000_82543) {
1556 ctrl |= E1000_CTRL_SLU;
1557 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1558 E1000_WRITE_REG(hw, CTRL, ctrl);
1560 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1561 E1000_WRITE_REG(hw, CTRL, ctrl);
1562 e1000_phy_hw_reset(hw);
1566 if((ret_val = e1000_detect_gig_phy(hw))) {
1570 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1572 if(hw->mac_type <= e1000_82543 ||
1573 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1575 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1576 hw->phy_reset_disable = FALSE;
1578 if(!hw->phy_reset_disable) {
1580 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1582 if (hw->phy_type == e1000_phy_igp) {
1584 if((ret_val = e1000_phy_reset(hw))) {
1594 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1599 /* Configure mdi-mdix settings */
1600 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1604 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1605 hw->dsp_config_state = e1000_dsp_config_disabled;
1606 /* Force MDI for IGP B-0 PHY */
1609 hw->mdix = 1;
1612 hw->dsp_config_state = e1000_dsp_config_enabled;
1615 switch (hw->mdix) {
1628 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1632 /* set auto-master slave resolution settings */
1633 e1000_ms_type phy_ms_setting = hw->master_slave;
1635 if(hw->ffe_config_state == e1000_ffe_config_active)
1636 hw->ffe_config_state = e1000_ffe_config_enabled;
1638 if(hw->dsp_config_state == e1000_dsp_config_activated)
1639 hw->dsp_config_state = e1000_dsp_config_enabled;
1645 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1647 if((ret_val = e1000_read_phy_reg(hw,
1652 if((ret_val = e1000_write_phy_reg(hw,
1657 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1661 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1666 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1672 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1693 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1697 /* Enable CRS on TX. This must be set for half-duplex operation. */
1698 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1705 * MDI/MDI-X = 0 (default)
1706 * 0 - Auto for all speeds
1707 * 1 - MDI mode
1708 * 2 - MDI-X mode
1709 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1714 switch (hw->mdix) {
1736 * 0 - Disabled
1737 * 1 - Enabled
1740 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1747 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1754 if (hw->phy_revision < M88E1011_I_REV_4) {
1761 if((ret_val = e1000_write_phy_reg(hw,
1768 if((ret_val = e1000_phy_reset(hw))) {
1791 /* Perform some bounds checking on the hw->autoneg_advertised
1794 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1799 if(hw->autoneg_advertised == 0)
1800 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1802 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1803 if((ret_val = e1000_phy_setup_autoneg(hw))) {
1804 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1807 DEBUGOUT("Restarting Auto-Neg\n");
1809 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1812 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1816 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1820 /* Does the user want to wait for Auto-Neg to complete here, or
1823 if(hw->wait_autoneg_complete) {
1824 if((ret_val = e1000_wait_autoneg(hw))) {
1833 if((ret_val = e1000_wait_autoneg(hw))) {
1838 } /* !hw->phy_reset_disable */
1844 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1846 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1855 * 2) Set up flow control on the MAC to that established with
1858 if(hw->mac_type >= e1000_82544) {
1859 e1000_config_collision_dist(hw);
1861 if((ret_val = e1000_config_mac_to_phy(hw))) {
1866 if((ret_val = e1000_config_fc_after_link_up(hw))) {
1867 DEBUGOUT("Error Configuring Flow Control\n");
1871 if(hw->phy_type == e1000_phy_igp) {
1872 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1885 return -E1000_ERR_NOLINK;
1889 * Configures PHY autoneg and flow control advertisement settings
1891 * hw - Struct containing variables accessed by shared code
1894 e1000_phy_setup_autoneg(struct e1000_hw *hw) argument
1902 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1903 if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1907 /* Read the MII 1000Base-T Control Register (Address 9). */
1908 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1918 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1920 * the 1000Base-T Control Register (Address 9).
1925 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1928 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1934 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1940 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1946 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1952 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1957 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1962 /* Check for a software override of the flow control settings, and
1964 * auto-negotiation is enabled, then software will have to set the
1965 * "PAUSE" bits to the correct value in the Auto-Negotiation
1966 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1969 * 0: Flow control is completely disabled
1970 * 1: Rx flow control is enabled (we can receive pause frames
1972 * 2: Tx flow control is enabled (we can send pause frames
1974 * 3: Both Rx and TX flow control (symmetric) are enabled.
1975 * other: No software override. The flow control configuration
1978 switch (hw->fc) {
1980 /* Flow control (RX & TX) is completely disabled by a
1981 * software over-ride.
1986 /* RX Flow control is enabled, and TX Flow control is
1987 * disabled, by a software over-ride.
1993 *hw's ability to send PAUSE frames.
1998 /* TX Flow control is enabled, and RX Flow control is
1999 * disabled, by a software over-ride.
2005 /* Flow control (both RX and TX) is enabled by a software
2006 * over-ride.
2011 DEBUGOUT("Flow control param set incorrectly\n");
2012 return -E1000_ERR_CONFIG;
2015 if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
2019 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2021 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
2030 * hw - Struct containing variables accessed by shared code
2036 e1000_config_collision_dist(struct e1000_hw *hw) argument
2040 tctl = E1000_READ_REG(hw, TCTL);
2045 E1000_WRITE_REG(hw, TCTL, tctl);
2046 E1000_WRITE_FLUSH(hw);
2052 * hw - Struct containing variables accessed by shared code
2053 * mii_reg - data to write to the MII control register
2059 e1000_config_mac_to_phy(struct e1000_hw *hw) argument
2061 uint32_t ctrl; local
2070 ctrl = E1000_READ_REG(hw, CTRL);
2071 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2072 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2077 if (hw->phy_type == e1000_phy_igp) {
2078 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2082 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
2083 else ctrl &= ~E1000_CTRL_FD;
2085 e1000_config_collision_dist(hw);
2092 ctrl |= E1000_CTRL_SPD_1000;
2095 ctrl |= E1000_CTRL_SPD_100;
2097 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
2101 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
2102 else ctrl &= ~E1000_CTRL_FD;
2104 e1000_config_collision_dist(hw);
2110 ctrl |= E1000_CTRL_SPD_1000;
2112 ctrl |= E1000_CTRL_SPD_100;
2115 E1000_WRITE_REG(hw, CTRL, ctrl);
2120 * Forces the MAC's flow control settings.
2122 * hw - Struct containing variables accessed by shared code
2131 e1000_force_mac_fc(struct e1000_hw *hw) argument
2133 uint32_t ctrl; local
2138 ctrl = E1000_READ_REG(hw, CTRL);
2140 /* Because we didn't get link via the internal auto-negotiation
2142 * auto-neg), we have to manually enable/disable transmit an
2143 * receive flow control.
2145 * The "Case" statement below enables/disable flow control
2146 * according to the "hw->fc" parameter.
2149 * 0: Flow control is completely disabled
2150 * 1: Rx flow control is enabled (we can receive pause
2152 * 2: Tx flow control is enabled (we can send pause frames
2154 * 3: Both Rx and TX flow control (symmetric) is enabled.
2158 switch (hw->fc) {
2160 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2163 ctrl &= (~E1000_CTRL_TFCE);
2164 ctrl |= E1000_CTRL_RFCE;
2167 ctrl &= (~E1000_CTRL_RFCE);
2168 ctrl |= E1000_CTRL_TFCE;
2171 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2174 DEBUGOUT("Flow control param set incorrectly\n");
2175 return -E1000_ERR_CONFIG;
2178 /* Disable TX Flow Control for 82542 (rev 2.0) */
2179 if(hw->mac_type == e1000_82542_rev2_0)
2180 ctrl &= (~E1000_CTRL_TFCE);
2182 E1000_WRITE_REG(hw, CTRL, ctrl);
2187 * Configures flow control settings after link is established
2189 * hw - Struct containing variables accessed by shared code
2192 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2193 * and autonegotiation is enabled, the MAC flow control settings will be set
2194 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2195 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2198 e1000_config_fc_after_link_up(struct e1000_hw *hw) argument
2209 /* Check for the case where we have fiber media and auto-neg failed
2213 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2214 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) {
2215 if((ret_val = e1000_force_mac_fc(hw))) {
2216 DEBUGOUT("Error forcing flow control settings\n");
2221 /* Check for the case where we have copper media and auto-neg is
2222 * enabled. In this case, we need to check and see if Auto-Neg
2224 * flow control configured.
2226 if(hw->media_type == e1000_media_type_copper) {
2231 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2233 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2240 * Register (Address 5) to determine how flow control was
2243 if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2246 if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2252 * Page Ability Register (Address 5) determine flow control
2255 * 1999, describes these PAUSE resolution bits and how flow
2261 *-------|---------|-------|---------|--------------------
2273 * Symmetric Flow Control is enabled at both ends. The
2276 * For Symmetric Flow Control:
2280 *-------|---------|-------|---------|--------------------
2288 * FULL flow control because we could not advertise RX
2293 if(hw->original_fc == e1000_fc_full) {
2294 hw->fc = e1000_fc_full;
2296 if(hw->fc == e1000_fc_full) {
2298 DEBUGOUT("Flow Control = FULL.\r\n");
2300 hw->fc = e1000_fc_rx_pause;
2301 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2308 *-------|---------|-------|---------|--------------------
2316 hw->fc = e1000_fc_tx_pause;
2317 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2323 *-------|---------|-------|---------|--------------------
2331 hw->fc = e1000_fc_rx_pause;
2332 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2334 /* Per the IEEE spec, at this point flow control should be
2337 * desired flow control, but can be forced on the link
2338 * partner. So if we advertised no flow control, that is
2340 * receive capability (Rx Pause Only or Full Flow Control)
2342 * ourselves to enable Rx Flow Control only. We can do
2344 * didn't want flow control enabled, and we enable Rx, no
2347 * flow control enabled, then by us enabling RX only, we
2355 else if(hw->original_fc == e1000_fc_none ||
2356 hw->original_fc == e1000_fc_tx_pause) {
2358 else if(hw->fc == e1000_fc_none)
2359 DEBUGOUT("Flow Control = NONE.\r\n");
2360 else if(hw->fc == e1000_fc_tx_pause) {
2362 hw->fc = e1000_fc_none;
2363 DEBUGOUT("Flow Control = NONE.\r\n");
2365 hw->fc = e1000_fc_rx_pause;
2366 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2369 /* Now we need to do one last check... If we auto-
2370 * negotiated to HALF DUPLEX, flow control should not be
2373 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2376 hw->fc = e1000_fc_none;
2379 * controller to use the correct flow control settings.
2381 if((ret_val = e1000_force_mac_fc(hw))) {
2382 DEBUGOUT("Error forcing flow control settings\n");
2395 * hw - Struct containing variables accessed by shared code
2400 e1000_check_for_link(struct e1000_hw *hw) argument
2403 uint32_t ctrl; local
2417 if(hw->media_type == e1000_media_type_fiber)
2418 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2420 ctrl = E1000_READ_REG(hw, CTRL);
2421 status = E1000_READ_REG(hw, STATUS);
2422 rxcw = E1000_READ_REG(hw, RXCW);
2425 * registers to see if Auto-Neg has completed and/or if our link
2431 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2433 if(hw->media_type == e1000_media_type_copper) {
2440 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2442 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2447 hw->get_link_status = FALSE;
2451 return -E1000_ERR_NOLINK;
2454 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2462 if(hw->mac_type >= e1000_82544)
2463 e1000_config_collision_dist(hw);
2465 if((ret_val = e1000_config_mac_to_phy(hw))) {
2471 /* Configure Flow Control now that Auto-Neg has completed. First, we
2472 * need to restore the desired flow control settings because we may
2473 * have had to re-autoneg with a different link partner.
2475 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2476 DEBUGOUT("Error configuring flow control\n");
2481 * auto-negotiated link. These are conditions for checking the link
2485 * we assume that they are GMII-based, and TBI compatibility is not
2487 * partner is TBI-based, and we turn on TBI Compatibility.
2489 if(hw->tbi_compatibility_en) {
2490 if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2501 if(hw->tbi_compatibility_on) {
2503 rctl = E1000_READ_REG(hw, RCTL);
2505 E1000_WRITE_REG(hw, RCTL, rctl);
2506 hw->tbi_compatibility_on = FALSE;
2514 if(!hw->tbi_compatibility_on) {
2515 hw->tbi_compatibility_on = TRUE;
2516 rctl = E1000_READ_REG(hw, RCTL);
2518 E1000_WRITE_REG(hw, RCTL, rctl);
2523 /* If we don't have link (auto-negotiation failed or link partner cannot
2524 * auto-negotiate), the cable is plugged in (we have signal), and our
2525 * link partner is not trying to auto-negotiate with us (we are receiving
2527 * auto-negotiation time to complete, in case the cable was just plugged
2530 else if((((hw->media_type == e1000_media_type_fiber) &&
2531 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2532 (hw->media_type == e1000_media_type_internal_serdes)) &&
2535 if(hw->autoneg_failed == 0) {
2536 hw->autoneg_failed = 1;
2541 /* Disable auto-negotiation in the TXCW register */
2542 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2544 /* Force link-up and also force full-duplex. */
2545 ctrl = E1000_READ_REG(hw, CTRL);
2546 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2547 E1000_WRITE_REG(hw, CTRL, ctrl);
2549 /* Configure Flow Control after forcing link up. */
2550 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2551 DEBUGOUT("Error configuring flow control\n");
2555 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2556 * auto-negotiation in the TXCW register and disable forced link in the
2557 * Device Control register in an attempt to auto-negotiate with our link
2560 else if(((hw->media_type == e1000_media_type_fiber) ||
2561 (hw->media_type == e1000_media_type_internal_serdes)) &&
2562 (ctrl & E1000_CTRL_SLU) &&
2565 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2566 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2569 /* If we force link for non-auto-negotiation switch, check link status
2572 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2573 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2576 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2578 hw->serdes_link_down = FALSE;
2582 hw->serdes_link_down = TRUE;
2593 * hw - Struct containing variables accessed by shared code
2594 * speed - Speed of the connection
2595 * duplex - Duplex setting of the connection
2598 e1000_get_speed_and_duplex(struct e1000_hw *hw, argument
2606 if(hw->mac_type >= e1000_82543) {
2607 status = E1000_READ_REG(hw, STATUS);
2636 * hw - Struct containing variables accessed by shared code
2639 e1000_wait_autoneg(struct e1000_hw *hw) argument
2646 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2649 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2650 /* Read the MII Status Register and wait for Auto-Neg
2653 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2655 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2658 DEBUGOUT("Auto-Neg complete.\n");
2663 DEBUGOUT("Auto-Neg timedout.\n");
2664 return -E1000_ERR_TIMEOUT;
2670 * hw - Struct containing variables accessed by shared code
2671 * ctrl - Device control register's current value
2674 e1000_raise_mdi_clk(struct e1000_hw *hw, argument
2675 uint32_t *ctrl) argument
2680 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2681 E1000_WRITE_FLUSH(hw);
2688 * hw - Struct containing variables accessed by shared code
2689 * ctrl - Device control register's current value
2692 e1000_lower_mdi_clk(struct e1000_hw *hw, argument
2693 uint32_t *ctrl) argument
2698 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2699 E1000_WRITE_FLUSH(hw);
2706 * hw - Struct containing variables accessed by shared code
2707 * data - Data to send out to the PHY
2708 * count - Number of bits to shift out
2713 e1000_shift_out_mdi_bits(struct e1000_hw *hw, argument
2717 uint32_t ctrl; local
2725 mask <<= (count - 1);
2727 ctrl = E1000_READ_REG(hw, CTRL);
2730 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2738 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2739 else ctrl &= ~E1000_CTRL_MDIO;
2741 E1000_WRITE_REG(hw, CTRL, ctrl);
2742 E1000_WRITE_FLUSH(hw);
2746 e1000_raise_mdi_clk(hw, &ctrl);
2747 e1000_lower_mdi_clk(hw, &ctrl);
2756 * hw - Struct containing variables accessed by shared code
2761 e1000_shift_in_mdi_bits(struct e1000_hw *hw) argument
2763 uint32_t ctrl; local
2774 ctrl = E1000_READ_REG(hw, CTRL);
2777 ctrl &= ~E1000_CTRL_MDIO_DIR;
2778 ctrl &= ~E1000_CTRL_MDIO;
2780 E1000_WRITE_REG(hw, CTRL, ctrl);
2781 E1000_WRITE_FLUSH(hw);
2787 e1000_raise_mdi_clk(hw, &ctrl);
2788 e1000_lower_mdi_clk(hw, &ctrl);
2792 e1000_raise_mdi_clk(hw, &ctrl);
2793 ctrl = E1000_READ_REG(hw, CTRL);
2795 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2796 e1000_lower_mdi_clk(hw, &ctrl);
2799 e1000_raise_mdi_clk(hw, &ctrl);
2800 e1000_lower_mdi_clk(hw, &ctrl);
2809 * hw - Struct containing variables accessed by shared code
2810 * reg_addr - address of the PHY register to read
2813 e1000_read_phy_reg(struct e1000_hw *hw, argument
2821 if(hw->phy_type == e1000_phy_igp &&
2823 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2828 ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2835 e1000_read_phy_reg_ex(struct e1000_hw *hw, argument
2847 return -E1000_ERR_PARAM;
2850 if(hw->mac_type > e1000_82543) {
2851 /* Set up Op-code, Phy Address, and register address in the MDI
2859 E1000_WRITE_REG(hw, MDIC, mdic);
2864 mdic = E1000_READ_REG(hw, MDIC);
2869 return -E1000_ERR_PHY;
2873 return -E1000_ERR_PHY;
2881 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2897 e1000_shift_out_mdi_bits(hw, mdic, 14);
2900 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2903 *phy_data = e1000_shift_in_mdi_bits(hw);
2911 * hw - Struct containing variables accessed by shared code
2912 * reg_addr - address of the PHY register to write
2913 * data - data to write to the PHY
2916 e1000_write_phy_reg(struct e1000_hw *hw, argument
2924 if(hw->phy_type == e1000_phy_igp &&
2926 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2931 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2938 e1000_write_phy_reg_ex(struct e1000_hw *hw, argument
2950 return -E1000_ERR_PARAM;
2953 if(hw->mac_type > e1000_82543) {
2954 /* Set up Op-code, Phy Address, register address, and data intended
2963 E1000_WRITE_REG(hw, MDIC, mdic);
2968 mdic = E1000_READ_REG(hw, MDIC);
2973 return -E1000_ERR_PHY;
2981 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2994 e1000_shift_out_mdi_bits(hw, mdic, 32);
3001 * Returns the PHY to the power-on reset state
3003 * hw - Struct containing variables accessed by shared code
3006 e1000_phy_hw_reset(struct e1000_hw *hw) argument
3008 uint32_t ctrl, ctrl_ext; local
3014 if(hw->mac_type > e1000_82543) {
3018 ctrl = E1000_READ_REG(hw, CTRL);
3019 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3020 E1000_WRITE_FLUSH(hw);
3022 E1000_WRITE_REG(hw, CTRL, ctrl);
3023 E1000_WRITE_FLUSH(hw);
3028 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3031 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3032 E1000_WRITE_FLUSH(hw);
3035 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3036 E1000_WRITE_FLUSH(hw);
3044 * hw - Struct containing variables accessed by shared code
3049 e1000_phy_reset(struct e1000_hw *hw) argument
3056 if(hw->mac_type != e1000_82541_rev_2) {
3057 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
3061 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
3065 } else e1000_phy_hw_reset(hw);
3067 if(hw->phy_type == e1000_phy_igp)
3068 e1000_phy_init_script(hw);
3076 * hw - Struct containing variables accessed by shared code
3079 e1000_detect_gig_phy(struct e1000_hw *hw) argument
3088 if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
3091 hw->phy_id = (uint32_t) (phy_id_high << 16);
3093 if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
3096 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3098 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3101 switch(hw->mac_type) {
3103 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3106 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3113 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3119 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3122 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3123 return -E1000_ERR_CONFIG;
3125 phy_init_status = e1000_set_phy_type(hw);
3128 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3131 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3132 return -E1000_ERR_PHY;
3136 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3139 * hw - Struct containing variables accessed by shared code
3142 e1000_init_eeprom_params(struct e1000_hw *hw) argument
3144 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3145 uint32_t eecd = E1000_READ_REG(hw, EECD);
3150 switch (hw->mac_type) {
3155 eeprom->type = e1000_eeprom_microwire;
3156 eeprom->word_size = 64;
3157 eeprom->opcode_bits = 3;
3158 eeprom->address_bits = 6;
3159 eeprom->delay_usec = 50;
3166 eeprom->type = e1000_eeprom_microwire;
3167 eeprom->opcode_bits = 3;
3168 eeprom->delay_usec = 50;
3170 eeprom->word_size = 256;
3171 eeprom->address_bits = 8;
3173 eeprom->word_size = 64;
3174 eeprom->address_bits = 6;
3182 eeprom->type = e1000_eeprom_spi;
3184 eeprom->page_size = 32;
3185 eeprom->address_bits = 16;
3187 eeprom->page_size = 8;
3188 eeprom->address_bits = 8;
3191 eeprom->type = e1000_eeprom_microwire;
3192 eeprom->opcode_bits = 3;
3193 eeprom->delay_usec = 50;
3195 eeprom->word_size = 256;
3196 eeprom->address_bits = 8;
3198 eeprom->word_size = 64;
3199 eeprom->address_bits = 6;
3204 eeprom->type = e1000_eeprom_spi;
3206 eeprom->page_size = 32;
3207 eeprom->address_bits = 16;
3209 eeprom->page_size = 8;
3210 eeprom->address_bits = 8;
3215 if (eeprom->type == e1000_eeprom_spi) {
3216 eeprom->opcode_bits = 8;
3217 eeprom->delay_usec = 1;
3218 eeprom->word_size = 64;
3219 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3224 eeprom->word_size = 8192;
3227 eeprom->word_size = 4096;
3230 eeprom->word_size = 2048;
3233 eeprom->word_size = 1024;
3236 eeprom->word_size = 512;
3239 eeprom->word_size = 256;
3250 * e1000_reset - Reset the adapter
3254 e1000_reset(struct e1000_hw *hw) argument
3258 * To take effect CTRL.RST is required.
3261 if(hw->mac_type < e1000_82547) {
3266 E1000_WRITE_REG(hw, PBA, pba);
3268 /* flow control settings */
3270 hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3271 hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3272 hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3273 hw->fc_send_xon = 1;
3274 hw->fc = hw->original_fc;
3277 e1000_reset_hw(hw);
3278 if(hw->mac_type >= e1000_82544)
3279 E1000_WRITE_REG(hw, WUC, 0);
3280 return e1000_init_hw(hw);
3284 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3293 e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw) argument
3298 pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3299 pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3300 pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3303 &hw->subsystem_vendor_id);
3304 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3307 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3311 result = e1000_set_mac_type(hw);
3319 e1000_init_eeprom_params(hw);
3322 if((hw->mac_type == e1000_82541) ||
3323 (hw->mac_type == e1000_82547) ||
3324 (hw->mac_type == e1000_82541_rev_2) ||
3325 (hw->mac_type == e1000_82547_rev_2))
3326 hw->phy_init_script = 1;
3329 e1000_set_media_type(hw);
3332 if(hw->mac_type < e1000_82543)
3333 hw->report_tx_early = 0;
3335 hw->report_tx_early = 1;
3337 hw->wait_autoneg_complete = FALSE;
3339 hw->tbi_compatibility_en = TRUE;
3341 hw->adaptive_ifs = TRUE;
3345 if(hw->media_type == e1000_media_type_copper) {
3346 hw->mdix = AUTO_ALL_MODES;
3347 hw->disable_polarity_correction = FALSE;
3348 hw->master_slave = E1000_MASTER_SLAVE;
3361 rd->buffer_addr = virt_to_bus(&packet);
3362 E1000_WRITE_REG (&hw, RDT, rx_tail);
3376 E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
3377 E1000_WRITE_REG (&hw, TDBAH, 0);
3378 E1000_WRITE_REG (&hw, TDLEN, 128);
3380 /* Setup the HW Tx Head and Tail descriptor pointers */
3382 E1000_WRITE_REG (&hw, TDH, 0);
3383 E1000_WRITE_REG (&hw, TDT, 0);
3389 tctl = E1000_READ_REG(&hw, TCTL);
3400 E1000_WRITE_REG (&hw, TCTL, tctl);
3402 e1000_config_collision_dist(&hw);
3407 E1000_WRITE_REG (&hw, RCTL, 0);
3415 E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
3416 E1000_WRITE_REG (&hw, RDBAH, 0);
3418 E1000_WRITE_REG (&hw, RDLEN, 128);
3420 /* Setup the HW Rx Head and Tail Descriptor Pointers */
3421 E1000_WRITE_REG (&hw, RDH, 0);
3422 E1000_WRITE_REG (&hw, RDT, 0);
3424 E1000_WRITE_REG (&hw, RCTL,
3435 POLL - Wait for a frame
3441 /* nic->packet should contain data on return */
3442 /* nic->packetlen should contain length of data */
3446 if (!rd->status & E1000_RXD_STAT_DD)
3451 // printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
3452 memcpy (nic->packet, packet, rd->length);
3453 nic->packetlen = rd->length;
3459 TRANSMIT - Transmit a frame
3478 memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
3486 txhd->buffer_addr = virt_to_bus (&hdr);
3487 txhd->lower.data = sizeof (hdr);
3488 txhd->upper.data = 0;
3490 txp->buffer_addr = virt_to_bus(p);
3491 txp->lower.data = E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | size;
3492 txp->upper.data = 0;
3494 E1000_WRITE_REG (&hw, TDT, tx_tail);
3495 while (!(txp->upper.data & E1000_TXD_STAT_DD)) {
3504 DISABLE - Turn off ethernet interface
3509 E1000_WRITE_REG (&hw, TDH, 0);
3510 E1000_WRITE_REG (&hw, TDT, 0);
3513 E1000_WRITE_REG (&hw, RDH, 0);
3514 E1000_WRITE_REG (&hw, RDT, 0);
3517 E1000_WRITE_REG (&hw, CTRL, E1000_CTRL_RST);
3520 E1000_WRITE_REG (&hw, RCTL, 0);
3521 E1000_WRITE_REG (&hw, TCTL, 0);
3525 iounmap(hw.hw_addr);
3529 IRQ - Enable, Disable, or Force interrupts
3549 PROBE - Look for an adapter, this routine's visible to the outside
3550 You should omit the last argument struct pci_device * for a non-PCI NIC
3560 /* Initialize hw with default values */
3561 memset(&hw, 0, sizeof(hw));
3562 hw.pdev = p;
3566 hw.fc = e1000_fc_none;
3568 hw.original_fc = e1000_fc_none;
3570 hw.autoneg_failed = 0;
3572 hw.get_link_status = TRUE;
3578 hw.hw_addr = ioremap(mmio_start, mmio_len);
3584 hw.io_base = pci_bar_start(p, i);
3591 nic->ioaddr = p->ioaddr & ~3;
3592 nic->irqno = 0;
3598 if (e1000_sw_init(p, &hw) < 0) {
3599 iounmap(hw.hw_addr);
3605 if (e1000_validate_eeprom_checksum(&hw) < 0) {
3607 iounmap(hw.hw_addr);
3613 e1000_read_mac_addr(&hw);
3614 memcpy (nic->node_addr, hw.mac_addr, ETH_ALEN);
3616 printf("Ethernet addr: %!\n", nic->node_addr);
3620 ret_val = e1000_reset(&hw);
3622 if ((ret_val == -E1000_ERR_NOLINK) ||
3623 (ret_val == -E1000_ERR_TIMEOUT)) {
3628 iounmap(hw.hw_addr);
3634 dev->disable = e1000_disable;
3635 nic->poll = e1000_poll;
3636 nic->transmit = e1000_transmit;
3637 nic->irq = e1000_irq;
3643 PCI_ROM(0x8086, 0x1000, "e1000-82542", "Intel EtherExpressPro1000"),
3644 PCI_ROM(0x8086, 0x1001, "e1000-82543gc-fiber", "Intel EtherExpressPro1000 82543GC Fiber"),
3645 PCI_ROM(0x8086, 0x1004, "e1000-82543gc-copper", "Intel EtherExpressPro1000 82543GC Copper"),
3646 PCI_ROM(0x8086, 0x1008, "e1000-82544ei-copper", "Intel EtherExpressPro1000 82544EI Copper"),
3647 PCI_ROM(0x8086, 0x1009, "e1000-82544ei-fiber", "Intel EtherExpressPro1000 82544EI Fiber"),
3648 PCI_ROM(0x8086, 0x100C, "e1000-82544gc-copper", "Intel EtherExpressPro1000 82544GC Copper"),
3649 PCI_ROM(0x8086, 0x100D, "e1000-82544gc-lom", "Intel EtherExpressPro1000 82544GC LOM"),
3650 PCI_ROM(0x8086, 0x100E, "e1000-82540em", "Intel EtherExpressPro1000 82540EM"),
3651 PCI_ROM(0x8086, 0x100F, "e1000-82545em-copper", "Intel EtherExpressPro1000 82545EM Copper"),
3652 PCI_ROM(0x8086, 0x1010, "e1000-82546eb-copper", "Intel EtherExpressPro1000 82546EB Copper"),
3653 PCI_ROM(0x8086, 0x1011, "e1000-82545em-fiber", "Intel EtherExpressPro1000 82545EM Fiber"),
3654 PCI_ROM(0x8086, 0x1012, "e1000-82546eb-fiber", "Intel EtherExpressPro1000 82546EB Copper"),
3655 PCI_ROM(0x8086, 0x1013, "e1000-82541ei", "Intel EtherExpressPro1000 82541EI"),
3656 PCI_ROM(0x8086, 0x1015, "e1000-82540em-lom", "Intel EtherExpressPro1000 82540EM LOM"),
3657 PCI_ROM(0x8086, 0x1016, "e1000-82540ep-lom", "Intel EtherExpressPro1000 82540EP LOM"),
3658 PCI_ROM(0x8086, 0x1017, "e1000-82540ep", "Intel EtherExpressPro1000 82540EP"),
3659 PCI_ROM(0x8086, 0x1018, "e1000-82541ep", "Intel EtherExpressPro1000 82541EP"),
3660 PCI_ROM(0x8086, 0x1019, "e1000-82547ei", "Intel EtherExpressPro1000 82547EI"),
3661 PCI_ROM(0x8086, 0x101d, "e1000-82546eb-quad-copper", "Intel EtherExpressPro1000 82546EB Quad Copper…
3662 PCI_ROM(0x8086, 0x101e, "e1000-82540ep-lp", "Intel EtherExpressPro1000 82540EP LP"),
3663 PCI_ROM(0x8086, 0x1026, "e1000-82545gm-copper", "Intel EtherExpressPro1000 82545GM Copper"),
3664 PCI_ROM(0x8086, 0x1027, "e1000-82545gm-fiber", "Intel EtherExpressPro1000 82545GM Fiber"),
3665 PCI_ROM(0x8086, 0x1028, "e1000-82545gm-serdes", "Intel EtherExpressPro1000 82545GM SERDES"),
3666 PCI_ROM(0x8086, 0x1075, "e1000-82547gi", "Intel EtherExpressPro1000 82547GI"),
3667 PCI_ROM(0x8086, 0x1076, "e1000-82541gi", "Intel EtherExpressPro1000 82541GI"),
3668 PCI_ROM(0x8086, 0x1077, "e1000-82541gi-mobile", "Intel EtherExpressPro1000 82541GI Mobile"),
3669 PCI_ROM(0x8086, 0x1078, "e1000-82541er", "Intel EtherExpressPro1000 82541ER"),
3670 PCI_ROM(0x8086, 0x1079, "e1000-82546gb-copper", "Intel EtherExpressPro1000 82546GB Copper"),
3671 PCI_ROM(0x8086, 0x107a, "e1000-82546gb-fiber", "Intel EtherExpressPro1000 82546GB Fiber"),
3672 PCI_ROM(0x8086, 0x107b, "e1000-82546gb-serdes", "Intel EtherExpressPro1000 82546GB SERDES"),