297  outl(phy_data, ee_addr);                        /* MII Clock Low */  in phy_write_1bit()
299  outl(phy_data|MDCLKH, ee_addr);                 /* MII Clock High */  in phy_write_1bit()
301  outl(phy_data, ee_addr);                        /* MII Clock Low */  in phy_write_1bit()
314  outl(0x50000, ee_addr);  in phy_read_1bit()
319  outl(0x40000, ee_addr);  in phy_read_1bit()
355   outl(csr6, ioaddr + CSR6);  in davicom_media_chk()
374   outl(csr6, ioaddr + CSR6);  in davicom_media_chk()
398   outl(EE_ENB & ~EE_CS, ee_addr);  in read_eeprom()
399   outl(EE_ENB, ee_addr);  in read_eeprom()
404     outl(EE_ENB | dataval, ee_addr);  in read_eeprom()
406     outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);  in read_eeprom()
409   outl(EE_ENB, ee_addr);  in read_eeprom()
412     outl(EE_ENB | EE_SHIFT_CLK, ee_addr);  in read_eeprom()
415     outl(EE_ENB, ee_addr);  in read_eeprom()
420   outl(EE_ENB & ~EE_CS, ee_addr);  in read_eeprom()
482   outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);  in davicom_reset()
485   outl(0x00000001, ioaddr + CSR0);  in davicom_reset()
490   outl(0x0C00000, ioaddr + CSR0);	/* Sten 10/9 */  in davicom_reset()
496   outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);  in davicom_reset()
497   outl(virt_to_bus(&txd[0]), ioaddr + CSR4);	/* Sten 10/9 */  in davicom_reset()
509   outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);  in davicom_reset()
511   outl(0, ioaddr + CSR1);  in davicom_reset()
530   outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);  in davicom_reset()
532   outl(0, ioaddr + CSR2);  in davicom_reset()
562   outl(0, ioaddr + CSR1);  in davicom_transmit()
626   outl(0x00000000, ioaddr + CSR7);  in davicom_disable()
629   outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);  in davicom_disable()
676   outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);  in davicom_probe()