Lines Matching refs:BASE
73 outw(RX_DISABLE, BASE + VX_COMMAND); in t595_reset()
74 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); in t595_reset()
76 outw(TX_DISABLE, BASE + VX_COMMAND); in t595_reset()
77 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); in t595_reset()
79 outw(RX_RESET, BASE + VX_COMMAND); in t595_reset()
81 outw(TX_RESET, BASE + VX_COMMAND); in t595_reset()
83 outw(C_INTR_LATCH, BASE + VX_COMMAND); in t595_reset()
84 outw(SET_RD_0_MASK, BASE + VX_COMMAND); in t595_reset()
85 outw(SET_INTR_MASK, BASE + VX_COMMAND); in t595_reset()
86 outw(SET_RX_FILTER, BASE + VX_COMMAND); in t595_reset()
108 outb(nic->node_addr[i], BASE + VX_W2_ADDR_0 + i); in t595_reset()
110 outw(RX_RESET, BASE + VX_COMMAND); in t595_reset()
112 outw(TX_RESET, BASE + VX_COMMAND); in t595_reset()
118 inb(BASE + VX_W1_TX_STATUS); in t595_reset()
121 S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); in t595_reset()
123 S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); in t595_reset()
132 outw(ACK_INTR | 0xff, BASE + VX_COMMAND); in t595_reset()
135 FIL_BRDCST|FIL_MULTICAST, BASE + VX_COMMAND); in t595_reset()
150 outw(RX_ENABLE, BASE + VX_COMMAND); in t595_reset()
151 outw(TX_ENABLE, BASE + VX_COMMAND); in t595_reset()
192 while(( status=inb(BASE + VX_W1_TX_STATUS) )& TXS_COMPLETE ) { in t595_transmit()
194 outw(TX_RESET, BASE + VX_COMMAND); in t595_transmit()
195 outw(TX_ENABLE, BASE + VX_COMMAND); in t595_transmit()
198 outb(0x0, BASE + VX_W1_TX_STATUS); in t595_transmit()
201 while (inw(BASE + VX_W1_FREE_TX) < len + pad + 4) { in t595_transmit()
205 outw(len, BASE + VX_W1_TX_PIO_WR_1); in t595_transmit()
206 outw(0x0, BASE + VX_W1_TX_PIO_WR_1); /* Second dword meaningless */ in t595_transmit()
209 outsw(BASE + VX_W1_TX_PIO_WR_1, d, ETH_ALEN/2); in t595_transmit()
210 outsw(BASE + VX_W1_TX_PIO_WR_1, nic->node_addr, ETH_ALEN/2); in t595_transmit()
211 outw(t, BASE + VX_W1_TX_PIO_WR_1); in t595_transmit()
212 outsw(BASE + VX_W1_TX_PIO_WR_1, p, s / 2); in t595_transmit()
214 outb(*(p+s - 1), BASE + VX_W1_TX_PIO_WR_1); in t595_transmit()
217 outb(0, BASE + VX_W1_TX_PIO_WR_1); /* Padding */ in t595_transmit()
220 while((inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) != 0) in t595_transmit()
234 cst=inw(BASE + VX_STATUS); in t595_poll()
243 outw(ACK_INTR | cst, BASE + VX_COMMAND); in t595_poll()
244 outw(C_INTR_LATCH, BASE + VX_COMMAND); in t595_poll()
249 status = inw(BASE + VX_W1_RX_STATUS); in t595_poll()
255 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); in t595_poll()
269 insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet, rx_fifo / 2); in t595_poll()
271 nic->packet[rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1); in t595_poll()
275 status = inw(BASE + VX_W1_RX_STATUS); in t595_poll()
282 insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet+nic->packetlen, rx_fifo / 2); in t595_poll()
284 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1); in t595_poll()
300 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); in t595_poll()
301 while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS); in t595_poll()
326 for (i = 0; is_eeprom_busy(BASE) && i < MAX_EEPROMBUSY; i++) in eeprom_rdy()
346 outw(EEPROM_CMD_RD | offset, BASE + VX_W0_EEPROM_COMMAND);
349 return (inw(BASE + VX_W0_EEPROM_DATA));
358 vx_connectors = inw(BASE + VX_W3_RESET_OPT) & 0x7f; in vxgetlink()
373 vx_connector = (inl(BASE + VX_W3_INTERNAL_CFG) in vxgetlink()
413 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK; in vxsetlink()
414 outl(j | (i <<INTERNAL_CONNECTOR_BITS), BASE + VX_W3_INTERNAL_CFG); in vxsetlink()
417 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); in vxsetlink()
420 outw(0, BASE + VX_W4_MEDIA_TYPE); in vxsetlink()
426 outw(ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE); in vxsetlink()
429 outw(START_TRANSCEIVER,BASE + VX_COMMAND); in vxsetlink()
435 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE); in vxsetlink()
448 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); in t595_disable()
451 outw(0, BASE + VX_W4_MEDIA_TYPE); in t595_disable()
485 outw(GLOBAL_RESET, BASE + VX_COMMAND); in t595_probe()
505 outw(ntohs(p[i]), BASE + VX_W2_ADDR_0 + (i * 2)); in t595_probe()