Lines Matching full:bank

33  * =========== Chip-Select Bank Address Mode Encodings =======================
41 /* Managing bank address mode tables */
53  * =========== DRAM Address Mappings for bank/row/column =====================
71 /* Managing row/column/bank tables */
85  * =========== Bank swizzling information ====================================
100 /* Managing bank swizzle tables */
118  * of the first row of internal bank-select 0 on a chip-select, then the
119  * next row on internal bank-select 1, then 2 then 3;  instead of then
121  * other chip-selects in the interleave.  The row/column/bank mappings
127  *		       | row bits | bank bits | column bits | - |
134  * row number and all internal bank numbers on one cs before moving on
145  * simply follows the last bank address bit.
149  * General notes for CS Bank Address Mode Encoding tables.
158  * Chip Select Bank Address Mode Encoding for rev CG and earlier.
185  * Chip Select Bank Address Mode Encoding for revs D and E.
224  * Chip Select Bank Address Mode Encoding for rev F
267  * General notes on Row/Column/Bank table initialisation.
271  * a given revision, access width, bank-swizzle mode, and current chip-select
272  * mode the row, column and internal sdram bank are derived from the
279  * The bankargs list up to three bit numbers per bank bit.  For revisions
280  * CG and earlier there is no bank swizzling, so just a single number
281  * should be listed.  Revisions D and E have the same row/column/bank mapping,
283  * into each bank bit.  The consumer will know whether they are using bank
286  * part of the row address - eg in table 12 for csmode 0000b bank address
290  * to know which is the first bit after column and bank address bits.
303  * Row/Column/Bank address mappings for rev CG in 64-bit mode, no interleave.
353  * Row/Column/Bank address mappings for rev CG in 128-bit mode, no interleave.
402  * Row/Column/Bank address mappings for rev D/E in 64-bit mode, no interleave.
471  * Row/Column/Bank address mappings for rev D/E in 128-bit mode, no interleave.
540  * Row/Column/Bank address mappings for revs F/G in 64-bit mode, no interleave.
615  * Row/Column/Bank address mappings for revs F/G in 128-bit mode, no interleave.
693  * Bank swizzling is an option in revisions E and later.  Each internal-bank-
695  * address bits to use is not dependent on bank address mode but on
698  * While rev E only supports 2 bank address bits, rev F supports 3 but not
699  * all chip-select bank address modes use all 3.  These tables will list
701  * bank address bits - the consumer musr determine how many should be
702  * applied (listed in the above row/col/bank tables).
797  * Lookup the Chip-Select Bank Address Mode Encoding table for a given
819  * width, bank-swizzle and chip-select mode.
839  * Lookup the bank swizzling information for a given chip revision and
906 	 * The first row bit is immediately after the last bank bit.  in rct_csintlv_bits()