Lines Matching +full:0 +full:x44148

17 	{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
21 		{ "PIDX", 0, 13 },
22 	{ "SGE_PF_GTS", 0x1e004, 0 },
26 		{ "CIDXInc", 0, 12 },
27 	{ "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 },
28 	{ "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 },
29 	{ "SGE_PF_KDOORBELL", 0x1e400, 0 },
33 		{ "PIDX", 0, 13 },
34 	{ "SGE_PF_GTS", 0x1e404, 0 },
38 		{ "CIDXInc", 0, 12 },
39 	{ "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 },
40 	{ "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 },
41 	{ "SGE_PF_KDOORBELL", 0x1e800, 0 },
45 		{ "PIDX", 0, 13 },
46 	{ "SGE_PF_GTS", 0x1e804, 0 },
50 		{ "CIDXInc", 0, 12 },
51 	{ "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 },
52 	{ "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 },
53 	{ "SGE_PF_KDOORBELL", 0x1ec00, 0 },
57 		{ "PIDX", 0, 13 },
58 	{ "SGE_PF_GTS", 0x1ec04, 0 },
62 		{ "CIDXInc", 0, 12 },
63 	{ "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 },
64 	{ "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 },
65 	{ "SGE_PF_KDOORBELL", 0x1f000, 0 },
69 		{ "PIDX", 0, 13 },
70 	{ "SGE_PF_GTS", 0x1f004, 0 },
74 		{ "CIDXInc", 0, 12 },
75 	{ "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 },
76 	{ "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 },
77 	{ "SGE_PF_KDOORBELL", 0x1f400, 0 },
81 		{ "PIDX", 0, 13 },
82 	{ "SGE_PF_GTS", 0x1f404, 0 },
86 		{ "CIDXInc", 0, 12 },
87 	{ "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 },
88 	{ "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 },
89 	{ "SGE_PF_KDOORBELL", 0x1f800, 0 },
93 		{ "PIDX", 0, 13 },
94 	{ "SGE_PF_GTS", 0x1f804, 0 },
98 		{ "CIDXInc", 0, 12 },
99 	{ "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 },
100 	{ "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 },
101 	{ "SGE_PF_KDOORBELL", 0x1fc00, 0 },
105 		{ "PIDX", 0, 13 },
106 	{ "SGE_PF_GTS", 0x1fc04, 0 },
110 		{ "CIDXInc", 0, 12 },
111 	{ "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 },
112 	{ "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 },
113 	{ "SGE_CONTROL", 0x1008, 0 },
124 		{ "GlobalEnable", 0, 1 },
125 	{ "SGE_HOST_PAGE_SIZE", 0x100c, 0 },
133 		{ "HostPageSizePF0", 0, 4 },
134 	{ "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 },
142 		{ "QueuesPerPagePF0", 0, 4 },
143 	{ "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 },
151 		{ "QueuesPerPageVFPF0", 0, 4 },
152 	{ "SGE_USER_MODE_LIMITS", 0x1018, 0 },
156 		{ "Length_Max", 0, 8 },
157 	{ "SGE_WR_ERROR", 0x101c, 0 },
158 	{ "SGE_INT_CAUSE1", 0x1024, 0 },
184 		{ "perr_egr_ctxt_mifrsp", 0, 1 },
185 	{ "SGE_INT_ENABLE1", 0x1028, 0 },
211 		{ "perr_egr_ctxt_mifrsp", 0, 1 },
212 	{ "SGE_PERR_ENABLE1", 0x102c, 0 },
238 		{ "perr_egr_ctxt_mifrsp", 0, 1 },
239 	{ "SGE_INT_CAUSE2", 0x1030, 0 },
260 		{ "perr_base_size", 0, 1 },
261 	{ "SGE_INT_ENABLE2", 0x1034, 0 },
282 		{ "perr_base_size", 0, 1 },
283 	{ "SGE_PERR_ENABLE2", 0x1038, 0 },
304 		{ "perr_base_size", 0, 1 },
305 	{ "SGE_INT_CAUSE3", 0x103c, 0 },
337 		{ "err_inv_ctxt0", 0, 1 },
338 	{ "SGE_INT_ENABLE3", 0x1040, 0 },
370 		{ "err_inv_ctxt0", 0, 1 },
371 	{ "SGE_FL_BUFFER_SIZE0", 0x1044, 0 },
373 	{ "SGE_FL_BUFFER_SIZE1", 0x1048, 0 },
375 	{ "SGE_FL_BUFFER_SIZE2", 0x104c, 0 },
377 	{ "SGE_FL_BUFFER_SIZE3", 0x1050, 0 },
379 	{ "SGE_FL_BUFFER_SIZE4", 0x1054, 0 },
381 	{ "SGE_FL_BUFFER_SIZE5", 0x1058, 0 },
383 	{ "SGE_FL_BUFFER_SIZE6", 0x105c, 0 },
385 	{ "SGE_FL_BUFFER_SIZE7", 0x1060, 0 },
387 	{ "SGE_FL_BUFFER_SIZE8", 0x1064, 0 },
389 	{ "SGE_FL_BUFFER_SIZE9", 0x1068, 0 },
391 	{ "SGE_FL_BUFFER_SIZE10", 0x106c, 0 },
393 	{ "SGE_FL_BUFFER_SIZE11", 0x1070, 0 },
395 	{ "SGE_FL_BUFFER_SIZE12", 0x1074, 0 },
397 	{ "SGE_FL_BUFFER_SIZE13", 0x1078, 0 },
399 	{ "SGE_FL_BUFFER_SIZE14", 0x107c, 0 },
401 	{ "SGE_FL_BUFFER_SIZE15", 0x1080, 0 },
403 	{ "SGE_DBQ_CTXT_BADDR", 0x1084, 0 },
405 	{ "SGE_IMSG_CTXT_BADDR", 0x1088, 0 },
407 	{ "SGE_FLM_CACHE_BADDR", 0x108c, 0 },
409 	{ "SGE_FLM_CFG", 0x1090, 0 },
420 		{ "NoEDRAM", 0, 1 },
421 	{ "SGE_CONM_CTRL", 0x1094, 0 },
425 	{ "SGE_TIMESTAMP_LO", 0x1098, 0 },
426 	{ "SGE_TIMESTAMP_HI", 0x109c, 0 },
428 		{ "Value", 0, 28 },
429 	{ "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 },
433 		{ "Threshold_3", 0, 6 },
434 	{ "SGE_DBFIFO_STATUS", 0x10a4, 0 },
437 		{ "merge_fifo_cnt", 0, 6 },
438 	{ "SGE_DOORBELL_CONTROL", 0x10a8, 0 },
458 		{ "gts_dbg_en", 0, 1 },
459 	{ "SGE_ITP_CONTROL", 0x10b4, 0 },
463 		{ "LL_Read_Wait_Disable", 0, 1 },
464 	{ "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 },
466 		{ "TimerValue1", 0, 16 },
467 	{ "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 },
469 		{ "TimerValue3", 0, 16 },
470 	{ "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 },
472 		{ "TimerValue5", 0, 16 },
473 	{ "SGE_GK_CONTROL", 0x10c4, 0 },
480 		{ "100ns_timer", 0, 8 },
481 	{ "SGE_GK_CONTROL2", 0x10c8, 0 },
484 		{ "merge_cnt_thresh", 0, 6 },
485 	{ "SGE_DEBUG_INDEX", 0x10cc, 0 },
486 	{ "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 },
487 	{ "SGE_DEBUG_DATA_LOW", 0x10d4, 0 },
488 	{ "SGE_REVISION", 0x10d8, 0 },
489 	{ "SGE_INT_CAUSE4", 0x10dc, 0 },
521 		{ "err_unexpected_timer", 0, 1 },
522 	{ "SGE_INT_ENABLE4", 0x10e0, 0 },
554 		{ "err_unexpected_timer", 0, 1 },
555 	{ "SGE_STAT_TOTAL", 0x10e4, 0 },
556 	{ "SGE_STAT_MATCH", 0x10e8, 0 },
557 	{ "SGE_STAT_CFG", 0x10ec, 0 },
562 		{ "StatMode", 0, 4 },
563 	{ "SGE_HINT_CFG", 0x10f0, 0 },
566 		{ "HintsAllowedHdr", 0, 6 },
567 	{ "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 },
575 		{ "QueuesPerPagePF0", 0, 4 },
576 	{ "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 },
584 		{ "QueuesPerPageVFPF0", 0, 4 },
585 	{ "SGE_ERROR_STATS", 0x1100, 0 },
590 		{ "Error_QID", 0, 17 },
591 	{ "SGE_IDMA0_DROP_CNT", 0x1104, 0 },
592 	{ "SGE_IDMA1_DROP_CNT", 0x1108, 0 },
593 	{ "SGE_INT_CAUSE5", 0x110c, 0 },
625 		{ "perr_idma_switch_output_fifo0", 0, 1 },
626 	{ "SGE_INT_ENABLE5", 0x1110, 0 },
658 		{ "perr_idma_switch_output_fifo0", 0, 1 },
659 	{ "SGE_PERR_ENABLE5", 0x1114, 0 },
691 		{ "perr_idma_switch_output_fifo0", 0, 1 },
692 	{ "SGE_FETCH_BURST_MAX_0_AND_1", 0x111c, 0 },
694 		{ "FetchBurstMax1", 0, 10 },
695 	{ "SGE_FETCH_BURST_MAX_2_AND_3", 0x1120, 0 },
697 		{ "FetchBurstMax3", 0, 10 },
698 	{ "SGE_CONTROL2", 0x1124, 0 },
714 		{ "TX_Coalesce_Pri", 0, 1 },
715 	{ "SGE_INT_CAUSE6", 0x1128, 0 },
735 		{ "fatal_deq", 0, 1 },
736 	{ "SGE_INT_ENABLE6", 0x112c, 0 },
756 		{ "fatal_deq", 0, 1 },
757 	{ "SGE_DBVFIFO_BADDR", 0x1138, 0 },
759 	{ "SGE_DBVFIFO_SIZE", 0x113c, 0 },
760 	{ "SGE_CHANGESET", 0x1144, 0 },
761 	{ "SGE_PC_RSP_ERROR", 0x1148, 0 },
762 	{ "SGE_TBUF_CONTROL", 0x114c, 0 },
764 		{ "DbpTbufRsv0", 0, 9 },
765 	{ "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 },
766 	{ "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 },
767 	{ "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 },
768 	{ "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 },
769 	{ "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 },
770 	{ "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 },
771 	{ "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 },
772 	{ "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 },
773 	{ "SGE_DBQ_TIMER_THRESH0", 0x11b8, 0 },
777 		{ "TxTimeTh0", 0, 6 },
778 	{ "SGE_DBQ_TIMER_THRESH1", 0x11bc, 0 },
782 		{ "TxTimeTh4", 0, 6 },
783 	{ "SGE_DBQ_TIMER_CONFIG", 0x11c0, 0 },
784 	{ "SGE_DBQ_TIMER_DBG", 0x11c4, 0 },
787 		{ "dbq_timer_qcnt", 0, 17 },
788 	{ "SGE_CTXT_CMD", 0x11fc, 0 },
792 		{ "QID", 0, 17 },
793 	{ "SGE_CTXT_DATA0", 0x1200, 0 },
794 	{ "SGE_CTXT_DATA1", 0x1204, 0 },
795 	{ "SGE_CTXT_DATA2", 0x1208, 0 },
796 	{ "SGE_CTXT_DATA3", 0x120c, 0 },
797 	{ "SGE_CTXT_DATA4", 0x1210, 0 },
798 	{ "SGE_CTXT_DATA5", 0x1214, 0 },
799 	{ "SGE_CTXT_DATA6", 0x1218, 0 },
800 	{ "SGE_CTXT_DATA7", 0x121c, 0 },
801 	{ "SGE_CTXT_MASK0", 0x1220, 0 },
802 	{ "SGE_CTXT_MASK1", 0x1224, 0 },
803 	{ "SGE_CTXT_MASK2", 0x1228, 0 },
804 	{ "SGE_CTXT_MASK3", 0x122c, 0 },
805 	{ "SGE_CTXT_MASK4", 0x1230, 0 },
806 	{ "SGE_CTXT_MASK5", 0x1234, 0 },
807 	{ "SGE_CTXT_MASK6", 0x1238, 0 },
808 	{ "SGE_CTXT_MASK7", 0x123c, 0 },
809 	{ "SGE_QBASE_MAP0", 0x1240, 0 },
813 		{ "Ingress1_Size", 0, 5 },
814 	{ "SGE_QBASE_MAP1", 0x1244, 0 },
815 	{ "SGE_QBASE_MAP2", 0x1248, 0 },
816 	{ "SGE_QBASE_MAP3", 0x124c, 0 },
818 		{ "Ingress0_Base", 0, 16 },
819 	{ "SGE_QBASE_INDEX", 0x1250, 0 },
820 	{ "SGE_CONM_CTRL2", 0x1254, 0 },
822 		{ "FlmThresh", 0, 7 },
823 	{ "SGE_DEBUG_CONM", 0x1258, 0 },
828 		{ "last_qid", 0, 10 },
829 	{ "SGE_DBG_QUEUE_STAT0_CTRL", 0x125c, 0 },
832 		{ "db_gts_qid", 0, 17 },
833 	{ "SGE_DBG_QUEUE_STAT1_CTRL", 0x1260, 0 },
836 		{ "db_gts_qid", 0, 17 },
837 	{ "SGE_DBG_QUEUE_STAT0", 0x1264, 0 },
838 	{ "SGE_DBG_QUEUE_STAT1", 0x1268, 0 },
839 	{ "SGE_DBG_BAR2_PKT_CNT", 0x126c, 0 },
840 	{ "SGE_DBG_DB_PKT_CNT", 0x1270, 0 },
841 	{ "SGE_DBG_GTS_PKT_CNT", 0x1274, 0 },
842 	{ "SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280, 0 },
850 		{ "debug_CIM_EOP0_cnt", 0, 4 },
851 	{ "SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284, 0 },
859 		{ "debug_U_Rx_EOP0_cnt", 0, 4 },
860 	{ "SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288, 0 },
862 		{ "dbg_tbuf_used0", 0, 9 },
863 	{ "SGE_DEBUG1_DBP_THREAD", 0x128c, 0 },
867 		{ "fl_enq_cnt", 0, 4 },
868 	{ "SGE_DEBUG1_DBP_THREAD", 0x1290, 0 },
872 		{ "fl_enq_cnt", 0, 4 },
873 	{ "SGE_DEBUG1_DBP_THREAD", 0x1294, 0 },
877 		{ "fl_enq_cnt", 0, 4 },
878 	{ "SGE_DEBUG1_DBP_THREAD", 0x1298, 0 },
882 		{ "fl_enq_cnt", 0, 4 },
883 	{ "SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c, 0 },
891 		{ "debug_PD_WrReq_EOP0_cnt", 0, 4 },
892 	{ "SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0, 0 },
910 		{ "debug_PD_WrReq_Int0_cnt", 0, 4 },
911 	{ "SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4, 0 },
917 		{ "debug_CPLSW_CIM_EOP0_cnt", 0, 4 },
918 	{ "SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8, 0 },
940 		{ "debug_CIM_AFull_d", 0, 1 },
941 	{ "SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac, 0 },
953 		{ "debug_st_flm_idma0_ctxt", 0, 3 },
954 	{ "SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0, 0 },
960 		{ "debug_idma0_ishift_tx_size", 0, 7 },
961 	{ "SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4, 0 },
962 	{ "SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8, 0 },
963 	{ "SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc, 0 },
964 	{ "SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0, 0 },
974 		{ "debug_st_idma0_idma_sm", 0, 6 },
975 	{ "SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4, 0 },
981 		{ "debug_itp_evr_state", 0, 3 },
982 	{ "SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8, 0 },
986 	{ "SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc, 0 },
987 	{ "SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0, 0 },
993 		{ "debug_flm_dbptr_qid", 0, 12 },
994 	{ "SGE_DEBUG0_DBP_THREAD", 0x12d4, 0 },
998 		{ "thread_qid", 0, 17 },
999 	{ "SGE_DEBUG0_DBP_THREAD", 0x12d8, 0 },
1003 		{ "thread_qid", 0, 17 },
1004 	{ "SGE_DEBUG0_DBP_THREAD", 0x12dc, 0 },
1008 		{ "thread_qid", 0, 17 },
1009 	{ "SGE_DEBUG0_DBP_THREAD", 0x12e0, 0 },
1013 		{ "thread_qid", 0, 17 },
1014 	{ "SGE_DEBUG0_DBP_THREAD", 0x12e4, 0 },
1018 		{ "thread_qid", 0, 17 },
1019 	{ "SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8, 0 },
1021 		{ "debug_imsg_qid", 0, 16 },
1022 	{ "SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec, 0 },
1024 		{ "debug_idma0_qid", 0, 16 },
1025 	{ "SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0, 0 },
1027 		{ "debug_idma0_flm_req_qid", 0, 16 },
1028 	{ "SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4, 0 },
1029 	{ "SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8, 0 },
1030 	{ "SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc, 0 },
1031 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1300, 0 },
1037 		{ "PfWCOffset", 0, 17 },
1038 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1304, 0 },
1044 		{ "PfWCOffset", 0, 17 },
1045 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1308, 0 },
1051 		{ "PfWCOffset", 0, 17 },
1052 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x130c, 0 },
1058 		{ "PfWCOffset", 0, 17 },
1059 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1310, 0 },
1065 		{ "PfWCOffset", 0, 17 },
1066 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1314, 0 },
1072 		{ "PfWCOffset", 0, 17 },
1073 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1318, 0 },
1079 		{ "PfWCOffset", 0, 17 },
1080 	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x131c, 0 },
1086 		{ "PfWCOffset", 0, 17 },
1087 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1320, 0 },
1093 		{ "VfWCOffset", 0, 17 },
1094 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1324, 0 },
1100 		{ "VfWCOffset", 0, 17 },
1101 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1328, 0 },
1107 		{ "VfWCOffset", 0, 17 },
1108 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x132c, 0 },
1114 		{ "VfWCOffset", 0, 17 },
1115 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1330, 0 },
1121 		{ "VfWCOffset", 0, 17 },
1122 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1334, 0 },
1128 		{ "VfWCOffset", 0, 17 },
1129 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1338, 0 },
1135 		{ "VfWCOffset", 0, 17 },
1136 	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x133c, 0 },
1142 		{ "VfWCOffset", 0, 17 },
1143 	{ "SGE_LA_RDPTR_0", 0x1800, 0 },
1144 	{ "SGE_LA_RDDATA_0", 0x1804, 0 },
1145 	{ "SGE_LA_WRPTR_0", 0x1808, 0 },
1146 	{ "SGE_LA_RESERVED_0", 0x180c, 0 },
1147 	{ "SGE_LA_RDPTR_1", 0x1810, 0 },
1148 	{ "SGE_LA_RDDATA_1", 0x1814, 0 },
1149 	{ "SGE_LA_WRPTR_1", 0x1818, 0 },
1150 	{ "SGE_LA_RESERVED_1", 0x181c, 0 },
1151 	{ "SGE_LA_RDPTR_2", 0x1820, 0 },
1152 	{ "SGE_LA_RDDATA_2", 0x1824, 0 },
1153 	{ "SGE_LA_WRPTR_2", 0x1828, 0 },
1154 	{ "SGE_LA_RESERVED_2", 0x182c, 0 },
1155 	{ "SGE_LA_RDPTR_3", 0x1830, 0 },
1156 	{ "SGE_LA_RDDATA_3", 0x1834, 0 },
1157 	{ "SGE_LA_WRPTR_3", 0x1838, 0 },
1158 	{ "SGE_LA_RESERVED_3", 0x183c, 0 },
1159 	{ "SGE_LA_RDPTR_4", 0x1840, 0 },
1160 	{ "SGE_LA_RDDATA_4", 0x1844, 0 },
1161 	{ "SGE_LA_WRPTR_4", 0x1848, 0 },
1162 	{ "SGE_LA_RESERVED_4", 0x184c, 0 },
1163 	{ "SGE_LA_RDPTR_5", 0x1850, 0 },
1164 	{ "SGE_LA_RDDATA_5", 0x1854, 0 },
1165 	{ "SGE_LA_WRPTR_5", 0x1858, 0 },
1166 	{ "SGE_LA_RESERVED_5", 0x185c, 0 },
1167 	{ "SGE_LA_RDPTR_6", 0x1860, 0 },
1168 	{ "SGE_LA_RDDATA_6", 0x1864, 0 },
1169 	{ "SGE_LA_WRPTR_6", 0x1868, 0 },
1170 	{ "SGE_LA_RESERVED_6", 0x186c, 0 },
1171 	{ "SGE_LA_RDPTR_7", 0x1870, 0 },
1172 	{ "SGE_LA_RDDATA_7", 0x1874, 0 },
1173 	{ "SGE_LA_WRPTR_7", 0x1878, 0 },
1174 	{ "SGE_LA_RESERVED_7", 0x187c, 0 },
1175 	{ "SGE_LA_RDPTR_8", 0x1880, 0 },
1176 	{ "SGE_LA_RDDATA_8", 0x1884, 0 },
1177 	{ "SGE_LA_WRPTR_8", 0x1888, 0 },
1178 	{ "SGE_LA_RESERVED_8", 0x188c, 0 },
1179 	{ "SGE_LA_RDPTR_9", 0x1890, 0 },
1180 	{ "SGE_LA_RDDATA_9", 0x1894, 0 },
1181 	{ "SGE_LA_WRPTR_9", 0x1898, 0 },
1182 	{ "SGE_LA_RESERVED_9", 0x189c, 0 },
1183 	{ "SGE_LA_RDPTR_10", 0x18a0, 0 },
1184 	{ "SGE_LA_RDDATA_10", 0x18a4, 0 },
1185 	{ "SGE_LA_WRPTR_10", 0x18a8, 0 },
1186 	{ "SGE_LA_RESERVED_10", 0x18ac, 0 },
1187 	{ "SGE_LA_RDPTR_11", 0x18b0, 0 },
1188 	{ "SGE_LA_RDDATA_11", 0x18b4, 0 },
1189 	{ "SGE_LA_WRPTR_11", 0x18b8, 0 },
1190 	{ "SGE_LA_RESERVED_11", 0x18bc, 0 },
1191 	{ "SGE_LA_RDPTR_12", 0x18c0, 0 },
1192 	{ "SGE_LA_RDDATA_12", 0x18c4, 0 },
1193 	{ "SGE_LA_WRPTR_12", 0x18c8, 0 },
1194 	{ "SGE_LA_RESERVED_12", 0x18cc, 0 },
1195 	{ "SGE_LA_RDPTR_13", 0x18d0, 0 },
1196 	{ "SGE_LA_RDDATA_13", 0x18d4, 0 },
1197 	{ "SGE_LA_WRPTR_13", 0x18d8, 0 },
1198 	{ "SGE_LA_RESERVED_13", 0x18dc, 0 },
1199 	{ "SGE_LA_RDPTR_14", 0x18e0, 0 },
1200 	{ "SGE_LA_RDDATA_14", 0x18e4, 0 },
1201 	{ "SGE_LA_WRPTR_14", 0x18e8, 0 },
1202 	{ "SGE_LA_RESERVED_14", 0x18ec, 0 },
1203 	{ "SGE_LA_RDPTR_15", 0x18f0, 0 },
1204 	{ "SGE_LA_RDDATA_15", 0x18f4, 0 },
1205 	{ "SGE_LA_WRPTR_15", 0x18f8, 0 },
1206 	{ "SGE_LA_RESERVED_15", 0x18fc, 0 },
1211 	{ "PCIE_INT_ENABLE", 0x3000, 0 },
1243 		{ "MstGrpPerr", 0, 1 },
1244 	{ "PCIE_INT_CAUSE", 0x3004, 0 },
1276 		{ "MstGrpPerr", 0, 1 },
1277 	{ "PCIE_PERR_ENABLE", 0x3008, 0 },
1307 		{ "MstGrpPerr", 0, 1 },
1308 	{ "PCIE_PERR_INJECT", 0x300c, 0 },
1310 		{ "IDE", 0, 1 },
1311 	{ "PCIE_NONFAT_ERR", 0x3010, 0 },
1339 		{ "CfgSnp", 0, 1 },
1340 	{ "PCIE_CFG", 0x3014, 0 },
1358 		{ "LinkDnRstEn", 0, 1 },
1359 	{ "PCIE_CFG2", 0x3018, 0 },
1362 		{ "TotMaxTag", 0, 3 },
1363 	{ "PCIE_CFG3", 0x301c, 0 },
1368 		{ "DMADCASTFirstOnly", 0, 1 },
1369 	{ "PCIE_CFG4", 0x3020, 0 },
1374 		{ "GenPME", 0, 8 },
1375 	{ "PCIE_CFG5", 0x3024, 0 },
1378 		{ "HoldCplEnteringL1", 0, 1 },
1379 	{ "PCIE_CFG6", 0x3028, 0 },
1382 		{ "PERstTimer", 0, 4 },
1383 	{ "PCIE_CFG7", 0x302c, 0 },
1384 	{ "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
1393 		{ "Register", 0, 8 },
1394 	{ "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
1395 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3068, 0 },
1398 		{ "Window", 0, 8 },
1399 	{ "PCIE_MEM_ACCESS_OFFSET", 0x306c, 0 },
1401 		{ "PFNum", 0, 3 },
1402 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3070, 0 },
1405 		{ "Window", 0, 8 },
1406 	{ "PCIE_MEM_ACCESS_OFFSET", 0x3074, 0 },
1408 		{ "PFNum", 0, 3 },
1409 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3078, 0 },
1412 		{ "Window", 0, 8 },
1413 	{ "PCIE_MEM_ACCESS_OFFSET", 0x307c, 0 },
1415 		{ "PFNum", 0, 3 },
1416 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3080, 0 },
1419 		{ "Window", 0, 8 },
1420 	{ "PCIE_MEM_ACCESS_OFFSET", 0x3084, 0 },
1422 		{ "PFNum", 0, 3 },
1423 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3088, 0 },
1426 		{ "Window", 0, 8 },
1427 	{ "PCIE_MEM_ACCESS_OFFSET", 0x308c, 0 },
1429 		{ "PFNum", 0, 3 },
1430 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3090, 0 },
1433 		{ "Window", 0, 8 },
1434 	{ "PCIE_MEM_ACCESS_OFFSET", 0x3094, 0 },
1436 		{ "PFNum", 0, 3 },
1437 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3098, 0 },
1440 		{ "Window", 0, 8 },
1441 	{ "PCIE_MEM_ACCESS_OFFSET", 0x309c, 0 },
1443 		{ "PFNum", 0, 3 },
1444 	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x30a0, 0 },
1447 		{ "Window", 0, 8 },
1448 	{ "PCIE_MEM_ACCESS_OFFSET", 0x30a4, 0 },
1450 		{ "PFNum", 0, 3 },
1451 	{ "PCIE_MAILBOX_BASE_WIN", 0x30a8, 0 },
1454 		{ "Window", 0, 2 },
1455 	{ "PCIE_MAILBOX_OFFSET", 0x30ac, 0 },
1457 	{ "PCIE_MA_CTRL", 0x30b0, 0 },
1462 		{ "MaxTag", 0, 5 },
1463 	{ "PCIE_FW", 0x30b8, 0 },
1464 	{ "PCIE_FW_PF", 0x30bc, 0 },
1465 	{ "PCIE_FW_PF", 0x30c0, 0 },
1466 	{ "PCIE_FW_PF", 0x30c4, 0 },
1467 	{ "PCIE_FW_PF", 0x30c8, 0 },
1468 	{ "PCIE_FW_PF", 0x30cc, 0 },
1469 	{ "PCIE_FW_PF", 0x30d0, 0 },
1470 	{ "PCIE_FW_PF", 0x30d4, 0 },
1471 	{ "PCIE_FW_PF", 0x30d8, 0 },
1472 	{ "PCIE_PIO_PAUSE", 0x30dc, 0 },
1477 		{ "PIOPause", 0, 1 },
1478 	{ "PCIE_MA_STAT", 0x30e0, 0 },
1479 	{ "PCIE_STATIC_CFG1", 0x30e4, 0 },
1481 	{ "PCIE_STATIC_CFG2", 0x30e8, 0 },
1483 		{ "STATIC_SPARE3", 0, 14 },
1484 	{ "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
1488 		{ "Select", 0, 4 },
1489 	{ "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
1490 	{ "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
1491 	{ "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
1492 	{ "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
1493 	{ "PCIE_PF_INT_CFG", 0x3140, 0 },
1497 		{ "VecBase", 0, 11 },
1498 	{ "PCIE_PF_INT_CFG2", 0x3144, 0 },
1502 	{ "PCIE_PF_INT_CFG", 0x3148, 0 },
1506 		{ "VecBase", 0, 11 },
1507 	{ "PCIE_PF_INT_CFG2", 0x314c, 0 },
1511 	{ "PCIE_PF_INT_CFG", 0x3150, 0 },
1515 		{ "VecBase", 0, 11 },
1516 	{ "PCIE_PF_INT_CFG2", 0x3154, 0 },
1520 	{ "PCIE_PF_INT_CFG", 0x3158, 0 },
1524 		{ "VecBase", 0, 11 },
1525 	{ "PCIE_PF_INT_CFG2", 0x315c, 0 },
1529 	{ "PCIE_PF_INT_CFG", 0x3160, 0 },
1533 		{ "VecBase", 0, 11 },
1534 	{ "PCIE_PF_INT_CFG2", 0x3164, 0 },
1538 	{ "PCIE_PF_INT_CFG", 0x3168, 0 },
1542 		{ "VecBase", 0, 11 },
1543 	{ "PCIE_PF_INT_CFG2", 0x316c, 0 },
1547 	{ "PCIE_PF_INT_CFG", 0x3170, 0 },
1551 		{ "VecBase", 0, 11 },
1552 	{ "PCIE_PF_INT_CFG2", 0x3174, 0 },
1556 	{ "PCIE_PF_INT_CFG", 0x3178, 0 },
1560 		{ "VecBase", 0, 11 },
1561 	{ "PCIE_PF_INT_CFG2", 0x317c, 0 },
1565 	{ "PCIE_VF_INT_CFG", 0x3180, 0 },
1567 		{ "VecBase", 0, 11 },
1568 	{ "PCIE_VF_INT_CFG2", 0x3184, 0 },
1572 	{ "PCIE_VF_INT_CFG", 0x3188, 0 },
1574 		{ "VecBase", 0, 11 },
1575 	{ "PCIE_VF_INT_CFG2", 0x318c, 0 },
1579 	{ "PCIE_VF_INT_CFG", 0x3190, 0 },
1581 		{ "VecBase", 0, 11 },
1582 	{ "PCIE_VF_INT_CFG2", 0x3194, 0 },
1586 	{ "PCIE_VF_INT_CFG", 0x3198, 0 },
1588 		{ "VecBase", 0, 11 },
1589 	{ "PCIE_VF_INT_CFG2", 0x319c, 0 },
1593 	{ "PCIE_VF_INT_CFG", 0x31a0, 0 },
1595 		{ "VecBase", 0, 11 },
1596 	{ "PCIE_VF_INT_CFG2", 0x31a4, 0 },
1600 	{ "PCIE_VF_INT_CFG", 0x31a8, 0 },
1602 		{ "VecBase", 0, 11 },
1603 	{ "PCIE_VF_INT_CFG2", 0x31ac, 0 },
1607 	{ "PCIE_VF_INT_CFG", 0x31b0, 0 },
1609 		{ "VecBase", 0, 11 },
1610 	{ "PCIE_VF_INT_CFG2", 0x31b4, 0 },
1614 	{ "PCIE_VF_INT_CFG", 0x31b8, 0 },
1616 		{ "VecBase", 0, 11 },
1617 	{ "PCIE_VF_INT_CFG2", 0x31bc, 0 },
1621 	{ "PCIE_VF_INT_CFG", 0x31c0, 0 },
1623 		{ "VecBase", 0, 11 },
1624 	{ "PCIE_VF_INT_CFG2", 0x31c4, 0 },
1628 	{ "PCIE_VF_INT_CFG", 0x31c8, 0 },
1630 		{ "VecBase", 0, 11 },
1631 	{ "PCIE_VF_INT_CFG2", 0x31cc, 0 },
1635 	{ "PCIE_VF_INT_CFG", 0x31d0, 0 },
1637 		{ "VecBase", 0, 11 },
1638 	{ "PCIE_VF_INT_CFG2", 0x31d4, 0 },
1642 	{ "PCIE_VF_INT_CFG", 0x31d8, 0 },
1644 		{ "VecBase", 0, 11 },
1645 	{ "PCIE_VF_INT_CFG2", 0x31dc, 0 },
1649 	{ "PCIE_VF_INT_CFG", 0x31e0, 0 },
1651 		{ "VecBase", 0, 11 },
1652 	{ "PCIE_VF_INT_CFG2", 0x31e4, 0 },
1656 	{ "PCIE_VF_INT_CFG", 0x31e8, 0 },
1658 		{ "VecBase", 0, 11 },
1659 	{ "PCIE_VF_INT_CFG2", 0x31ec, 0 },
1663 	{ "PCIE_VF_INT_CFG", 0x31f0, 0 },
1665 		{ "VecBase", 0, 11 },
1666 	{ "PCIE_VF_INT_CFG2", 0x31f4, 0 },
1670 	{ "PCIE_VF_INT_CFG", 0x31f8, 0 },
1672 		{ "VecBase", 0, 11 },
1673 	{ "PCIE_VF_INT_CFG2", 0x31fc, 0 },
1677 	{ "PCIE_VF_INT_CFG", 0x3200, 0 },
1679 		{ "VecBase", 0, 11 },
1680 	{ "PCIE_VF_INT_CFG2", 0x3204, 0 },
1684 	{ "PCIE_VF_INT_CFG", 0x3208, 0 },
1686 		{ "VecBase", 0, 11 },
1687 	{ "PCIE_VF_INT_CFG2", 0x320c, 0 },
1691 	{ "PCIE_VF_INT_CFG", 0x3210, 0 },
1693 		{ "VecBase", 0, 11 },
1694 	{ "PCIE_VF_INT_CFG2", 0x3214, 0 },
1698 	{ "PCIE_VF_INT_CFG", 0x3218, 0 },
1700 		{ "VecBase", 0, 11 },
1701 	{ "PCIE_VF_INT_CFG2", 0x321c, 0 },
1705 	{ "PCIE_VF_INT_CFG", 0x3220, 0 },
1707 		{ "VecBase", 0, 11 },
1708 	{ "PCIE_VF_INT_CFG2", 0x3224, 0 },
1712 	{ "PCIE_VF_INT_CFG", 0x3228, 0 },
1714 		{ "VecBase", 0, 11 },
1715 	{ "PCIE_VF_INT_CFG2", 0x322c, 0 },
1719 	{ "PCIE_VF_INT_CFG", 0x3230, 0 },
1721 		{ "VecBase", 0, 11 },
1722 	{ "PCIE_VF_INT_CFG2", 0x3234, 0 },
1726 	{ "PCIE_VF_INT_CFG", 0x3238, 0 },
1728 		{ "VecBase", 0, 11 },
1729 	{ "PCIE_VF_INT_CFG2", 0x323c, 0 },
1733 	{ "PCIE_VF_INT_CFG", 0x3240, 0 },
1735 		{ "VecBase", 0, 11 },
1736 	{ "PCIE_VF_INT_CFG2", 0x3244, 0 },
1740 	{ "PCIE_VF_INT_CFG", 0x3248, 0 },
1742 		{ "VecBase", 0, 11 },
1743 	{ "PCIE_VF_INT_CFG2", 0x324c, 0 },
1747 	{ "PCIE_VF_INT_CFG", 0x3250, 0 },
1749 		{ "VecBase", 0, 11 },
1750 	{ "PCIE_VF_INT_CFG2", 0x3254, 0 },
1754 	{ "PCIE_VF_INT_CFG", 0x3258, 0 },
1756 		{ "VecBase", 0, 11 },
1757 	{ "PCIE_VF_INT_CFG2", 0x325c, 0 },
1761 	{ "PCIE_VF_INT_CFG", 0x3260, 0 },
1763 		{ "VecBase", 0, 11 },
1764 	{ "PCIE_VF_INT_CFG2", 0x3264, 0 },
1768 	{ "PCIE_VF_INT_CFG", 0x3268, 0 },
1770 		{ "VecBase", 0, 11 },
1771 	{ "PCIE_VF_INT_CFG2", 0x326c, 0 },
1775 	{ "PCIE_VF_INT_CFG", 0x3270, 0 },
1777 		{ "VecBase", 0, 11 },
1778 	{ "PCIE_VF_INT_CFG2", 0x3274, 0 },
1782 	{ "PCIE_VF_INT_CFG", 0x3278, 0 },
1784 		{ "VecBase", 0, 11 },
1785 	{ "PCIE_VF_INT_CFG2", 0x327c, 0 },
1789 	{ "PCIE_VF_INT_CFG", 0x3280, 0 },
1791 		{ "VecBase", 0, 11 },
1792 	{ "PCIE_VF_INT_CFG2", 0x3284, 0 },
1796 	{ "PCIE_VF_INT_CFG", 0x3288, 0 },
1798 		{ "VecBase", 0, 11 },
1799 	{ "PCIE_VF_INT_CFG2", 0x328c, 0 },
1803 	{ "PCIE_VF_INT_CFG", 0x3290, 0 },
1805 		{ "VecBase", 0, 11 },
1806 	{ "PCIE_VF_INT_CFG2", 0x3294, 0 },
1810 	{ "PCIE_VF_INT_CFG", 0x3298, 0 },
1812 		{ "VecBase", 0, 11 },
1813 	{ "PCIE_VF_INT_CFG2", 0x329c, 0 },
1817 	{ "PCIE_VF_INT_CFG", 0x32a0, 0 },
1819 		{ "VecBase", 0, 11 },
1820 	{ "PCIE_VF_INT_CFG2", 0x32a4, 0 },
1824 	{ "PCIE_VF_INT_CFG", 0x32a8, 0 },
1826 		{ "VecBase", 0, 11 },
1827 	{ "PCIE_VF_INT_CFG2", 0x32ac, 0 },
1831 	{ "PCIE_VF_INT_CFG", 0x32b0, 0 },
1833 		{ "VecBase", 0, 11 },
1834 	{ "PCIE_VF_INT_CFG2", 0x32b4, 0 },
1838 	{ "PCIE_VF_INT_CFG", 0x32b8, 0 },
1840 		{ "VecBase", 0, 11 },
1841 	{ "PCIE_VF_INT_CFG2", 0x32bc, 0 },
1845 	{ "PCIE_VF_INT_CFG", 0x32c0, 0 },
1847 		{ "VecBase", 0, 11 },
1848 	{ "PCIE_VF_INT_CFG2", 0x32c4, 0 },
1852 	{ "PCIE_VF_INT_CFG", 0x32c8, 0 },
1854 		{ "VecBase", 0, 11 },
1855 	{ "PCIE_VF_INT_CFG2", 0x32cc, 0 },
1859 	{ "PCIE_VF_INT_CFG", 0x32d0, 0 },
1861 		{ "VecBase", 0, 11 },
1862 	{ "PCIE_VF_INT_CFG2", 0x32d4, 0 },
1866 	{ "PCIE_VF_INT_CFG", 0x32d8, 0 },
1868 		{ "VecBase", 0, 11 },
1869 	{ "PCIE_VF_INT_CFG2", 0x32dc, 0 },
1873 	{ "PCIE_VF_INT_CFG", 0x32e0, 0 },
1875 		{ "VecBase", 0, 11 },
1876 	{ "PCIE_VF_INT_CFG2", 0x32e4, 0 },
1880 	{ "PCIE_VF_INT_CFG", 0x32e8, 0 },
1882 		{ "VecBase", 0, 11 },
1883 	{ "PCIE_VF_INT_CFG2", 0x32ec, 0 },
1887 	{ "PCIE_VF_INT_CFG", 0x32f0, 0 },
1889 		{ "VecBase", 0, 11 },
1890 	{ "PCIE_VF_INT_CFG2", 0x32f4, 0 },
1894 	{ "PCIE_VF_INT_CFG", 0x32f8, 0 },
1896 		{ "VecBase", 0, 11 },
1897 	{ "PCIE_VF_INT_CFG2", 0x32fc, 0 },
1901 	{ "PCIE_VF_INT_CFG", 0x3300, 0 },
1903 		{ "VecBase", 0, 11 },
1904 	{ "PCIE_VF_INT_CFG2", 0x3304, 0 },
1908 	{ "PCIE_VF_INT_CFG", 0x3308, 0 },
1910 		{ "VecBase", 0, 11 },
1911 	{ "PCIE_VF_INT_CFG2", 0x330c, 0 },
1915 	{ "PCIE_VF_INT_CFG", 0x3310, 0 },
1917 		{ "VecBase", 0, 11 },
1918 	{ "PCIE_VF_INT_CFG2", 0x3314, 0 },
1922 	{ "PCIE_VF_INT_CFG", 0x3318, 0 },
1924 		{ "VecBase", 0, 11 },
1925 	{ "PCIE_VF_INT_CFG2", 0x331c, 0 },
1929 	{ "PCIE_VF_INT_CFG", 0x3320, 0 },
1931 		{ "VecBase", 0, 11 },
1932 	{ "PCIE_VF_INT_CFG2", 0x3324, 0 },
1936 	{ "PCIE_VF_INT_CFG", 0x3328, 0 },
1938 		{ "VecBase", 0, 11 },
1939 	{ "PCIE_VF_INT_CFG2", 0x332c, 0 },
1943 	{ "PCIE_VF_INT_CFG", 0x3330, 0 },
1945 		{ "VecBase", 0, 11 },
1946 	{ "PCIE_VF_INT_CFG2", 0x3334, 0 },
1950 	{ "PCIE_VF_INT_CFG", 0x3338, 0 },
1952 		{ "VecBase", 0, 11 },
1953 	{ "PCIE_VF_INT_CFG2", 0x333c, 0 },
1957 	{ "PCIE_VF_INT_CFG", 0x3340, 0 },
1959 		{ "VecBase", 0, 11 },
1960 	{ "PCIE_VF_INT_CFG2", 0x3344, 0 },
1964 	{ "PCIE_VF_INT_CFG", 0x3348, 0 },
1966 		{ "VecBase", 0, 11 },
1967 	{ "PCIE_VF_INT_CFG2", 0x334c, 0 },
1971 	{ "PCIE_VF_INT_CFG", 0x3350, 0 },
1973 		{ "VecBase", 0, 11 },
1974 	{ "PCIE_VF_INT_CFG2", 0x3354, 0 },
1978 	{ "PCIE_VF_INT_CFG", 0x3358, 0 },
1980 		{ "VecBase", 0, 11 },
1981 	{ "PCIE_VF_INT_CFG2", 0x335c, 0 },
1985 	{ "PCIE_VF_INT_CFG", 0x3360, 0 },
1987 		{ "VecBase", 0, 11 },
1988 	{ "PCIE_VF_INT_CFG2", 0x3364, 0 },
1992 	{ "PCIE_VF_INT_CFG", 0x3368, 0 },
1994 		{ "VecBase", 0, 11 },
1995 	{ "PCIE_VF_INT_CFG2", 0x336c, 0 },
1999 	{ "PCIE_VF_INT_CFG", 0x3370, 0 },
2001 		{ "VecBase", 0, 11 },
2002 	{ "PCIE_VF_INT_CFG2", 0x3374, 0 },
2006 	{ "PCIE_VF_INT_CFG", 0x3378, 0 },
2008 		{ "VecBase", 0, 11 },
2009 	{ "PCIE_VF_INT_CFG2", 0x337c, 0 },
2013 	{ "PCIE_VF_INT_CFG", 0x3380, 0 },
2015 		{ "VecBase", 0, 11 },
2016 	{ "PCIE_VF_INT_CFG2", 0x3384, 0 },
2020 	{ "PCIE_VF_INT_CFG", 0x3388, 0 },
2022 		{ "VecBase", 0, 11 },
2023 	{ "PCIE_VF_INT_CFG2", 0x338c, 0 },
2027 	{ "PCIE_VF_INT_CFG", 0x3390, 0 },
2029 		{ "VecBase", 0, 11 },
2030 	{ "PCIE_VF_INT_CFG2", 0x3394, 0 },
2034 	{ "PCIE_VF_INT_CFG", 0x3398, 0 },
2036 		{ "VecBase", 0, 11 },
2037 	{ "PCIE_VF_INT_CFG2", 0x339c, 0 },
2041 	{ "PCIE_VF_INT_CFG", 0x33a0, 0 },
2043 		{ "VecBase", 0, 11 },
2044 	{ "PCIE_VF_INT_CFG2", 0x33a4, 0 },
2048 	{ "PCIE_VF_INT_CFG", 0x33a8, 0 },
2050 		{ "VecBase", 0, 11 },
2051 	{ "PCIE_VF_INT_CFG2", 0x33ac, 0 },
2055 	{ "PCIE_VF_INT_CFG", 0x33b0, 0 },
2057 		{ "VecBase", 0, 11 },
2058 	{ "PCIE_VF_INT_CFG2", 0x33b4, 0 },
2062 	{ "PCIE_VF_INT_CFG", 0x33b8, 0 },
2064 		{ "VecBase", 0, 11 },
2065 	{ "PCIE_VF_INT_CFG2", 0x33bc, 0 },
2069 	{ "PCIE_VF_INT_CFG", 0x33c0, 0 },
2071 		{ "VecBase", 0, 11 },
2072 	{ "PCIE_VF_INT_CFG2", 0x33c4, 0 },
2076 	{ "PCIE_VF_INT_CFG", 0x33c8, 0 },
2078 		{ "VecBase", 0, 11 },
2079 	{ "PCIE_VF_INT_CFG2", 0x33cc, 0 },
2083 	{ "PCIE_VF_INT_CFG", 0x33d0, 0 },
2085 		{ "VecBase", 0, 11 },
2086 	{ "PCIE_VF_INT_CFG2", 0x33d4, 0 },
2090 	{ "PCIE_VF_INT_CFG", 0x33d8, 0 },
2092 		{ "VecBase", 0, 11 },
2093 	{ "PCIE_VF_INT_CFG2", 0x33dc, 0 },
2097 	{ "PCIE_VF_INT_CFG", 0x33e0, 0 },
2099 		{ "VecBase", 0, 11 },
2100 	{ "PCIE_VF_INT_CFG2", 0x33e4, 0 },
2104 	{ "PCIE_VF_INT_CFG", 0x33e8, 0 },
2106 		{ "VecBase", 0, 11 },
2107 	{ "PCIE_VF_INT_CFG2", 0x33ec, 0 },
2111 	{ "PCIE_VF_INT_CFG", 0x33f0, 0 },
2113 		{ "VecBase", 0, 11 },
2114 	{ "PCIE_VF_INT_CFG2", 0x33f4, 0 },
2118 	{ "PCIE_VF_INT_CFG", 0x33f8, 0 },
2120 		{ "VecBase", 0, 11 },
2121 	{ "PCIE_VF_INT_CFG2", 0x33fc, 0 },
2125 	{ "PCIE_VF_INT_CFG", 0x3400, 0 },
2127 		{ "VecBase", 0, 11 },
2128 	{ "PCIE_VF_INT_CFG2", 0x3404, 0 },
2132 	{ "PCIE_VF_INT_CFG", 0x3408, 0 },
2134 		{ "VecBase", 0, 11 },
2135 	{ "PCIE_VF_INT_CFG2", 0x340c, 0 },
2139 	{ "PCIE_VF_INT_CFG", 0x3410, 0 },
2141 		{ "VecBase", 0, 11 },
2142 	{ "PCIE_VF_INT_CFG2", 0x3414, 0 },
2146 	{ "PCIE_VF_INT_CFG", 0x3418, 0 },
2148 		{ "VecBase", 0, 11 },
2149 	{ "PCIE_VF_INT_CFG2", 0x341c, 0 },
2153 	{ "PCIE_VF_INT_CFG", 0x3420, 0 },
2155 		{ "VecBase", 0, 11 },
2156 	{ "PCIE_VF_INT_CFG2", 0x3424, 0 },
2160 	{ "PCIE_VF_INT_CFG", 0x3428, 0 },
2162 		{ "VecBase", 0, 11 },
2163 	{ "PCIE_VF_INT_CFG2", 0x342c, 0 },
2167 	{ "PCIE_VF_INT_CFG", 0x3430, 0 },
2169 		{ "VecBase", 0, 11 },
2170 	{ "PCIE_VF_INT_CFG2", 0x3434, 0 },
2174 	{ "PCIE_VF_INT_CFG", 0x3438, 0 },
2176 		{ "VecBase", 0, 11 },
2177 	{ "PCIE_VF_INT_CFG2", 0x343c, 0 },
2181 	{ "PCIE_VF_INT_CFG", 0x3440, 0 },
2183 		{ "VecBase", 0, 11 },
2184 	{ "PCIE_VF_INT_CFG2", 0x3444, 0 },
2188 	{ "PCIE_VF_INT_CFG", 0x3448, 0 },
2190 		{ "VecBase", 0, 11 },
2191 	{ "PCIE_VF_INT_CFG2", 0x344c, 0 },
2195 	{ "PCIE_VF_INT_CFG", 0x3450, 0 },
2197 		{ "VecBase", 0, 11 },
2198 	{ "PCIE_VF_INT_CFG2", 0x3454, 0 },
2202 	{ "PCIE_VF_INT_CFG", 0x3458, 0 },
2204 		{ "VecBase", 0, 11 },
2205 	{ "PCIE_VF_INT_CFG2", 0x345c, 0 },
2209 	{ "PCIE_VF_INT_CFG", 0x3460, 0 },
2211 		{ "VecBase", 0, 11 },
2212 	{ "PCIE_VF_INT_CFG2", 0x3464, 0 },
2216 	{ "PCIE_VF_INT_CFG", 0x3468, 0 },
2218 		{ "VecBase", 0, 11 },
2219 	{ "PCIE_VF_INT_CFG2", 0x346c, 0 },
2223 	{ "PCIE_VF_INT_CFG", 0x3470, 0 },
2225 		{ "VecBase", 0, 11 },
2226 	{ "PCIE_VF_INT_CFG2", 0x3474, 0 },
2230 	{ "PCIE_VF_INT_CFG", 0x3478, 0 },
2232 		{ "VecBase", 0, 11 },
2233 	{ "PCIE_VF_INT_CFG2", 0x347c, 0 },
2237 	{ "PCIE_VF_INT_CFG", 0x3480, 0 },
2239 		{ "VecBase", 0, 11 },
2240 	{ "PCIE_VF_INT_CFG2", 0x3484, 0 },
2244 	{ "PCIE_VF_INT_CFG", 0x3488, 0 },
2246 		{ "VecBase", 0, 11 },
2247 	{ "PCIE_VF_INT_CFG2", 0x348c, 0 },
2251 	{ "PCIE_VF_INT_CFG", 0x3490, 0 },
2253 		{ "VecBase", 0, 11 },
2254 	{ "PCIE_VF_INT_CFG2", 0x3494, 0 },
2258 	{ "PCIE_VF_INT_CFG", 0x3498, 0 },
2260 		{ "VecBase", 0, 11 },
2261 	{ "PCIE_VF_INT_CFG2", 0x349c, 0 },
2265 	{ "PCIE_VF_INT_CFG", 0x34a0, 0 },
2267 		{ "VecBase", 0, 11 },
2268 	{ "PCIE_VF_INT_CFG2", 0x34a4, 0 },
2272 	{ "PCIE_VF_INT_CFG", 0x34a8, 0 },
2274 		{ "VecBase", 0, 11 },
2275 	{ "PCIE_VF_INT_CFG2", 0x34ac, 0 },
2279 	{ "PCIE_VF_INT_CFG", 0x34b0, 0 },
2281 		{ "VecBase", 0, 11 },
2282 	{ "PCIE_VF_INT_CFG2", 0x34b4, 0 },
2286 	{ "PCIE_VF_INT_CFG", 0x34b8, 0 },
2288 		{ "VecBase", 0, 11 },
2289 	{ "PCIE_VF_INT_CFG2", 0x34bc, 0 },
2293 	{ "PCIE_VF_INT_CFG", 0x34c0, 0 },
2295 		{ "VecBase", 0, 11 },
2296 	{ "PCIE_VF_INT_CFG2", 0x34c4, 0 },
2300 	{ "PCIE_VF_INT_CFG", 0x34c8, 0 },
2302 		{ "VecBase", 0, 11 },
2303 	{ "PCIE_VF_INT_CFG2", 0x34cc, 0 },
2307 	{ "PCIE_VF_INT_CFG", 0x34d0, 0 },
2309 		{ "VecBase", 0, 11 },
2310 	{ "PCIE_VF_INT_CFG2", 0x34d4, 0 },
2314 	{ "PCIE_VF_INT_CFG", 0x34d8, 0 },
2316 		{ "VecBase", 0, 11 },
2317 	{ "PCIE_VF_INT_CFG2", 0x34dc, 0 },
2321 	{ "PCIE_VF_INT_CFG", 0x34e0, 0 },
2323 		{ "VecBase", 0, 11 },
2324 	{ "PCIE_VF_INT_CFG2", 0x34e4, 0 },
2328 	{ "PCIE_VF_INT_CFG", 0x34e8, 0 },
2330 		{ "VecBase", 0, 11 },
2331 	{ "PCIE_VF_INT_CFG2", 0x34ec, 0 },
2335 	{ "PCIE_VF_INT_CFG", 0x34f0, 0 },
2337 		{ "VecBase", 0, 11 },
2338 	{ "PCIE_VF_INT_CFG2", 0x34f4, 0 },
2342 	{ "PCIE_VF_INT_CFG", 0x34f8, 0 },
2344 		{ "VecBase", 0, 11 },
2345 	{ "PCIE_VF_INT_CFG2", 0x34fc, 0 },
2349 	{ "PCIE_VF_INT_CFG", 0x3500, 0 },
2351 		{ "VecBase", 0, 11 },
2352 	{ "PCIE_VF_INT_CFG2", 0x3504, 0 },
2356 	{ "PCIE_VF_INT_CFG", 0x3508, 0 },
2358 		{ "VecBase", 0, 11 },
2359 	{ "PCIE_VF_INT_CFG2", 0x350c, 0 },
2363 	{ "PCIE_VF_INT_CFG", 0x3510, 0 },
2365 		{ "VecBase", 0, 11 },
2366 	{ "PCIE_VF_INT_CFG2", 0x3514, 0 },
2370 	{ "PCIE_VF_INT_CFG", 0x3518, 0 },
2372 		{ "VecBase", 0, 11 },
2373 	{ "PCIE_VF_INT_CFG2", 0x351c, 0 },
2377 	{ "PCIE_VF_INT_CFG", 0x3520, 0 },
2379 		{ "VecBase", 0, 11 },
2380 	{ "PCIE_VF_INT_CFG2", 0x3524, 0 },
2384 	{ "PCIE_VF_INT_CFG", 0x3528, 0 },
2386 		{ "VecBase", 0, 11 },
2387 	{ "PCIE_VF_INT_CFG2", 0x352c, 0 },
2391 	{ "PCIE_VF_INT_CFG", 0x3530, 0 },
2393 		{ "VecBase", 0, 11 },
2394 	{ "PCIE_VF_INT_CFG2", 0x3534, 0 },
2398 	{ "PCIE_VF_INT_CFG", 0x3538, 0 },
2400 		{ "VecBase", 0, 11 },
2401 	{ "PCIE_VF_INT_CFG2", 0x353c, 0 },
2405 	{ "PCIE_VF_INT_CFG", 0x3540, 0 },
2407 		{ "VecBase", 0, 11 },
2408 	{ "PCIE_VF_INT_CFG2", 0x3544, 0 },
2412 	{ "PCIE_VF_INT_CFG", 0x3548, 0 },
2414 		{ "VecBase", 0, 11 },
2415 	{ "PCIE_VF_INT_CFG2", 0x354c, 0 },
2419 	{ "PCIE_VF_INT_CFG", 0x3550, 0 },
2421 		{ "VecBase", 0, 11 },
2422 	{ "PCIE_VF_INT_CFG2", 0x3554, 0 },
2426 	{ "PCIE_VF_INT_CFG", 0x3558, 0 },
2428 		{ "VecBase", 0, 11 },
2429 	{ "PCIE_VF_INT_CFG2", 0x355c, 0 },
2433 	{ "PCIE_VF_INT_CFG", 0x3560, 0 },
2435 		{ "VecBase", 0, 11 },
2436 	{ "PCIE_VF_INT_CFG2", 0x3564, 0 },
2440 	{ "PCIE_VF_INT_CFG", 0x3568, 0 },
2442 		{ "VecBase", 0, 11 },
2443 	{ "PCIE_VF_INT_CFG2", 0x356c, 0 },
2447 	{ "PCIE_VF_INT_CFG", 0x3570, 0 },
2449 		{ "VecBase", 0, 11 },
2450 	{ "PCIE_VF_INT_CFG2", 0x3574, 0 },
2454 	{ "PCIE_VF_INT_CFG", 0x3578, 0 },
2456 		{ "VecBase", 0, 11 },
2457 	{ "PCIE_VF_INT_CFG2", 0x357c, 0 },
2461 	{ "PCIE_PF_MSI_EN", 0x35a8, 0 },
2462 	{ "PCIE_VF_MSI_EN_0", 0x35ac, 0 },
2463 	{ "PCIE_VF_MSI_EN_1", 0x35b0, 0 },
2464 	{ "PCIE_VF_MSI_EN_2", 0x35b4, 0 },
2465 	{ "PCIE_VF_MSI_EN_3", 0x35b8, 0 },
2466 	{ "PCIE_PF_MSIX_EN", 0x35bc, 0 },
2467 	{ "PCIE_VF_MSIX_EN_0", 0x35c0, 0 },
2468 	{ "PCIE_VF_MSIX_EN_1", 0x35c4, 0 },
2469 	{ "PCIE_VF_MSIX_EN_2", 0x35c8, 0 },
2470 	{ "PCIE_VF_MSIX_EN_3", 0x35cc, 0 },
2471 	{ "PCIE_FID_VFID_SEL", 0x35ec, 0 },
2472 	{ "PCIE_FID_VFID", 0x3600, 0 },
2479 		{ "RVF", 0, 8 },
2480 	{ "PCIE_FID_VFID", 0x3604, 0 },
2487 		{ "RVF", 0, 8 },
2488 	{ "PCIE_FID_VFID", 0x3608, 0 },
2495 		{ "RVF", 0, 8 },
2496 	{ "PCIE_FID_VFID", 0x360c, 0 },
2503 		{ "RVF", 0, 8 },
2504 	{ "PCIE_FID_VFID", 0x3610, 0 },
2511 		{ "RVF", 0, 8 },
2512 	{ "PCIE_FID_VFID", 0x3614, 0 },
2519 		{ "RVF", 0, 8 },
2520 	{ "PCIE_FID_VFID", 0x3618, 0 },
2527 		{ "RVF", 0, 8 },
2528 	{ "PCIE_FID_VFID", 0x361c, 0 },
2535 		{ "RVF", 0, 8 },
2536 	{ "PCIE_FID_VFID", 0x3620, 0 },
2543 		{ "RVF", 0, 8 },
2544 	{ "PCIE_FID_VFID", 0x3624, 0 },
2551 		{ "RVF", 0, 8 },
2552 	{ "PCIE_FID_VFID", 0x3628, 0 },
2559 		{ "RVF", 0, 8 },
2560 	{ "PCIE_FID_VFID", 0x362c, 0 },
2567 		{ "RVF", 0, 8 },
2568 	{ "PCIE_FID_VFID", 0x3630, 0 },
2575 		{ "RVF", 0, 8 },
2576 	{ "PCIE_FID_VFID", 0x3634, 0 },
2583 		{ "RVF", 0, 8 },
2584 	{ "PCIE_FID_VFID", 0x3638, 0 },
2591 		{ "RVF", 0, 8 },
2592 	{ "PCIE_FID_VFID", 0x363c, 0 },
2599 		{ "RVF", 0, 8 },
2600 	{ "PCIE_FID_VFID", 0x3640, 0 },
2607 		{ "RVF", 0, 8 },
2608 	{ "PCIE_FID_VFID", 0x3644, 0 },
2615 		{ "RVF", 0, 8 },
2616 	{ "PCIE_FID_VFID", 0x3648, 0 },
2623 		{ "RVF", 0, 8 },
2624 	{ "PCIE_FID_VFID", 0x364c, 0 },
2631 		{ "RVF", 0, 8 },
2632 	{ "PCIE_FID_VFID", 0x3650, 0 },
2639 		{ "RVF", 0, 8 },
2640 	{ "PCIE_FID_VFID", 0x3654, 0 },
2647 		{ "RVF", 0, 8 },
2648 	{ "PCIE_FID_VFID", 0x3658, 0 },
2655 		{ "RVF", 0, 8 },
2656 	{ "PCIE_FID_VFID", 0x365c, 0 },
2663 		{ "RVF", 0, 8 },
2664 	{ "PCIE_FID_VFID", 0x3660, 0 },
2671 		{ "RVF", 0, 8 },
2672 	{ "PCIE_FID_VFID", 0x3664, 0 },
2679 		{ "RVF", 0, 8 },
2680 	{ "PCIE_FID_VFID", 0x3668, 0 },
2687 		{ "RVF", 0, 8 },
2688 	{ "PCIE_FID_VFID", 0x366c, 0 },
2695 		{ "RVF", 0, 8 },
2696 	{ "PCIE_FID_VFID", 0x3670, 0 },
2703 		{ "RVF", 0, 8 },
2704 	{ "PCIE_FID_VFID", 0x3674, 0 },
2711 		{ "RVF", 0, 8 },
2712 	{ "PCIE_FID_VFID", 0x3678, 0 },
2719 		{ "RVF", 0, 8 },
2720 	{ "PCIE_FID_VFID", 0x367c, 0 },
2727 		{ "RVF", 0, 8 },
2728 	{ "PCIE_FID_VFID", 0x3680, 0 },
2735 		{ "RVF", 0, 8 },
2736 	{ "PCIE_FID_VFID", 0x3684, 0 },
2743 		{ "RVF", 0, 8 },
2744 	{ "PCIE_FID_VFID", 0x3688, 0 },
2751 		{ "RVF", 0, 8 },
2752 	{ "PCIE_FID_VFID", 0x368c, 0 },
2759 		{ "RVF", 0, 8 },
2760 	{ "PCIE_FID_VFID", 0x3690, 0 },
2767 		{ "RVF", 0, 8 },
2768 	{ "PCIE_FID_VFID", 0x3694, 0 },
2775 		{ "RVF", 0, 8 },
2776 	{ "PCIE_FID_VFID", 0x3698, 0 },
2783 		{ "RVF", 0, 8 },
2784 	{ "PCIE_FID_VFID", 0x369c, 0 },
2791 		{ "RVF", 0, 8 },
2792 	{ "PCIE_FID_VFID", 0x36a0, 0 },
2799 		{ "RVF", 0, 8 },
2800 	{ "PCIE_FID_VFID", 0x36a4, 0 },
2807 		{ "RVF", 0, 8 },
2808 	{ "PCIE_FID_VFID", 0x36a8, 0 },
2815 		{ "RVF", 0, 8 },
2816 	{ "PCIE_FID_VFID", 0x36ac, 0 },
2823 		{ "RVF", 0, 8 },
2824 	{ "PCIE_FID_VFID", 0x36b0, 0 },
2831 		{ "RVF", 0, 8 },
2832 	{ "PCIE_FID_VFID", 0x36b4, 0 },
2839 		{ "RVF", 0, 8 },
2840 	{ "PCIE_FID_VFID", 0x36b8, 0 },
2847 		{ "RVF", 0, 8 },
2848 	{ "PCIE_FID_VFID", 0x36bc, 0 },
2855 		{ "RVF", 0, 8 },
2856 	{ "PCIE_FID_VFID", 0x36c0, 0 },
2863 		{ "RVF", 0, 8 },
2864 	{ "PCIE_FID_VFID", 0x36c4, 0 },
2871 		{ "RVF", 0, 8 },
2872 	{ "PCIE_FID_VFID", 0x36c8, 0 },
2879 		{ "RVF", 0, 8 },
2880 	{ "PCIE_FID_VFID", 0x36cc, 0 },
2887 		{ "RVF", 0, 8 },
2888 	{ "PCIE_FID_VFID", 0x36d0, 0 },
2895 		{ "RVF", 0, 8 },
2896 	{ "PCIE_FID_VFID", 0x36d4, 0 },
2903 		{ "RVF", 0, 8 },
2904 	{ "PCIE_FID_VFID", 0x36d8, 0 },
2911 		{ "RVF", 0, 8 },
2912 	{ "PCIE_FID_VFID", 0x36dc, 0 },
2919 		{ "RVF", 0, 8 },
2920 	{ "PCIE_FID_VFID", 0x36e0, 0 },
2927 		{ "RVF", 0, 8 },
2928 	{ "PCIE_FID_VFID", 0x36e4, 0 },
2935 		{ "RVF", 0, 8 },
2936 	{ "PCIE_FID_VFID", 0x36e8, 0 },
2943 		{ "RVF", 0, 8 },
2944 	{ "PCIE_FID_VFID", 0x36ec, 0 },
2951 		{ "RVF", 0, 8 },
2952 	{ "PCIE_FID_VFID", 0x36f0, 0 },
2959 		{ "RVF", 0, 8 },
2960 	{ "PCIE_FID_VFID", 0x36f4, 0 },
2967 		{ "RVF", 0, 8 },
2968 	{ "PCIE_FID_VFID", 0x36f8, 0 },
2975 		{ "RVF", 0, 8 },
2976 	{ "PCIE_FID_VFID", 0x36fc, 0 },
2983 		{ "RVF", 0, 8 },
2984 	{ "PCIE_FID_VFID", 0x3700, 0 },
2991 		{ "RVF", 0, 8 },
2992 	{ "PCIE_FID_VFID", 0x3704, 0 },
2999 		{ "RVF", 0, 8 },
3000 	{ "PCIE_FID_VFID", 0x3708, 0 },
3007 		{ "RVF", 0, 8 },
3008 	{ "PCIE_FID_VFID", 0x370c, 0 },
3015 		{ "RVF", 0, 8 },
3016 	{ "PCIE_FID_VFID", 0x3710, 0 },
3023 		{ "RVF", 0, 8 },
3024 	{ "PCIE_FID_VFID", 0x3714, 0 },
3031 		{ "RVF", 0, 8 },
3032 	{ "PCIE_FID_VFID", 0x3718, 0 },
3039 		{ "RVF", 0, 8 },
3040 	{ "PCIE_FID_VFID", 0x371c, 0 },
3047 		{ "RVF", 0, 8 },
3048 	{ "PCIE_FID_VFID", 0x3720, 0 },
3055 		{ "RVF", 0, 8 },
3056 	{ "PCIE_FID_VFID", 0x3724, 0 },
3063 		{ "RVF", 0, 8 },
3064 	{ "PCIE_FID_VFID", 0x3728, 0 },
3071 		{ "RVF", 0, 8 },
3072 	{ "PCIE_FID_VFID", 0x372c, 0 },
3079 		{ "RVF", 0, 8 },
3080 	{ "PCIE_FID_VFID", 0x3730, 0 },
3087 		{ "RVF", 0, 8 },
3088 	{ "PCIE_FID_VFID", 0x3734, 0 },
3095 		{ "RVF", 0, 8 },
3096 	{ "PCIE_FID_VFID", 0x3738, 0 },
3103 		{ "RVF", 0, 8 },
3104 	{ "PCIE_FID_VFID", 0x373c, 0 },
3111 		{ "RVF", 0, 8 },
3112 	{ "PCIE_FID_VFID", 0x3740, 0 },
3119 		{ "RVF", 0, 8 },
3120 	{ "PCIE_FID_VFID", 0x3744, 0 },
3127 		{ "RVF", 0, 8 },
3128 	{ "PCIE_FID_VFID", 0x3748, 0 },
3135 		{ "RVF", 0, 8 },
3136 	{ "PCIE_FID_VFID", 0x374c, 0 },
3143 		{ "RVF", 0, 8 },
3144 	{ "PCIE_FID_VFID", 0x3750, 0 },
3151 		{ "RVF", 0, 8 },
3152 	{ "PCIE_FID_VFID", 0x3754, 0 },
3159 		{ "RVF", 0, 8 },
3160 	{ "PCIE_FID_VFID", 0x3758, 0 },
3167 		{ "RVF", 0, 8 },
3168 	{ "PCIE_FID_VFID", 0x375c, 0 },
3175 		{ "RVF", 0, 8 },
3176 	{ "PCIE_FID_VFID", 0x3760, 0 },
3183 		{ "RVF", 0, 8 },
3184 	{ "PCIE_FID_VFID", 0x3764, 0 },
3191 		{ "RVF", 0, 8 },
3192 	{ "PCIE_FID_VFID", 0x3768, 0 },
3199 		{ "RVF", 0, 8 },
3200 	{ "PCIE_FID_VFID", 0x376c, 0 },
3207 		{ "RVF", 0, 8 },
3208 	{ "PCIE_FID_VFID", 0x3770, 0 },
3215 		{ "RVF", 0, 8 },
3216 	{ "PCIE_FID_VFID", 0x3774, 0 },
3223 		{ "RVF", 0, 8 },
3224 	{ "PCIE_FID_VFID", 0x3778, 0 },
3231 		{ "RVF", 0, 8 },
3232 	{ "PCIE_FID_VFID", 0x377c, 0 },
3239 		{ "RVF", 0, 8 },
3240 	{ "PCIE_FID_VFID", 0x3780, 0 },
3247 		{ "RVF", 0, 8 },
3248 	{ "PCIE_FID_VFID", 0x3784, 0 },
3255 		{ "RVF", 0, 8 },
3256 	{ "PCIE_FID_VFID", 0x3788, 0 },
3263 		{ "RVF", 0, 8 },
3264 	{ "PCIE_FID_VFID", 0x378c, 0 },
3271 		{ "RVF", 0, 8 },
3272 	{ "PCIE_FID_VFID", 0x3790, 0 },
3279 		{ "RVF", 0, 8 },
3280 	{ "PCIE_FID_VFID", 0x3794, 0 },
3287 		{ "RVF", 0, 8 },
3288 	{ "PCIE_FID_VFID", 0x3798, 0 },
3295 		{ "RVF", 0, 8 },
3296 	{ "PCIE_FID_VFID", 0x379c, 0 },
3303 		{ "RVF", 0, 8 },
3304 	{ "PCIE_FID_VFID", 0x37a0, 0 },
3311 		{ "RVF", 0, 8 },
3312 	{ "PCIE_FID_VFID", 0x37a4, 0 },
3319 		{ "RVF", 0, 8 },
3320 	{ "PCIE_FID_VFID", 0x37a8, 0 },
3327 		{ "RVF", 0, 8 },
3328 	{ "PCIE_FID_VFID", 0x37ac, 0 },
3335 		{ "RVF", 0, 8 },
3336 	{ "PCIE_FID_VFID", 0x37b0, 0 },
3343 		{ "RVF", 0, 8 },
3344 	{ "PCIE_FID_VFID", 0x37b4, 0 },
3351 		{ "RVF", 0, 8 },
3352 	{ "PCIE_FID_VFID", 0x37b8, 0 },
3359 		{ "RVF", 0, 8 },
3360 	{ "PCIE_FID_VFID", 0x37bc, 0 },
3367 		{ "RVF", 0, 8 },
3368 	{ "PCIE_FID_VFID", 0x37c0, 0 },
3375 		{ "RVF", 0, 8 },
3376 	{ "PCIE_FID_VFID", 0x37c4, 0 },
3383 		{ "RVF", 0, 8 },
3384 	{ "PCIE_FID_VFID", 0x37c8, 0 },
3391 		{ "RVF", 0, 8 },
3392 	{ "PCIE_FID_VFID", 0x37cc, 0 },
3399 		{ "RVF", 0, 8 },
3400 	{ "PCIE_FID_VFID", 0x37d0, 0 },
3407 		{ "RVF", 0, 8 },
3408 	{ "PCIE_FID_VFID", 0x37d4, 0 },
3415 		{ "RVF", 0, 8 },
3416 	{ "PCIE_FID_VFID", 0x37d8, 0 },
3423 		{ "RVF", 0, 8 },
3424 	{ "PCIE_FID_VFID", 0x37dc, 0 },
3431 		{ "RVF", 0, 8 },
3432 	{ "PCIE_FID_VFID", 0x37e0, 0 },
3439 		{ "RVF", 0, 8 },
3440 	{ "PCIE_FID_VFID", 0x37e4, 0 },
3447 		{ "RVF", 0, 8 },
3448 	{ "PCIE_FID_VFID", 0x37e8, 0 },
3455 		{ "RVF", 0, 8 },
3456 	{ "PCIE_FID_VFID", 0x37ec, 0 },
3463 		{ "RVF", 0, 8 },
3464 	{ "PCIE_FID_VFID", 0x37f0, 0 },
3471 		{ "RVF", 0, 8 },
3472 	{ "PCIE_FID_VFID", 0x37f4, 0 },
3479 		{ "RVF", 0, 8 },
3480 	{ "PCIE_FID_VFID", 0x37f8, 0 },
3487 		{ "RVF", 0, 8 },
3488 	{ "PCIE_FID_VFID", 0x37fc, 0 },
3495 		{ "RVF", 0, 8 },
3496 	{ "PCIE_FID_VFID", 0x3800, 0 },
3503 		{ "RVF", 0, 8 },
3504 	{ "PCIE_FID_VFID", 0x3804, 0 },
3511 		{ "RVF", 0, 8 },
3512 	{ "PCIE_FID_VFID", 0x3808, 0 },
3519 		{ "RVF", 0, 8 },
3520 	{ "PCIE_FID_VFID", 0x380c, 0 },
3527 		{ "RVF", 0, 8 },
3528 	{ "PCIE_FID_VFID", 0x3810, 0 },
3535 		{ "RVF", 0, 8 },
3536 	{ "PCIE_FID_VFID", 0x3814, 0 },
3543 		{ "RVF", 0, 8 },
3544 	{ "PCIE_FID_VFID", 0x3818, 0 },
3551 		{ "RVF", 0, 8 },
3552 	{ "PCIE_FID_VFID", 0x381c, 0 },
3559 		{ "RVF", 0, 8 },
3560 	{ "PCIE_FID_VFID", 0x3820, 0 },
3567 		{ "RVF", 0, 8 },
3568 	{ "PCIE_FID_VFID", 0x3824, 0 },
3575 		{ "RVF", 0, 8 },
3576 	{ "PCIE_FID_VFID", 0x3828, 0 },
3583 		{ "RVF", 0, 8 },
3584 	{ "PCIE_FID_VFID", 0x382c, 0 },
3591 		{ "RVF", 0, 8 },
3592 	{ "PCIE_FID_VFID", 0x3830, 0 },
3599 		{ "RVF", 0, 8 },
3600 	{ "PCIE_FID_VFID", 0x3834, 0 },
3607 		{ "RVF", 0, 8 },
3608 	{ "PCIE_FID_VFID", 0x3838, 0 },
3615 		{ "RVF", 0, 8 },
3616 	{ "PCIE_FID_VFID", 0x383c, 0 },
3623 		{ "RVF", 0, 8 },
3624 	{ "PCIE_FID_VFID", 0x3840, 0 },
3631 		{ "RVF", 0, 8 },
3632 	{ "PCIE_FID_VFID", 0x3844, 0 },
3639 		{ "RVF", 0, 8 },
3640 	{ "PCIE_FID_VFID", 0x3848, 0 },
3647 		{ "RVF", 0, 8 },
3648 	{ "PCIE_FID_VFID", 0x384c, 0 },
3655 		{ "RVF", 0, 8 },
3656 	{ "PCIE_FID_VFID", 0x3850, 0 },
3663 		{ "RVF", 0, 8 },
3664 	{ "PCIE_FID_VFID", 0x3854, 0 },
3671 		{ "RVF", 0, 8 },
3672 	{ "PCIE_FID_VFID", 0x3858, 0 },
3679 		{ "RVF", 0, 8 },
3680 	{ "PCIE_FID_VFID", 0x385c, 0 },
3687 		{ "RVF", 0, 8 },
3688 	{ "PCIE_FID_VFID", 0x3860, 0 },
3695 		{ "RVF", 0, 8 },
3696 	{ "PCIE_FID_VFID", 0x3864, 0 },
3703 		{ "RVF", 0, 8 },
3704 	{ "PCIE_FID_VFID", 0x3868, 0 },
3711 		{ "RVF", 0, 8 },
3712 	{ "PCIE_FID_VFID", 0x386c, 0 },
3719 		{ "RVF", 0, 8 },
3720 	{ "PCIE_FID_VFID", 0x3870, 0 },
3727 		{ "RVF", 0, 8 },
3728 	{ "PCIE_FID_VFID", 0x3874, 0 },
3735 		{ "RVF", 0, 8 },
3736 	{ "PCIE_FID_VFID", 0x3878, 0 },
3743 		{ "RVF", 0, 8 },
3744 	{ "PCIE_FID_VFID", 0x387c, 0 },
3751 		{ "RVF", 0, 8 },
3752 	{ "PCIE_FID_VFID", 0x3880, 0 },
3759 		{ "RVF", 0, 8 },
3760 	{ "PCIE_FID_VFID", 0x3884, 0 },
3767 		{ "RVF", 0, 8 },
3768 	{ "PCIE_FID_VFID", 0x3888, 0 },
3775 		{ "RVF", 0, 8 },
3776 	{ "PCIE_FID_VFID", 0x388c, 0 },
3783 		{ "RVF", 0, 8 },
3784 	{ "PCIE_FID_VFID", 0x3890, 0 },
3791 		{ "RVF", 0, 8 },
3792 	{ "PCIE_FID_VFID", 0x3894, 0 },
3799 		{ "RVF", 0, 8 },
3800 	{ "PCIE_FID_VFID", 0x3898, 0 },
3807 		{ "RVF", 0, 8 },
3808 	{ "PCIE_FID_VFID", 0x389c, 0 },
3815 		{ "RVF", 0, 8 },
3816 	{ "PCIE_FID_VFID", 0x38a0, 0 },
3823 		{ "RVF", 0, 8 },
3824 	{ "PCIE_FID_VFID", 0x38a4, 0 },
3831 		{ "RVF", 0, 8 },
3832 	{ "PCIE_FID_VFID", 0x38a8, 0 },
3839 		{ "RVF", 0, 8 },
3840 	{ "PCIE_FID_VFID", 0x38ac, 0 },
3847 		{ "RVF", 0, 8 },
3848 	{ "PCIE_FID_VFID", 0x38b0, 0 },
3855 		{ "RVF", 0, 8 },
3856 	{ "PCIE_FID_VFID", 0x38b4, 0 },
3863 		{ "RVF", 0, 8 },
3864 	{ "PCIE_FID_VFID", 0x38b8, 0 },
3871 		{ "RVF", 0, 8 },
3872 	{ "PCIE_FID_VFID", 0x38bc, 0 },
3879 		{ "RVF", 0, 8 },
3880 	{ "PCIE_FID_VFID", 0x38c0, 0 },
3887 		{ "RVF", 0, 8 },
3888 	{ "PCIE_FID_VFID", 0x38c4, 0 },
3895 		{ "RVF", 0, 8 },
3896 	{ "PCIE_FID_VFID", 0x38c8, 0 },
3903 		{ "RVF", 0, 8 },
3904 	{ "PCIE_FID_VFID", 0x38cc, 0 },
3911 		{ "RVF", 0, 8 },
3912 	{ "PCIE_FID_VFID", 0x38d0, 0 },
3919 		{ "RVF", 0, 8 },
3920 	{ "PCIE_FID_VFID", 0x38d4, 0 },
3927 		{ "RVF", 0, 8 },
3928 	{ "PCIE_FID_VFID", 0x38d8, 0 },
3935 		{ "RVF", 0, 8 },
3936 	{ "PCIE_FID_VFID", 0x38dc, 0 },
3943 		{ "RVF", 0, 8 },
3944 	{ "PCIE_FID_VFID", 0x38e0, 0 },
3951 		{ "RVF", 0, 8 },
3952 	{ "PCIE_FID_VFID", 0x38e4, 0 },
3959 		{ "RVF", 0, 8 },
3960 	{ "PCIE_FID_VFID", 0x38e8, 0 },
3967 		{ "RVF", 0, 8 },
3968 	{ "PCIE_FID_VFID", 0x38ec, 0 },
3975 		{ "RVF", 0, 8 },
3976 	{ "PCIE_FID_VFID", 0x38f0, 0 },
3983 		{ "RVF", 0, 8 },
3984 	{ "PCIE_FID_VFID", 0x38f4, 0 },
3991 		{ "RVF", 0, 8 },
3992 	{ "PCIE_FID_VFID", 0x38f8, 0 },
3999 		{ "RVF", 0, 8 },
4000 	{ "PCIE_FID_VFID", 0x38fc, 0 },
4007 		{ "RVF", 0, 8 },
4008 	{ "PCIE_FID_VFID", 0x3900, 0 },
4015 		{ "RVF", 0, 8 },
4016 	{ "PCIE_FID_VFID", 0x3904, 0 },
4023 		{ "RVF", 0, 8 },
4024 	{ "PCIE_FID_VFID", 0x3908, 0 },
4031 		{ "RVF", 0, 8 },
4032 	{ "PCIE_FID_VFID", 0x390c, 0 },
4039 		{ "RVF", 0, 8 },
4040 	{ "PCIE_FID_VFID", 0x3910, 0 },
4047 		{ "RVF", 0, 8 },
4048 	{ "PCIE_FID_VFID", 0x3914, 0 },
4055 		{ "RVF", 0, 8 },
4056 	{ "PCIE_FID_VFID", 0x3918, 0 },
4063 		{ "RVF", 0, 8 },
4064 	{ "PCIE_FID_VFID", 0x391c, 0 },
4071 		{ "RVF", 0, 8 },
4072 	{ "PCIE_FID_VFID", 0x3920, 0 },
4079 		{ "RVF", 0, 8 },
4080 	{ "PCIE_FID_VFID", 0x3924, 0 },
4087 		{ "RVF", 0, 8 },
4088 	{ "PCIE_FID_VFID", 0x3928, 0 },
4095 		{ "RVF", 0, 8 },
4096 	{ "PCIE_FID_VFID", 0x392c, 0 },
4103 		{ "RVF", 0, 8 },
4104 	{ "PCIE_FID_VFID", 0x3930, 0 },
4111 		{ "RVF", 0, 8 },
4112 	{ "PCIE_FID_VFID", 0x3934, 0 },
4119 		{ "RVF", 0, 8 },
4120 	{ "PCIE_FID_VFID", 0x3938, 0 },
4127 		{ "RVF", 0, 8 },
4128 	{ "PCIE_FID_VFID", 0x393c, 0 },
4135 		{ "RVF", 0, 8 },
4136 	{ "PCIE_FID_VFID", 0x3940, 0 },
4143 		{ "RVF", 0, 8 },
4144 	{ "PCIE_FID_VFID", 0x3944, 0 },
4151 		{ "RVF", 0, 8 },
4152 	{ "PCIE_FID_VFID", 0x3948, 0 },
4159 		{ "RVF", 0, 8 },
4160 	{ "PCIE_FID_VFID", 0x394c, 0 },
4167 		{ "RVF", 0, 8 },
4168 	{ "PCIE_FID_VFID", 0x3950, 0 },
4175 		{ "RVF", 0, 8 },
4176 	{ "PCIE_FID_VFID", 0x3954, 0 },
4183 		{ "RVF", 0, 8 },
4184 	{ "PCIE_FID_VFID", 0x3958, 0 },
4191 		{ "RVF", 0, 8 },
4192 	{ "PCIE_FID_VFID", 0x395c, 0 },
4199 		{ "RVF", 0, 8 },
4200 	{ "PCIE_FID_VFID", 0x3960, 0 },
4207 		{ "RVF", 0, 8 },
4208 	{ "PCIE_FID_VFID", 0x3964, 0 },
4215 		{ "RVF", 0, 8 },
4216 	{ "PCIE_FID_VFID", 0x3968, 0 },
4223 		{ "RVF", 0, 8 },
4224 	{ "PCIE_FID_VFID", 0x396c, 0 },
4231 		{ "RVF", 0, 8 },
4232 	{ "PCIE_FID_VFID", 0x3970, 0 },
4239 		{ "RVF", 0, 8 },
4240 	{ "PCIE_FID_VFID", 0x3974, 0 },
4247 		{ "RVF", 0, 8 },
4248 	{ "PCIE_FID_VFID", 0x3978, 0 },
4255 		{ "RVF", 0, 8 },
4256 	{ "PCIE_FID_VFID", 0x397c, 0 },
4263 		{ "RVF", 0, 8 },
4264 	{ "PCIE_FID_VFID", 0x3980, 0 },
4271 		{ "RVF", 0, 8 },
4272 	{ "PCIE_FID_VFID", 0x3984, 0 },
4279 		{ "RVF", 0, 8 },
4280 	{ "PCIE_FID_VFID", 0x3988, 0 },
4287 		{ "RVF", 0, 8 },
4288 	{ "PCIE_FID_VFID", 0x398c, 0 },
4295 		{ "RVF", 0, 8 },
4296 	{ "PCIE_FID_VFID", 0x3990, 0 },
4303 		{ "RVF", 0, 8 },
4304 	{ "PCIE_FID_VFID", 0x3994, 0 },
4311 		{ "RVF", 0, 8 },
4312 	{ "PCIE_FID_VFID", 0x3998, 0 },
4319 		{ "RVF", 0, 8 },
4320 	{ "PCIE_FID_VFID", 0x399c, 0 },
4327 		{ "RVF", 0, 8 },
4328 	{ "PCIE_FID_VFID", 0x39a0, 0 },
4335 		{ "RVF", 0, 8 },
4336 	{ "PCIE_FID_VFID", 0x39a4, 0 },
4343 		{ "RVF", 0, 8 },
4344 	{ "PCIE_FID_VFID", 0x39a8, 0 },
4351 		{ "RVF", 0, 8 },
4352 	{ "PCIE_FID_VFID", 0x39ac, 0 },
4359 		{ "RVF", 0, 8 },
4360 	{ "PCIE_FID_VFID", 0x39b0, 0 },
4367 		{ "RVF", 0, 8 },
4368 	{ "PCIE_FID_VFID", 0x39b4, 0 },
4375 		{ "RVF", 0, 8 },
4376 	{ "PCIE_FID_VFID", 0x39b8, 0 },
4383 		{ "RVF", 0, 8 },
4384 	{ "PCIE_FID_VFID", 0x39bc, 0 },
4391 		{ "RVF", 0, 8 },
4392 	{ "PCIE_FID_VFID", 0x39c0, 0 },
4399 		{ "RVF", 0, 8 },
4400 	{ "PCIE_FID_VFID", 0x39c4, 0 },
4407 		{ "RVF", 0, 8 },
4408 	{ "PCIE_FID_VFID", 0x39c8, 0 },
4415 		{ "RVF", 0, 8 },
4416 	{ "PCIE_FID_VFID", 0x39cc, 0 },
4423 		{ "RVF", 0, 8 },
4424 	{ "PCIE_FID_VFID", 0x39d0, 0 },
4431 		{ "RVF", 0, 8 },
4432 	{ "PCIE_FID_VFID", 0x39d4, 0 },
4439 		{ "RVF", 0, 8 },
4440 	{ "PCIE_FID_VFID", 0x39d8, 0 },
4447 		{ "RVF", 0, 8 },
4448 	{ "PCIE_FID_VFID", 0x39dc, 0 },
4455 		{ "RVF", 0, 8 },
4456 	{ "PCIE_FID_VFID", 0x39e0, 0 },
4463 		{ "RVF", 0, 8 },
4464 	{ "PCIE_FID_VFID", 0x39e4, 0 },
4471 		{ "RVF", 0, 8 },
4472 	{ "PCIE_FID_VFID", 0x39e8, 0 },
4479 		{ "RVF", 0, 8 },
4480 	{ "PCIE_FID_VFID", 0x39ec, 0 },
4487 		{ "RVF", 0, 8 },
4488 	{ "PCIE_FID_VFID", 0x39f0, 0 },
4495 		{ "RVF", 0, 8 },
4496 	{ "PCIE_FID_VFID", 0x39f4, 0 },
4503 		{ "RVF", 0, 8 },
4504 	{ "PCIE_FID_VFID", 0x39f8, 0 },
4511 		{ "RVF", 0, 8 },
4512 	{ "PCIE_FID_VFID", 0x39fc, 0 },
4519 		{ "RVF", 0, 8 },
4520 	{ "PCIE_FID_VFID", 0x3a00, 0 },
4527 		{ "RVF", 0, 8 },
4528 	{ "PCIE_FID_VFID", 0x3a04, 0 },
4535 		{ "RVF", 0, 8 },
4536 	{ "PCIE_FID_VFID", 0x3a08, 0 },
4543 		{ "RVF", 0, 8 },
4544 	{ "PCIE_FID_VFID", 0x3a0c, 0 },
4551 		{ "RVF", 0, 8 },
4552 	{ "PCIE_FID_VFID", 0x3a10, 0 },
4559 		{ "RVF", 0, 8 },
4560 	{ "PCIE_FID_VFID", 0x3a14, 0 },
4567 		{ "RVF", 0, 8 },
4568 	{ "PCIE_FID_VFID", 0x3a18, 0 },
4575 		{ "RVF", 0, 8 },
4576 	{ "PCIE_FID_VFID", 0x3a1c, 0 },
4583 		{ "RVF", 0, 8 },
4584 	{ "PCIE_FID_VFID", 0x3a20, 0 },
4591 		{ "RVF", 0, 8 },
4592 	{ "PCIE_FID_VFID", 0x3a24, 0 },
4599 		{ "RVF", 0, 8 },
4600 	{ "PCIE_FID_VFID", 0x3a28, 0 },
4607 		{ "RVF", 0, 8 },
4608 	{ "PCIE_FID_VFID", 0x3a2c, 0 },
4615 		{ "RVF", 0, 8 },
4616 	{ "PCIE_FID_VFID", 0x3a30, 0 },
4623 		{ "RVF", 0, 8 },
4624 	{ "PCIE_FID_VFID", 0x3a34, 0 },
4631 		{ "RVF", 0, 8 },
4632 	{ "PCIE_FID_VFID", 0x3a38, 0 },
4639 		{ "RVF", 0, 8 },
4640 	{ "PCIE_FID_VFID", 0x3a3c, 0 },
4647 		{ "RVF", 0, 8 },
4648 	{ "PCIE_FID_VFID", 0x3a40, 0 },
4655 		{ "RVF", 0, 8 },
4656 	{ "PCIE_FID_VFID", 0x3a44, 0 },
4663 		{ "RVF", 0, 8 },
4664 	{ "PCIE_FID_VFID", 0x3a48, 0 },
4671 		{ "RVF", 0, 8 },
4672 	{ "PCIE_FID_VFID", 0x3a4c, 0 },
4679 		{ "RVF", 0, 8 },
4680 	{ "PCIE_FID_VFID", 0x3a50, 0 },
4687 		{ "RVF", 0, 8 },
4688 	{ "PCIE_FID_VFID", 0x3a54, 0 },
4695 		{ "RVF", 0, 8 },
4696 	{ "PCIE_FID_VFID", 0x3a58, 0 },
4703 		{ "RVF", 0, 8 },
4704 	{ "PCIE_FID_VFID", 0x3a5c, 0 },
4711 		{ "RVF", 0, 8 },
4712 	{ "PCIE_FID_VFID", 0x3a60, 0 },
4719 		{ "RVF", 0, 8 },
4720 	{ "PCIE_FID_VFID", 0x3a64, 0 },
4727 		{ "RVF", 0, 8 },
4728 	{ "PCIE_FID_VFID", 0x3a68, 0 },
4735 		{ "RVF", 0, 8 },
4736 	{ "PCIE_FID_VFID", 0x3a6c, 0 },
4743 		{ "RVF", 0, 8 },
4744 	{ "PCIE_FID_VFID", 0x3a70, 0 },
4751 		{ "RVF", 0, 8 },
4752 	{ "PCIE_FID_VFID", 0x3a74, 0 },
4759 		{ "RVF", 0, 8 },
4760 	{ "PCIE_FID_VFID", 0x3a78, 0 },
4767 		{ "RVF", 0, 8 },
4768 	{ "PCIE_FID_VFID", 0x3a7c, 0 },
4775 		{ "RVF", 0, 8 },
4776 	{ "PCIE_FID_VFID", 0x3a80, 0 },
4783 		{ "RVF", 0, 8 },
4784 	{ "PCIE_FID_VFID", 0x3a84, 0 },
4791 		{ "RVF", 0, 8 },
4792 	{ "PCIE_FID_VFID", 0x3a88, 0 },
4799 		{ "RVF", 0, 8 },
4800 	{ "PCIE_FID_VFID", 0x3a8c, 0 },
4807 		{ "RVF", 0, 8 },
4808 	{ "PCIE_FID_VFID", 0x3a90, 0 },
4815 		{ "RVF", 0, 8 },
4816 	{ "PCIE_FID_VFID", 0x3a94, 0 },
4823 		{ "RVF", 0, 8 },
4824 	{ "PCIE_FID_VFID", 0x3a98, 0 },
4831 		{ "RVF", 0, 8 },
4832 	{ "PCIE_FID_VFID", 0x3a9c, 0 },
4839 		{ "RVF", 0, 8 },
4840 	{ "PCIE_FID_VFID", 0x3aa0, 0 },
4847 		{ "RVF", 0, 8 },
4848 	{ "PCIE_FID_VFID", 0x3aa4, 0 },
4855 		{ "RVF", 0, 8 },
4856 	{ "PCIE_FID_VFID", 0x3aa8, 0 },
4863 		{ "RVF", 0, 8 },
4864 	{ "PCIE_FID_VFID", 0x3aac, 0 },
4871 		{ "RVF", 0, 8 },
4872 	{ "PCIE_FID_VFID", 0x3ab0, 0 },
4879 		{ "RVF", 0, 8 },
4880 	{ "PCIE_FID_VFID", 0x3ab4, 0 },
4887 		{ "RVF", 0, 8 },
4888 	{ "PCIE_FID_VFID", 0x3ab8, 0 },
4895 		{ "RVF", 0, 8 },
4896 	{ "PCIE_FID_VFID", 0x3abc, 0 },
4903 		{ "RVF", 0, 8 },
4904 	{ "PCIE_FID_VFID", 0x3ac0, 0 },
4911 		{ "RVF", 0, 8 },
4912 	{ "PCIE_FID_VFID", 0x3ac4, 0 },
4919 		{ "RVF", 0, 8 },
4920 	{ "PCIE_FID_VFID", 0x3ac8, 0 },
4927 		{ "RVF", 0, 8 },
4928 	{ "PCIE_FID_VFID", 0x3acc, 0 },
4935 		{ "RVF", 0, 8 },
4936 	{ "PCIE_FID_VFID", 0x3ad0, 0 },
4943 		{ "RVF", 0, 8 },
4944 	{ "PCIE_FID_VFID", 0x3ad4, 0 },
4951 		{ "RVF", 0, 8 },
4952 	{ "PCIE_FID_VFID", 0x3ad8, 0 },
4959 		{ "RVF", 0, 8 },
4960 	{ "PCIE_FID_VFID", 0x3adc, 0 },
4967 		{ "RVF", 0, 8 },
4968 	{ "PCIE_FID_VFID", 0x3ae0, 0 },
4975 		{ "RVF", 0, 8 },
4976 	{ "PCIE_FID_VFID", 0x3ae4, 0 },
4983 		{ "RVF", 0, 8 },
4984 	{ "PCIE_FID_VFID", 0x3ae8, 0 },
4991 		{ "RVF", 0, 8 },
4992 	{ "PCIE_FID_VFID", 0x3aec, 0 },
4999 		{ "RVF", 0, 8 },
5000 	{ "PCIE_FID_VFID", 0x3af0, 0 },
5007 		{ "RVF", 0, 8 },
5008 	{ "PCIE_FID_VFID", 0x3af4, 0 },
5015 		{ "RVF", 0, 8 },
5016 	{ "PCIE_FID_VFID", 0x3af8, 0 },
5023 		{ "RVF", 0, 8 },
5024 	{ "PCIE_FID_VFID", 0x3afc, 0 },
5031 		{ "RVF", 0, 8 },
5032 	{ "PCIE_FID_VFID", 0x3b00, 0 },
5039 		{ "RVF", 0, 8 },
5040 	{ "PCIE_FID_VFID", 0x3b04, 0 },
5047 		{ "RVF", 0, 8 },
5048 	{ "PCIE_FID_VFID", 0x3b08, 0 },
5055 		{ "RVF", 0, 8 },
5056 	{ "PCIE_FID_VFID", 0x3b0c, 0 },
5063 		{ "RVF", 0, 8 },
5064 	{ "PCIE_FID_VFID", 0x3b10, 0 },
5071 		{ "RVF", 0, 8 },
5072 	{ "PCIE_FID_VFID", 0x3b14, 0 },
5079 		{ "RVF", 0, 8 },
5080 	{ "PCIE_FID_VFID", 0x3b18, 0 },
5087 		{ "RVF", 0, 8 },
5088 	{ "PCIE_FID_VFID", 0x3b1c, 0 },
5095 		{ "RVF", 0, 8 },
5096 	{ "PCIE_FID_VFID", 0x3b20, 0 },
5103 		{ "RVF", 0, 8 },
5104 	{ "PCIE_FID_VFID", 0x3b24, 0 },
5111 		{ "RVF", 0, 8 },
5112 	{ "PCIE_FID_VFID", 0x3b28, 0 },
5119 		{ "RVF", 0, 8 },
5120 	{ "PCIE_FID_VFID", 0x3b2c, 0 },
5127 		{ "RVF", 0, 8 },
5128 	{ "PCIE_FID_VFID", 0x3b30, 0 },
5135 		{ "RVF", 0, 8 },
5136 	{ "PCIE_FID_VFID", 0x3b34, 0 },
5143 		{ "RVF", 0, 8 },
5144 	{ "PCIE_FID_VFID", 0x3b38, 0 },
5151 		{ "RVF", 0, 8 },
5152 	{ "PCIE_FID_VFID", 0x3b3c, 0 },
5159 		{ "RVF", 0, 8 },
5160 	{ "PCIE_FID_VFID", 0x3b40, 0 },
5167 		{ "RVF", 0, 8 },
5168 	{ "PCIE_FID_VFID", 0x3b44, 0 },
5175 		{ "RVF", 0, 8 },
5176 	{ "PCIE_FID_VFID", 0x3b48, 0 },
5183 		{ "RVF", 0, 8 },
5184 	{ "PCIE_FID_VFID", 0x3b4c, 0 },
5191 		{ "RVF", 0, 8 },
5192 	{ "PCIE_FID_VFID", 0x3b50, 0 },
5199 		{ "RVF", 0, 8 },
5200 	{ "PCIE_FID_VFID", 0x3b54, 0 },
5207 		{ "RVF", 0, 8 },
5208 	{ "PCIE_FID_VFID", 0x3b58, 0 },
5215 		{ "RVF", 0, 8 },
5216 	{ "PCIE_FID_VFID", 0x3b5c, 0 },
5223 		{ "RVF", 0, 8 },
5224 	{ "PCIE_FID_VFID", 0x3b60, 0 },
5231 		{ "RVF", 0, 8 },
5232 	{ "PCIE_FID_VFID", 0x3b64, 0 },
5239 		{ "RVF", 0, 8 },
5240 	{ "PCIE_FID_VFID", 0x3b68, 0 },
5247 		{ "RVF", 0, 8 },
5248 	{ "PCIE_FID_VFID", 0x3b6c, 0 },
5255 		{ "RVF", 0, 8 },
5256 	{ "PCIE_FID_VFID", 0x3b70, 0 },
5263 		{ "RVF", 0, 8 },
5264 	{ "PCIE_FID_VFID", 0x3b74, 0 },
5271 		{ "RVF", 0, 8 },
5272 	{ "PCIE_FID_VFID", 0x3b78, 0 },
5279 		{ "RVF", 0, 8 },
5280 	{ "PCIE_FID_VFID", 0x3b7c, 0 },
5287 		{ "RVF", 0, 8 },
5288 	{ "PCIE_FID_VFID", 0x3b80, 0 },
5295 		{ "RVF", 0, 8 },
5296 	{ "PCIE_FID_VFID", 0x3b84, 0 },
5303 		{ "RVF", 0, 8 },
5304 	{ "PCIE_FID_VFID", 0x3b88, 0 },
5311 		{ "RVF", 0, 8 },
5312 	{ "PCIE_FID_VFID", 0x3b8c, 0 },
5319 		{ "RVF", 0, 8 },
5320 	{ "PCIE_FID_VFID", 0x3b90, 0 },
5327 		{ "RVF", 0, 8 },
5328 	{ "PCIE_FID_VFID", 0x3b94, 0 },
5335 		{ "RVF", 0, 8 },
5336 	{ "PCIE_FID_VFID", 0x3b98, 0 },
5343 		{ "RVF", 0, 8 },
5344 	{ "PCIE_FID_VFID", 0x3b9c, 0 },
5351 		{ "RVF", 0, 8 },
5352 	{ "PCIE_FID_VFID", 0x3ba0, 0 },
5359 		{ "RVF", 0, 8 },
5360 	{ "PCIE_FID_VFID", 0x3ba4, 0 },
5367 		{ "RVF", 0, 8 },
5368 	{ "PCIE_FID_VFID", 0x3ba8, 0 },
5375 		{ "RVF", 0, 8 },
5376 	{ "PCIE_FID_VFID", 0x3bac, 0 },
5383 		{ "RVF", 0, 8 },
5384 	{ "PCIE_FID_VFID", 0x3bb0, 0 },
5391 		{ "RVF", 0, 8 },
5392 	{ "PCIE_FID_VFID", 0x3bb4, 0 },
5399 		{ "RVF", 0, 8 },
5400 	{ "PCIE_FID_VFID", 0x3bb8, 0 },
5407 		{ "RVF", 0, 8 },
5408 	{ "PCIE_FID_VFID", 0x3bbc, 0 },
5415 		{ "RVF", 0, 8 },
5416 	{ "PCIE_FID_VFID", 0x3bc0, 0 },
5423 		{ "RVF", 0, 8 },
5424 	{ "PCIE_FID_VFID", 0x3bc4, 0 },
5431 		{ "RVF", 0, 8 },
5432 	{ "PCIE_FID_VFID", 0x3bc8, 0 },
5439 		{ "RVF", 0, 8 },
5440 	{ "PCIE_FID_VFID", 0x3bcc, 0 },
5447 		{ "RVF", 0, 8 },
5448 	{ "PCIE_FID_VFID", 0x3bd0, 0 },
5455 		{ "RVF", 0, 8 },
5456 	{ "PCIE_FID_VFID", 0x3bd4, 0 },
5463 		{ "RVF", 0, 8 },
5464 	{ "PCIE_FID_VFID", 0x3bd8, 0 },
5471 		{ "RVF", 0, 8 },
5472 	{ "PCIE_FID_VFID", 0x3bdc, 0 },
5479 		{ "RVF", 0, 8 },
5480 	{ "PCIE_FID_VFID", 0x3be0, 0 },
5487 		{ "RVF", 0, 8 },
5488 	{ "PCIE_FID_VFID", 0x3be4, 0 },
5495 		{ "RVF", 0, 8 },
5496 	{ "PCIE_FID_VFID", 0x3be8, 0 },
5503 		{ "RVF", 0, 8 },
5504 	{ "PCIE_FID_VFID", 0x3bec, 0 },
5511 		{ "RVF", 0, 8 },
5512 	{ "PCIE_FID_VFID", 0x3bf0, 0 },
5519 		{ "RVF", 0, 8 },
5520 	{ "PCIE_FID_VFID", 0x3bf4, 0 },
5527 		{ "RVF", 0, 8 },
5528 	{ "PCIE_FID_VFID", 0x3bf8, 0 },
5535 		{ "RVF", 0, 8 },
5536 	{ "PCIE_FID_VFID", 0x3bfc, 0 },
5543 		{ "RVF", 0, 8 },
5544 	{ "PCIE_FID_VFID", 0x3c00, 0 },
5551 		{ "RVF", 0, 8 },
5552 	{ "PCIE_FID_VFID", 0x3c04, 0 },
5559 		{ "RVF", 0, 8 },
5560 	{ "PCIE_FID_VFID", 0x3c08, 0 },
5567 		{ "RVF", 0, 8 },
5568 	{ "PCIE_FID_VFID", 0x3c0c, 0 },
5575 		{ "RVF", 0, 8 },
5576 	{ "PCIE_FID_VFID", 0x3c10, 0 },
5583 		{ "RVF", 0, 8 },
5584 	{ "PCIE_FID_VFID", 0x3c14, 0 },
5591 		{ "RVF", 0, 8 },
5592 	{ "PCIE_FID_VFID", 0x3c18, 0 },
5599 		{ "RVF", 0, 8 },
5600 	{ "PCIE_FID_VFID", 0x3c1c, 0 },
5607 		{ "RVF", 0, 8 },
5608 	{ "PCIE_FID_VFID", 0x3c20, 0 },
5615 		{ "RVF", 0, 8 },
5616 	{ "PCIE_FID_VFID", 0x3c24, 0 },
5623 		{ "RVF", 0, 8 },
5624 	{ "PCIE_FID_VFID", 0x3c28, 0 },
5631 		{ "RVF", 0, 8 },
5632 	{ "PCIE_FID_VFID", 0x3c2c, 0 },
5639 		{ "RVF", 0, 8 },
5640 	{ "PCIE_FID_VFID", 0x3c30, 0 },
5647 		{ "RVF", 0, 8 },
5648 	{ "PCIE_FID_VFID", 0x3c34, 0 },
5655 		{ "RVF", 0, 8 },
5656 	{ "PCIE_FID_VFID", 0x3c38, 0 },
5663 		{ "RVF", 0, 8 },
5664 	{ "PCIE_FID_VFID", 0x3c3c, 0 },
5671 		{ "RVF", 0, 8 },
5672 	{ "PCIE_FID_VFID", 0x3c40, 0 },
5679 		{ "RVF", 0, 8 },
5680 	{ "PCIE_FID_VFID", 0x3c44, 0 },
5687 		{ "RVF", 0, 8 },
5688 	{ "PCIE_FID_VFID", 0x3c48, 0 },
5695 		{ "RVF", 0, 8 },
5696 	{ "PCIE_FID_VFID", 0x3c4c, 0 },
5703 		{ "RVF", 0, 8 },
5704 	{ "PCIE_FID_VFID", 0x3c50, 0 },
5711 		{ "RVF", 0, 8 },
5712 	{ "PCIE_FID_VFID", 0x3c54, 0 },
5719 		{ "RVF", 0, 8 },
5720 	{ "PCIE_FID_VFID", 0x3c58, 0 },
5727 		{ "RVF", 0, 8 },
5728 	{ "PCIE_FID_VFID", 0x3c5c, 0 },
5735 		{ "RVF", 0, 8 },
5736 	{ "PCIE_FID_VFID", 0x3c60, 0 },
5743 		{ "RVF", 0, 8 },
5744 	{ "PCIE_FID_VFID", 0x3c64, 0 },
5751 		{ "RVF", 0, 8 },
5752 	{ "PCIE_FID_VFID", 0x3c68, 0 },
5759 		{ "RVF", 0, 8 },
5760 	{ "PCIE_FID_VFID", 0x3c6c, 0 },
5767 		{ "RVF", 0, 8 },
5768 	{ "PCIE_FID_VFID", 0x3c70, 0 },
5775 		{ "RVF", 0, 8 },
5776 	{ "PCIE_FID_VFID", 0x3c74, 0 },
5783 		{ "RVF", 0, 8 },
5784 	{ "PCIE_FID_VFID", 0x3c78, 0 },
5791 		{ "RVF", 0, 8 },
5792 	{ "PCIE_FID_VFID", 0x3c7c, 0 },
5799 		{ "RVF", 0, 8 },
5800 	{ "PCIE_FID_VFID", 0x3c80, 0 },
5807 		{ "RVF", 0, 8 },
5808 	{ "PCIE_FID_VFID", 0x3c84, 0 },
5815 		{ "RVF", 0, 8 },
5816 	{ "PCIE_FID_VFID", 0x3c88, 0 },
5823 		{ "RVF", 0, 8 },
5824 	{ "PCIE_FID_VFID", 0x3c8c, 0 },
5831 		{ "RVF", 0, 8 },
5832 	{ "PCIE_FID_VFID", 0x3c90, 0 },
5839 		{ "RVF", 0, 8 },
5840 	{ "PCIE_FID_VFID", 0x3c94, 0 },
5847 		{ "RVF", 0, 8 },
5848 	{ "PCIE_FID_VFID", 0x3c98, 0 },
5855 		{ "RVF", 0, 8 },
5856 	{ "PCIE_FID_VFID", 0x3c9c, 0 },
5863 		{ "RVF", 0, 8 },
5864 	{ "PCIE_FID_VFID", 0x3ca0, 0 },
5871 		{ "RVF", 0, 8 },
5872 	{ "PCIE_FID_VFID", 0x3ca4, 0 },
5879 		{ "RVF", 0, 8 },
5880 	{ "PCIE_FID_VFID", 0x3ca8, 0 },
5887 		{ "RVF", 0, 8 },
5888 	{ "PCIE_FID_VFID", 0x3cac, 0 },
5895 		{ "RVF", 0, 8 },
5896 	{ "PCIE_FID_VFID", 0x3cb0, 0 },
5903 		{ "RVF", 0, 8 },
5904 	{ "PCIE_FID_VFID", 0x3cb4, 0 },
5911 		{ "RVF", 0, 8 },
5912 	{ "PCIE_FID_VFID", 0x3cb8, 0 },
5919 		{ "RVF", 0, 8 },
5920 	{ "PCIE_FID_VFID", 0x3cbc, 0 },
5927 		{ "RVF", 0, 8 },
5928 	{ "PCIE_FID_VFID", 0x3cc0, 0 },
5935 		{ "RVF", 0, 8 },
5936 	{ "PCIE_FID_VFID", 0x3cc4, 0 },
5943 		{ "RVF", 0, 8 },
5944 	{ "PCIE_FID_VFID", 0x3cc8, 0 },
5951 		{ "RVF", 0, 8 },
5952 	{ "PCIE_FID_VFID", 0x3ccc, 0 },
5959 		{ "RVF", 0, 8 },
5960 	{ "PCIE_FID_VFID", 0x3cd0, 0 },
5967 		{ "RVF", 0, 8 },
5968 	{ "PCIE_FID_VFID", 0x3cd4, 0 },
5975 		{ "RVF", 0, 8 },
5976 	{ "PCIE_FID_VFID", 0x3cd8, 0 },
5983 		{ "RVF", 0, 8 },
5984 	{ "PCIE_FID_VFID", 0x3cdc, 0 },
5991 		{ "RVF", 0, 8 },
5992 	{ "PCIE_FID_VFID", 0x3ce0, 0 },
5999 		{ "RVF", 0, 8 },
6000 	{ "PCIE_FID_VFID", 0x3ce4, 0 },
6007 		{ "RVF", 0, 8 },
6008 	{ "PCIE_FID_VFID", 0x3ce8, 0 },
6015 		{ "RVF", 0, 8 },
6016 	{ "PCIE_FID_VFID", 0x3cec, 0 },
6023 		{ "RVF", 0, 8 },
6024 	{ "PCIE_FID_VFID", 0x3cf0, 0 },
6031 		{ "RVF", 0, 8 },
6032 	{ "PCIE_FID_VFID", 0x3cf4, 0 },
6039 		{ "RVF", 0, 8 },
6040 	{ "PCIE_FID_VFID", 0x3cf8, 0 },
6047 		{ "RVF", 0, 8 },
6048 	{ "PCIE_FID_VFID", 0x3cfc, 0 },
6055 		{ "RVF", 0, 8 },
6056 	{ "PCIE_FID_VFID", 0x3d00, 0 },
6063 		{ "RVF", 0, 8 },
6064 	{ "PCIE_FID_VFID", 0x3d04, 0 },
6071 		{ "RVF", 0, 8 },
6072 	{ "PCIE_FID_VFID", 0x3d08, 0 },
6079 		{ "RVF", 0, 8 },
6080 	{ "PCIE_FID_VFID", 0x3d0c, 0 },
6087 		{ "RVF", 0, 8 },
6088 	{ "PCIE_FID_VFID", 0x3d10, 0 },
6095 		{ "RVF", 0, 8 },
6096 	{ "PCIE_FID_VFID", 0x3d14, 0 },
6103 		{ "RVF", 0, 8 },
6104 	{ "PCIE_FID_VFID", 0x3d18, 0 },
6111 		{ "RVF", 0, 8 },
6112 	{ "PCIE_FID_VFID", 0x3d1c, 0 },
6119 		{ "RVF", 0, 8 },
6120 	{ "PCIE_FID_VFID", 0x3d20, 0 },
6127 		{ "RVF", 0, 8 },
6128 	{ "PCIE_FID_VFID", 0x3d24, 0 },
6135 		{ "RVF", 0, 8 },
6136 	{ "PCIE_FID_VFID", 0x3d28, 0 },
6143 		{ "RVF", 0, 8 },
6144 	{ "PCIE_FID_VFID", 0x3d2c, 0 },
6151 		{ "RVF", 0, 8 },
6152 	{ "PCIE_FID_VFID", 0x3d30, 0 },
6159 		{ "RVF", 0, 8 },
6160 	{ "PCIE_FID_VFID", 0x3d34, 0 },
6167 		{ "RVF", 0, 8 },
6168 	{ "PCIE_FID_VFID", 0x3d38, 0 },
6175 		{ "RVF", 0, 8 },
6176 	{ "PCIE_FID_VFID", 0x3d3c, 0 },
6183 		{ "RVF", 0, 8 },
6184 	{ "PCIE_FID_VFID", 0x3d40, 0 },
6191 		{ "RVF", 0, 8 },
6192 	{ "PCIE_FID_VFID", 0x3d44, 0 },
6199 		{ "RVF", 0, 8 },
6200 	{ "PCIE_FID_VFID", 0x3d48, 0 },
6207 		{ "RVF", 0, 8 },
6208 	{ "PCIE_FID_VFID", 0x3d4c, 0 },
6215 		{ "RVF", 0, 8 },
6216 	{ "PCIE_FID_VFID", 0x3d50, 0 },
6223 		{ "RVF", 0, 8 },
6224 	{ "PCIE_FID_VFID", 0x3d54, 0 },
6231 		{ "RVF", 0, 8 },
6232 	{ "PCIE_FID_VFID", 0x3d58, 0 },
6239 		{ "RVF", 0, 8 },
6240 	{ "PCIE_FID_VFID", 0x3d5c, 0 },
6247 		{ "RVF", 0, 8 },
6248 	{ "PCIE_FID_VFID", 0x3d60, 0 },
6255 		{ "RVF", 0, 8 },
6256 	{ "PCIE_FID_VFID", 0x3d64, 0 },
6263 		{ "RVF", 0, 8 },
6264 	{ "PCIE_FID_VFID", 0x3d68, 0 },
6271 		{ "RVF", 0, 8 },
6272 	{ "PCIE_FID_VFID", 0x3d6c, 0 },
6279 		{ "RVF", 0, 8 },
6280 	{ "PCIE_FID_VFID", 0x3d70, 0 },
6287 		{ "RVF", 0, 8 },
6288 	{ "PCIE_FID_VFID", 0x3d74, 0 },
6295 		{ "RVF", 0, 8 },
6296 	{ "PCIE_FID_VFID", 0x3d78, 0 },
6303 		{ "RVF", 0, 8 },
6304 	{ "PCIE_FID_VFID", 0x3d7c, 0 },
6311 		{ "RVF", 0, 8 },
6312 	{ "PCIE_FID_VFID", 0x3d80, 0 },
6319 		{ "RVF", 0, 8 },
6320 	{ "PCIE_FID_VFID", 0x3d84, 0 },
6327 		{ "RVF", 0, 8 },
6328 	{ "PCIE_FID_VFID", 0x3d88, 0 },
6335 		{ "RVF", 0, 8 },
6336 	{ "PCIE_FID_VFID", 0x3d8c, 0 },
6343 		{ "RVF", 0, 8 },
6344 	{ "PCIE_FID_VFID", 0x3d90, 0 },
6351 		{ "RVF", 0, 8 },
6352 	{ "PCIE_FID_VFID", 0x3d94, 0 },
6359 		{ "RVF", 0, 8 },
6360 	{ "PCIE_FID_VFID", 0x3d98, 0 },
6367 		{ "RVF", 0, 8 },
6368 	{ "PCIE_FID_VFID", 0x3d9c, 0 },
6375 		{ "RVF", 0, 8 },
6376 	{ "PCIE_FID_VFID", 0x3da0, 0 },
6383 		{ "RVF", 0, 8 },
6384 	{ "PCIE_FID_VFID", 0x3da4, 0 },
6391 		{ "RVF", 0, 8 },
6392 	{ "PCIE_FID_VFID", 0x3da8, 0 },
6399 		{ "RVF", 0, 8 },
6400 	{ "PCIE_FID_VFID", 0x3dac, 0 },
6407 		{ "RVF", 0, 8 },
6408 	{ "PCIE_FID_VFID", 0x3db0, 0 },
6415 		{ "RVF", 0, 8 },
6416 	{ "PCIE_FID_VFID", 0x3db4, 0 },
6423 		{ "RVF", 0, 8 },
6424 	{ "PCIE_FID_VFID", 0x3db8, 0 },
6431 		{ "RVF", 0, 8 },
6432 	{ "PCIE_FID_VFID", 0x3dbc, 0 },
6439 		{ "RVF", 0, 8 },
6440 	{ "PCIE_FID_VFID", 0x3dc0, 0 },
6447 		{ "RVF", 0, 8 },
6448 	{ "PCIE_FID_VFID", 0x3dc4, 0 },
6455 		{ "RVF", 0, 8 },
6456 	{ "PCIE_FID_VFID", 0x3dc8, 0 },
6463 		{ "RVF", 0, 8 },
6464 	{ "PCIE_FID_VFID", 0x3dcc, 0 },
6471 		{ "RVF", 0, 8 },
6472 	{ "PCIE_FID_VFID", 0x3dd0, 0 },
6479 		{ "RVF", 0, 8 },
6480 	{ "PCIE_FID_VFID", 0x3dd4, 0 },
6487 		{ "RVF", 0, 8 },
6488 	{ "PCIE_FID_VFID", 0x3dd8, 0 },
6495 		{ "RVF", 0, 8 },
6496 	{ "PCIE_FID_VFID", 0x3ddc, 0 },
6503 		{ "RVF", 0, 8 },
6504 	{ "PCIE_FID_VFID", 0x3de0, 0 },
6511 		{ "RVF", 0, 8 },
6512 	{ "PCIE_FID_VFID", 0x3de4, 0 },
6519 		{ "RVF", 0, 8 },
6520 	{ "PCIE_FID_VFID", 0x3de8, 0 },
6527 		{ "RVF", 0, 8 },
6528 	{ "PCIE_FID_VFID", 0x3dec, 0 },
6535 		{ "RVF", 0, 8 },
6536 	{ "PCIE_FID_VFID", 0x3df0, 0 },
6543 		{ "RVF", 0, 8 },
6544 	{ "PCIE_FID_VFID", 0x3df4, 0 },
6551 		{ "RVF", 0, 8 },
6552 	{ "PCIE_FID_VFID", 0x3df8, 0 },
6559 		{ "RVF", 0, 8 },
6560 	{ "PCIE_FID_VFID", 0x3dfc, 0 },
6567 		{ "RVF", 0, 8 },
6568 	{ "PCIE_FID_VFID", 0x3e00, 0 },
6575 		{ "RVF", 0, 8 },
6576 	{ "PCIE_FID_VFID", 0x3e04, 0 },
6583 		{ "RVF", 0, 8 },
6584 	{ "PCIE_FID_VFID", 0x3e08, 0 },
6591 		{ "RVF", 0, 8 },
6592 	{ "PCIE_FID_VFID", 0x3e0c, 0 },
6599 		{ "RVF", 0, 8 },
6600 	{ "PCIE_FID_VFID", 0x3e10, 0 },
6607 		{ "RVF", 0, 8 },
6608 	{ "PCIE_FID_VFID", 0x3e14, 0 },
6615 		{ "RVF", 0, 8 },
6616 	{ "PCIE_FID_VFID", 0x3e18, 0 },
6623 		{ "RVF", 0, 8 },
6624 	{ "PCIE_FID_VFID", 0x3e1c, 0 },
6631 		{ "RVF", 0, 8 },
6632 	{ "PCIE_FID_VFID", 0x3e20, 0 },
6639 		{ "RVF", 0, 8 },
6640 	{ "PCIE_FID_VFID", 0x3e24, 0 },
6647 		{ "RVF", 0, 8 },
6648 	{ "PCIE_FID_VFID", 0x3e28, 0 },
6655 		{ "RVF", 0, 8 },
6656 	{ "PCIE_FID_VFID", 0x3e2c, 0 },
6663 		{ "RVF", 0, 8 },
6664 	{ "PCIE_FID_VFID", 0x3e30, 0 },
6671 		{ "RVF", 0, 8 },
6672 	{ "PCIE_FID_VFID", 0x3e34, 0 },
6679 		{ "RVF", 0, 8 },
6680 	{ "PCIE_FID_VFID", 0x3e38, 0 },
6687 		{ "RVF", 0, 8 },
6688 	{ "PCIE_FID_VFID", 0x3e3c, 0 },
6695 		{ "RVF", 0, 8 },
6696 	{ "PCIE_FID_VFID", 0x3e40, 0 },
6703 		{ "RVF", 0, 8 },
6704 	{ "PCIE_FID_VFID", 0x3e44, 0 },
6711 		{ "RVF", 0, 8 },
6712 	{ "PCIE_FID_VFID", 0x3e48, 0 },
6719 		{ "RVF", 0, 8 },
6720 	{ "PCIE_FID_VFID", 0x3e4c, 0 },
6727 		{ "RVF", 0, 8 },
6728 	{ "PCIE_FID_VFID", 0x3e50, 0 },
6735 		{ "RVF", 0, 8 },
6736 	{ "PCIE_FID_VFID", 0x3e54, 0 },
6743 		{ "RVF", 0, 8 },
6744 	{ "PCIE_FID_VFID", 0x3e58, 0 },
6751 		{ "RVF", 0, 8 },
6752 	{ "PCIE_FID_VFID", 0x3e5c, 0 },
6759 		{ "RVF", 0, 8 },
6760 	{ "PCIE_FID_VFID", 0x3e60, 0 },
6767 		{ "RVF", 0, 8 },
6768 	{ "PCIE_FID_VFID", 0x3e64, 0 },
6775 		{ "RVF", 0, 8 },
6776 	{ "PCIE_FID_VFID", 0x3e68, 0 },
6783 		{ "RVF", 0, 8 },
6784 	{ "PCIE_FID_VFID", 0x3e6c, 0 },
6791 		{ "RVF", 0, 8 },
6792 	{ "PCIE_FID_VFID", 0x3e70, 0 },
6799 		{ "RVF", 0, 8 },
6800 	{ "PCIE_FID_VFID", 0x3e74, 0 },
6807 		{ "RVF", 0, 8 },
6808 	{ "PCIE_FID_VFID", 0x3e78, 0 },
6815 		{ "RVF", 0, 8 },
6816 	{ "PCIE_FID_VFID", 0x3e7c, 0 },
6823 		{ "RVF", 0, 8 },
6824 	{ "PCIE_FID_VFID", 0x3e80, 0 },
6831 		{ "RVF", 0, 8 },
6832 	{ "PCIE_FID_VFID", 0x3e84, 0 },
6839 		{ "RVF", 0, 8 },
6840 	{ "PCIE_FID_VFID", 0x3e88, 0 },
6847 		{ "RVF", 0, 8 },
6848 	{ "PCIE_FID_VFID", 0x3e8c, 0 },
6855 		{ "RVF", 0, 8 },
6856 	{ "PCIE_FID_VFID", 0x3e90, 0 },
6863 		{ "RVF", 0, 8 },
6864 	{ "PCIE_FID_VFID", 0x3e94, 0 },
6871 		{ "RVF", 0, 8 },
6872 	{ "PCIE_FID_VFID", 0x3e98, 0 },
6879 		{ "RVF", 0, 8 },
6880 	{ "PCIE_FID_VFID", 0x3e9c, 0 },
6887 		{ "RVF", 0, 8 },
6888 	{ "PCIE_FID_VFID", 0x3ea0, 0 },
6895 		{ "RVF", 0, 8 },
6896 	{ "PCIE_FID_VFID", 0x3ea4, 0 },
6903 		{ "RVF", 0, 8 },
6904 	{ "PCIE_FID_VFID", 0x3ea8, 0 },
6911 		{ "RVF", 0, 8 },
6912 	{ "PCIE_FID_VFID", 0x3eac, 0 },
6919 		{ "RVF", 0, 8 },
6920 	{ "PCIE_FID_VFID", 0x3eb0, 0 },
6927 		{ "RVF", 0, 8 },
6928 	{ "PCIE_FID_VFID", 0x3eb4, 0 },
6935 		{ "RVF", 0, 8 },
6936 	{ "PCIE_FID_VFID", 0x3eb8, 0 },
6943 		{ "RVF", 0, 8 },
6944 	{ "PCIE_FID_VFID", 0x3ebc, 0 },
6951 		{ "RVF", 0, 8 },
6952 	{ "PCIE_FID_VFID", 0x3ec0, 0 },
6959 		{ "RVF", 0, 8 },
6960 	{ "PCIE_FID_VFID", 0x3ec4, 0 },
6967 		{ "RVF", 0, 8 },
6968 	{ "PCIE_FID_VFID", 0x3ec8, 0 },
6975 		{ "RVF", 0, 8 },
6976 	{ "PCIE_FID_VFID", 0x3ecc, 0 },
6983 		{ "RVF", 0, 8 },
6984 	{ "PCIE_FID_VFID", 0x3ed0, 0 },
6991 		{ "RVF", 0, 8 },
6992 	{ "PCIE_FID_VFID", 0x3ed4, 0 },
6999 		{ "RVF", 0, 8 },
7000 	{ "PCIE_FID_VFID", 0x3ed8, 0 },
7007 		{ "RVF", 0, 8 },
7008 	{ "PCIE_FID_VFID", 0x3edc, 0 },
7015 		{ "RVF", 0, 8 },
7016 	{ "PCIE_FID_VFID", 0x3ee0, 0 },
7023 		{ "RVF", 0, 8 },
7024 	{ "PCIE_FID_VFID", 0x3ee4, 0 },
7031 		{ "RVF", 0, 8 },
7032 	{ "PCIE_FID_VFID", 0x3ee8, 0 },
7039 		{ "RVF", 0, 8 },
7040 	{ "PCIE_FID_VFID", 0x3eec, 0 },
7047 		{ "RVF", 0, 8 },
7048 	{ "PCIE_FID_VFID", 0x3ef0, 0 },
7055 		{ "RVF", 0, 8 },
7056 	{ "PCIE_FID_VFID", 0x3ef4, 0 },
7063 		{ "RVF", 0, 8 },
7064 	{ "PCIE_FID_VFID", 0x3ef8, 0 },
7071 		{ "RVF", 0, 8 },
7072 	{ "PCIE_FID_VFID", 0x3efc, 0 },
7079 		{ "RVF", 0, 8 },
7080 	{ "PCIE_FID_VFID", 0x3f00, 0 },
7087 		{ "RVF", 0, 8 },
7088 	{ "PCIE_FID_VFID", 0x3f04, 0 },
7095 		{ "RVF", 0, 8 },
7096 	{ "PCIE_FID_VFID", 0x3f08, 0 },
7103 		{ "RVF", 0, 8 },
7104 	{ "PCIE_FID_VFID", 0x3f0c, 0 },
7111 		{ "RVF", 0, 8 },
7112 	{ "PCIE_FID_VFID", 0x3f10, 0 },
7119 		{ "RVF", 0, 8 },
7120 	{ "PCIE_FID_VFID", 0x3f14, 0 },
7127 		{ "RVF", 0, 8 },
7128 	{ "PCIE_FID_VFID", 0x3f18, 0 },
7135 		{ "RVF", 0, 8 },
7136 	{ "PCIE_FID_VFID", 0x3f1c, 0 },
7143 		{ "RVF", 0, 8 },
7144 	{ "PCIE_FID_VFID", 0x3f20, 0 },
7151 		{ "RVF", 0, 8 },
7152 	{ "PCIE_FID_VFID", 0x3f24, 0 },
7159 		{ "RVF", 0, 8 },
7160 	{ "PCIE_FID_VFID", 0x3f28, 0 },
7167 		{ "RVF", 0, 8 },
7168 	{ "PCIE_FID_VFID", 0x3f2c, 0 },
7175 		{ "RVF", 0, 8 },
7176 	{ "PCIE_FID_VFID", 0x3f30, 0 },
7183 		{ "RVF", 0, 8 },
7184 	{ "PCIE_FID_VFID", 0x3f34, 0 },
7191 		{ "RVF", 0, 8 },
7192 	{ "PCIE_FID_VFID", 0x3f38, 0 },
7199 		{ "RVF", 0, 8 },
7200 	{ "PCIE_FID_VFID", 0x3f3c, 0 },
7207 		{ "RVF", 0, 8 },
7208 	{ "PCIE_FID_VFID", 0x3f40, 0 },
7215 		{ "RVF", 0, 8 },
7216 	{ "PCIE_FID_VFID", 0x3f44, 0 },
7223 		{ "RVF", 0, 8 },
7224 	{ "PCIE_FID_VFID", 0x3f48, 0 },
7231 		{ "RVF", 0, 8 },
7232 	{ "PCIE_FID_VFID", 0x3f4c, 0 },
7239 		{ "RVF", 0, 8 },
7240 	{ "PCIE_FID_VFID", 0x3f50, 0 },
7247 		{ "RVF", 0, 8 },
7248 	{ "PCIE_FID_VFID", 0x3f54, 0 },
7255 		{ "RVF", 0, 8 },
7256 	{ "PCIE_FID_VFID", 0x3f58, 0 },
7263 		{ "RVF", 0, 8 },
7264 	{ "PCIE_FID_VFID", 0x3f5c, 0 },
7271 		{ "RVF", 0, 8 },
7272 	{ "PCIE_FID_VFID", 0x3f60, 0 },
7279 		{ "RVF", 0, 8 },
7280 	{ "PCIE_FID_VFID", 0x3f64, 0 },
7287 		{ "RVF", 0, 8 },
7288 	{ "PCIE_FID_VFID", 0x3f68, 0 },
7295 		{ "RVF", 0, 8 },
7296 	{ "PCIE_FID_VFID", 0x3f6c, 0 },
7303 		{ "RVF", 0, 8 },
7304 	{ "PCIE_FID_VFID", 0x3f70, 0 },
7311 		{ "RVF", 0, 8 },
7312 	{ "PCIE_FID_VFID", 0x3f74, 0 },
7319 		{ "RVF", 0, 8 },
7320 	{ "PCIE_FID_VFID", 0x3f78, 0 },
7327 		{ "RVF", 0, 8 },
7328 	{ "PCIE_FID_VFID", 0x3f7c, 0 },
7335 		{ "RVF", 0, 8 },
7336 	{ "PCIE_FID_VFID", 0x3f80, 0 },
7343 		{ "RVF", 0, 8 },
7344 	{ "PCIE_FID_VFID", 0x3f84, 0 },
7351 		{ "RVF", 0, 8 },
7352 	{ "PCIE_FID_VFID", 0x3f88, 0 },
7359 		{ "RVF", 0, 8 },
7360 	{ "PCIE_FID_VFID", 0x3f8c, 0 },
7367 		{ "RVF", 0, 8 },
7368 	{ "PCIE_FID_VFID", 0x3f90, 0 },
7375 		{ "RVF", 0, 8 },
7376 	{ "PCIE_FID_VFID", 0x3f94, 0 },
7383 		{ "RVF", 0, 8 },
7384 	{ "PCIE_FID_VFID", 0x3f98, 0 },
7391 		{ "RVF", 0, 8 },
7392 	{ "PCIE_FID_VFID", 0x3f9c, 0 },
7399 		{ "RVF", 0, 8 },
7400 	{ "PCIE_FID_VFID", 0x3fa0, 0 },
7407 		{ "RVF", 0, 8 },
7408 	{ "PCIE_FID_VFID", 0x3fa4, 0 },
7415 		{ "RVF", 0, 8 },
7416 	{ "PCIE_FID_VFID", 0x3fa8, 0 },
7423 		{ "RVF", 0, 8 },
7424 	{ "PCIE_FID_VFID", 0x3fac, 0 },
7431 		{ "RVF", 0, 8 },
7432 	{ "PCIE_FID_VFID", 0x3fb0, 0 },
7439 		{ "RVF", 0, 8 },
7440 	{ "PCIE_FID_VFID", 0x3fb4, 0 },
7447 		{ "RVF", 0, 8 },
7448 	{ "PCIE_FID_VFID", 0x3fb8, 0 },
7455 		{ "RVF", 0, 8 },
7456 	{ "PCIE_FID_VFID", 0x3fbc, 0 },
7463 		{ "RVF", 0, 8 },
7464 	{ "PCIE_FID_VFID", 0x3fc0, 0 },
7471 		{ "RVF", 0, 8 },
7472 	{ "PCIE_FID_VFID", 0x3fc4, 0 },
7479 		{ "RVF", 0, 8 },
7480 	{ "PCIE_FID_VFID", 0x3fc8, 0 },
7487 		{ "RVF", 0, 8 },
7488 	{ "PCIE_FID_VFID", 0x3fcc, 0 },
7495 		{ "RVF", 0, 8 },
7496 	{ "PCIE_FID_VFID", 0x3fd0, 0 },
7503 		{ "RVF", 0, 8 },
7504 	{ "PCIE_FID_VFID", 0x3fd4, 0 },
7511 		{ "RVF", 0, 8 },
7512 	{ "PCIE_FID_VFID", 0x3fd8, 0 },
7519 		{ "RVF", 0, 8 },
7520 	{ "PCIE_FID_VFID", 0x3fdc, 0 },
7527 		{ "RVF", 0, 8 },
7528 	{ "PCIE_FID_VFID", 0x3fe0, 0 },
7535 		{ "RVF", 0, 8 },
7536 	{ "PCIE_FID_VFID", 0x3fe4, 0 },
7543 		{ "RVF", 0, 8 },
7544 	{ "PCIE_FID_VFID", 0x3fe8, 0 },
7551 		{ "RVF", 0, 8 },
7552 	{ "PCIE_FID_VFID", 0x3fec, 0 },
7559 		{ "RVF", 0, 8 },
7560 	{ "PCIE_FID_VFID", 0x3ff0, 0 },
7567 		{ "RVF", 0, 8 },
7568 	{ "PCIE_FID_VFID", 0x3ff4, 0 },
7575 		{ "RVF", 0, 8 },
7576 	{ "PCIE_FID_VFID", 0x3ff8, 0 },
7583 		{ "RVF", 0, 8 },
7584 	{ "PCIE_FID_VFID", 0x3ffc, 0 },
7591 		{ "RVF", 0, 8 },
7592 	{ "PCIE_FID_VFID", 0x4000, 0 },
7599 		{ "RVF", 0, 8 },
7600 	{ "PCIE_FID_VFID", 0x4004, 0 },
7607 		{ "RVF", 0, 8 },
7608 	{ "PCIE_FID_VFID", 0x4008, 0 },
7615 		{ "RVF", 0, 8 },
7616 	{ "PCIE_FID_VFID", 0x400c, 0 },
7623 		{ "RVF", 0, 8 },
7624 	{ "PCIE_FID_VFID", 0x4010, 0 },
7631 		{ "RVF", 0, 8 },
7632 	{ "PCIE_FID_VFID", 0x4014, 0 },
7639 		{ "RVF", 0, 8 },
7640 	{ "PCIE_FID_VFID", 0x4018, 0 },
7647 		{ "RVF", 0, 8 },
7648 	{ "PCIE_FID_VFID", 0x401c, 0 },
7655 		{ "RVF", 0, 8 },
7656 	{ "PCIE_FID_VFID", 0x4020, 0 },
7663 		{ "RVF", 0, 8 },
7664 	{ "PCIE_FID_VFID", 0x4024, 0 },
7671 		{ "RVF", 0, 8 },
7672 	{ "PCIE_FID_VFID", 0x4028, 0 },
7679 		{ "RVF", 0, 8 },
7680 	{ "PCIE_FID_VFID", 0x402c, 0 },
7687 		{ "RVF", 0, 8 },
7688 	{ "PCIE_FID_VFID", 0x4030, 0 },
7695 		{ "RVF", 0, 8 },
7696 	{ "PCIE_FID_VFID", 0x4034, 0 },
7703 		{ "RVF", 0, 8 },
7704 	{ "PCIE_FID_VFID", 0x4038, 0 },
7711 		{ "RVF", 0, 8 },
7712 	{ "PCIE_FID_VFID", 0x403c, 0 },
7719 		{ "RVF", 0, 8 },
7720 	{ "PCIE_FID_VFID", 0x4040, 0 },
7727 		{ "RVF", 0, 8 },
7728 	{ "PCIE_FID_VFID", 0x4044, 0 },
7735 		{ "RVF", 0, 8 },
7736 	{ "PCIE_FID_VFID", 0x4048, 0 },
7743 		{ "RVF", 0, 8 },
7744 	{ "PCIE_FID_VFID", 0x404c, 0 },
7751 		{ "RVF", 0, 8 },
7752 	{ "PCIE_FID_VFID", 0x4050, 0 },
7759 		{ "RVF", 0, 8 },
7760 	{ "PCIE_FID_VFID", 0x4054, 0 },
7767 		{ "RVF", 0, 8 },
7768 	{ "PCIE_FID_VFID", 0x4058, 0 },
7775 		{ "RVF", 0, 8 },
7776 	{ "PCIE_FID_VFID", 0x405c, 0 },
7783 		{ "RVF", 0, 8 },
7784 	{ "PCIE_FID_VFID", 0x4060, 0 },
7791 		{ "RVF", 0, 8 },
7792 	{ "PCIE_FID_VFID", 0x4064, 0 },
7799 		{ "RVF", 0, 8 },
7800 	{ "PCIE_FID_VFID", 0x4068, 0 },
7807 		{ "RVF", 0, 8 },
7808 	{ "PCIE_FID_VFID", 0x406c, 0 },
7815 		{ "RVF", 0, 8 },
7816 	{ "PCIE_FID_VFID", 0x4070, 0 },
7823 		{ "RVF", 0, 8 },
7824 	{ "PCIE_FID_VFID", 0x4074, 0 },
7831 		{ "RVF", 0, 8 },
7832 	{ "PCIE_FID_VFID", 0x4078, 0 },
7839 		{ "RVF", 0, 8 },
7840 	{ "PCIE_FID_VFID", 0x407c, 0 },
7847 		{ "RVF", 0, 8 },
7848 	{ "PCIE_FID_VFID", 0x4080, 0 },
7855 		{ "RVF", 0, 8 },
7856 	{ "PCIE_FID_VFID", 0x4084, 0 },
7863 		{ "RVF", 0, 8 },
7864 	{ "PCIE_FID_VFID", 0x4088, 0 },
7871 		{ "RVF", 0, 8 },
7872 	{ "PCIE_FID_VFID", 0x408c, 0 },
7879 		{ "RVF", 0, 8 },
7880 	{ "PCIE_FID_VFID", 0x4090, 0 },
7887 		{ "RVF", 0, 8 },
7888 	{ "PCIE_FID_VFID", 0x4094, 0 },
7895 		{ "RVF", 0, 8 },
7896 	{ "PCIE_FID_VFID", 0x4098, 0 },
7903 		{ "RVF", 0, 8 },
7904 	{ "PCIE_FID_VFID", 0x409c, 0 },
7911 		{ "RVF", 0, 8 },
7912 	{ "PCIE_FID_VFID", 0x40a0, 0 },
7919 		{ "RVF", 0, 8 },
7920 	{ "PCIE_FID_VFID", 0x40a4, 0 },
7927 		{ "RVF", 0, 8 },
7928 	{ "PCIE_FID_VFID", 0x40a8, 0 },
7935 		{ "RVF", 0, 8 },
7936 	{ "PCIE_FID_VFID", 0x40ac, 0 },
7943 		{ "RVF", 0, 8 },
7944 	{ "PCIE_FID_VFID", 0x40b0, 0 },
7951 		{ "RVF", 0, 8 },
7952 	{ "PCIE_FID_VFID", 0x40b4, 0 },
7959 		{ "RVF", 0, 8 },
7960 	{ "PCIE_FID_VFID", 0x40b8, 0 },
7967 		{ "RVF", 0, 8 },
7968 	{ "PCIE_FID_VFID", 0x40bc, 0 },
7975 		{ "RVF", 0, 8 },
7976 	{ "PCIE_FID_VFID", 0x40c0, 0 },
7983 		{ "RVF", 0, 8 },
7984 	{ "PCIE_FID_VFID", 0x40c4, 0 },
7991 		{ "RVF", 0, 8 },
7992 	{ "PCIE_FID_VFID", 0x40c8, 0 },
7999 		{ "RVF", 0, 8 },
8000 	{ "PCIE_FID_VFID", 0x40cc, 0 },
8007 		{ "RVF", 0, 8 },
8008 	{ "PCIE_FID_VFID", 0x40d0, 0 },
8015 		{ "RVF", 0, 8 },
8016 	{ "PCIE_FID_VFID", 0x40d4, 0 },
8023 		{ "RVF", 0, 8 },
8024 	{ "PCIE_FID_VFID", 0x40d8, 0 },
8031 		{ "RVF", 0, 8 },
8032 	{ "PCIE_FID_VFID", 0x40dc, 0 },
8039 		{ "RVF", 0, 8 },
8040 	{ "PCIE_FID_VFID", 0x40e0, 0 },
8047 		{ "RVF", 0, 8 },
8048 	{ "PCIE_FID_VFID", 0x40e4, 0 },
8055 		{ "RVF", 0, 8 },
8056 	{ "PCIE_FID_VFID", 0x40e8, 0 },
8063 		{ "RVF", 0, 8 },
8064 	{ "PCIE_FID_VFID", 0x40ec, 0 },
8071 		{ "RVF", 0, 8 },
8072 	{ "PCIE_FID_VFID", 0x40f0, 0 },
8079 		{ "RVF", 0, 8 },
8080 	{ "PCIE_FID_VFID", 0x40f4, 0 },
8087 		{ "RVF", 0, 8 },
8088 	{ "PCIE_FID_VFID", 0x40f8, 0 },
8095 		{ "RVF", 0, 8 },
8096 	{ "PCIE_FID_VFID", 0x40fc, 0 },
8103 		{ "RVF", 0, 8 },
8104 	{ "PCIE_FID_VFID", 0x4100, 0 },
8111 		{ "RVF", 0, 8 },
8112 	{ "PCIE_FID_VFID", 0x4104, 0 },
8119 		{ "RVF", 0, 8 },
8120 	{ "PCIE_FID_VFID", 0x4108, 0 },
8127 		{ "RVF", 0, 8 },
8128 	{ "PCIE_FID_VFID", 0x410c, 0 },
8135 		{ "RVF", 0, 8 },
8136 	{ "PCIE_FID_VFID", 0x4110, 0 },
8143 		{ "RVF", 0, 8 },
8144 	{ "PCIE_FID_VFID", 0x4114, 0 },
8151 		{ "RVF", 0, 8 },
8152 	{ "PCIE_FID_VFID", 0x4118, 0 },
8159 		{ "RVF", 0, 8 },
8160 	{ "PCIE_FID_VFID", 0x411c, 0 },
8167 		{ "RVF", 0, 8 },
8168 	{ "PCIE_FID_VFID", 0x4120, 0 },
8175 		{ "RVF", 0, 8 },
8176 	{ "PCIE_FID_VFID", 0x4124, 0 },
8183 		{ "RVF", 0, 8 },
8184 	{ "PCIE_FID_VFID", 0x4128, 0 },
8191 		{ "RVF", 0, 8 },
8192 	{ "PCIE_FID_VFID", 0x412c, 0 },
8199 		{ "RVF", 0, 8 },
8200 	{ "PCIE_FID_VFID", 0x4130, 0 },
8207 		{ "RVF", 0, 8 },
8208 	{ "PCIE_FID_VFID", 0x4134, 0 },
8215 		{ "RVF", 0, 8 },
8216 	{ "PCIE_FID_VFID", 0x4138, 0 },
8223 		{ "RVF", 0, 8 },
8224 	{ "PCIE_FID_VFID", 0x413c, 0 },
8231 		{ "RVF", 0, 8 },
8232 	{ "PCIE_FID_VFID", 0x4140, 0 },
8239 		{ "RVF", 0, 8 },
8240 	{ "PCIE_FID_VFID", 0x4144, 0 },
8247 		{ "RVF", 0, 8 },
8248 	{ "PCIE_FID_VFID", 0x4148, 0 },
8255 		{ "RVF", 0, 8 },
8256 	{ "PCIE_FID_VFID", 0x414c, 0 },
8263 		{ "RVF", 0, 8 },
8264 	{ "PCIE_FID_VFID", 0x4150, 0 },
8271 		{ "RVF", 0, 8 },
8272 	{ "PCIE_FID_VFID", 0x4154, 0 },
8279 		{ "RVF", 0, 8 },
8280 	{ "PCIE_FID_VFID", 0x4158, 0 },
8287 		{ "RVF", 0, 8 },
8288 	{ "PCIE_FID_VFID", 0x415c, 0 },
8295 		{ "RVF", 0, 8 },
8296 	{ "PCIE_FID_VFID", 0x4160, 0 },
8303 		{ "RVF", 0, 8 },
8304 	{ "PCIE_FID_VFID", 0x4164, 0 },
8311 		{ "RVF", 0, 8 },
8312 	{ "PCIE_FID_VFID", 0x4168, 0 },
8319 		{ "RVF", 0, 8 },
8320 	{ "PCIE_FID_VFID", 0x416c, 0 },
8327 		{ "RVF", 0, 8 },
8328 	{ "PCIE_FID_VFID", 0x4170, 0 },
8335 		{ "RVF", 0, 8 },
8336 	{ "PCIE_FID_VFID", 0x4174, 0 },
8343 		{ "RVF", 0, 8 },
8344 	{ "PCIE_FID_VFID", 0x4178, 0 },
8351 		{ "RVF", 0, 8 },
8352 	{ "PCIE_FID_VFID", 0x417c, 0 },
8359 		{ "RVF", 0, 8 },
8360 	{ "PCIE_FID_VFID", 0x4180, 0 },
8367 		{ "RVF", 0, 8 },
8368 	{ "PCIE_FID_VFID", 0x4184, 0 },
8375 		{ "RVF", 0, 8 },
8376 	{ "PCIE_FID_VFID", 0x4188, 0 },
8383 		{ "RVF", 0, 8 },
8384 	{ "PCIE_FID_VFID", 0x418c, 0 },
8391 		{ "RVF", 0, 8 },
8392 	{ "PCIE_FID_VFID", 0x4190, 0 },
8399 		{ "RVF", 0, 8 },
8400 	{ "PCIE_FID_VFID", 0x4194, 0 },
8407 		{ "RVF", 0, 8 },
8408 	{ "PCIE_FID_VFID", 0x4198, 0 },
8415 		{ "RVF", 0, 8 },
8416 	{ "PCIE_FID_VFID", 0x419c, 0 },
8423 		{ "RVF", 0, 8 },
8424 	{ "PCIE_FID_VFID", 0x41a0, 0 },
8431 		{ "RVF", 0, 8 },
8432 	{ "PCIE_FID_VFID", 0x41a4, 0 },
8439 		{ "RVF", 0, 8 },
8440 	{ "PCIE_FID_VFID", 0x41a8, 0 },
8447 		{ "RVF", 0, 8 },
8448 	{ "PCIE_FID_VFID", 0x41ac, 0 },
8455 		{ "RVF", 0, 8 },
8456 	{ "PCIE_FID_VFID", 0x41b0, 0 },
8463 		{ "RVF", 0, 8 },
8464 	{ "PCIE_FID_VFID", 0x41b4, 0 },
8471 		{ "RVF", 0, 8 },
8472 	{ "PCIE_FID_VFID", 0x41b8, 0 },
8479 		{ "RVF", 0, 8 },
8480 	{ "PCIE_FID_VFID", 0x41bc, 0 },
8487 		{ "RVF", 0, 8 },
8488 	{ "PCIE_FID_VFID", 0x41c0, 0 },
8495 		{ "RVF", 0, 8 },
8496 	{ "PCIE_FID_VFID", 0x41c4, 0 },
8503 		{ "RVF", 0, 8 },
8504 	{ "PCIE_FID_VFID", 0x41c8, 0 },
8511 		{ "RVF", 0, 8 },
8512 	{ "PCIE_FID_VFID", 0x41cc, 0 },
8519 		{ "RVF", 0, 8 },
8520 	{ "PCIE_FID_VFID", 0x41d0, 0 },
8527 		{ "RVF", 0, 8 },
8528 	{ "PCIE_FID_VFID", 0x41d4, 0 },
8535 		{ "RVF", 0, 8 },
8536 	{ "PCIE_FID_VFID", 0x41d8, 0 },
8543 		{ "RVF", 0, 8 },
8544 	{ "PCIE_FID_VFID", 0x41dc, 0 },
8551 		{ "RVF", 0, 8 },
8552 	{ "PCIE_FID_VFID", 0x41e0, 0 },
8559 		{ "RVF", 0, 8 },
8560 	{ "PCIE_FID_VFID", 0x41e4, 0 },
8567 		{ "RVF", 0, 8 },
8568 	{ "PCIE_FID_VFID", 0x41e8, 0 },
8575 		{ "RVF", 0, 8 },
8576 	{ "PCIE_FID_VFID", 0x41ec, 0 },
8583 		{ "RVF", 0, 8 },
8584 	{ "PCIE_FID_VFID", 0x41f0, 0 },
8591 		{ "RVF", 0, 8 },
8592 	{ "PCIE_FID_VFID", 0x41f4, 0 },
8599 		{ "RVF", 0, 8 },
8600 	{ "PCIE_FID_VFID", 0x41f8, 0 },
8607 		{ "RVF", 0, 8 },
8608 	{ "PCIE_FID_VFID", 0x41fc, 0 },
8615 		{ "RVF", 0, 8 },
8616 	{ "PCIE_FID_VFID", 0x4200, 0 },
8623 		{ "RVF", 0, 8 },
8624 	{ "PCIE_FID_VFID", 0x4204, 0 },
8631 		{ "RVF", 0, 8 },
8632 	{ "PCIE_FID_VFID", 0x4208, 0 },
8639 		{ "RVF", 0, 8 },
8640 	{ "PCIE_FID_VFID", 0x420c, 0 },
8647 		{ "RVF", 0, 8 },
8648 	{ "PCIE_FID_VFID", 0x4210, 0 },
8655 		{ "RVF", 0, 8 },
8656 	{ "PCIE_FID_VFID", 0x4214, 0 },
8663 		{ "RVF", 0, 8 },
8664 	{ "PCIE_FID_VFID", 0x4218, 0 },
8671 		{ "RVF", 0, 8 },
8672 	{ "PCIE_FID_VFID", 0x421c, 0 },
8679 		{ "RVF", 0, 8 },
8680 	{ "PCIE_FID_VFID", 0x4220, 0 },
8687 		{ "RVF", 0, 8 },
8688 	{ "PCIE_FID_VFID", 0x4224, 0 },
8695 		{ "RVF", 0, 8 },
8696 	{ "PCIE_FID_VFID", 0x4228, 0 },
8703 		{ "RVF", 0, 8 },
8704 	{ "PCIE_FID_VFID", 0x422c, 0 },
8711 		{ "RVF", 0, 8 },
8712 	{ "PCIE_FID_VFID", 0x4230, 0 },
8719 		{ "RVF", 0, 8 },
8720 	{ "PCIE_FID_VFID", 0x4234, 0 },
8727 		{ "RVF", 0, 8 },
8728 	{ "PCIE_FID_VFID", 0x4238, 0 },
8735 		{ "RVF", 0, 8 },
8736 	{ "PCIE_FID_VFID", 0x423c, 0 },
8743 		{ "RVF", 0, 8 },
8744 	{ "PCIE_FID_VFID", 0x4240, 0 },
8751 		{ "RVF", 0, 8 },
8752 	{ "PCIE_FID_VFID", 0x4244, 0 },
8759 		{ "RVF", 0, 8 },
8760 	{ "PCIE_FID_VFID", 0x4248, 0 },
8767 		{ "RVF", 0, 8 },
8768 	{ "PCIE_FID_VFID", 0x424c, 0 },
8775 		{ "RVF", 0, 8 },
8776 	{ "PCIE_FID_VFID", 0x4250, 0 },
8783 		{ "RVF", 0, 8 },
8784 	{ "PCIE_FID_VFID", 0x4254, 0 },
8791 		{ "RVF", 0, 8 },
8792 	{ "PCIE_FID_VFID", 0x4258, 0 },
8799 		{ "RVF", 0, 8 },
8800 	{ "PCIE_FID_VFID", 0x425c, 0 },
8807 		{ "RVF", 0, 8 },
8808 	{ "PCIE_FID_VFID", 0x4260, 0 },
8815 		{ "RVF", 0, 8 },
8816 	{ "PCIE_FID_VFID", 0x4264, 0 },
8823 		{ "RVF", 0, 8 },
8824 	{ "PCIE_FID_VFID", 0x4268, 0 },
8831 		{ "RVF", 0, 8 },
8832 	{ "PCIE_FID_VFID", 0x426c, 0 },
8839 		{ "RVF", 0, 8 },
8840 	{ "PCIE_FID_VFID", 0x4270, 0 },
8847 		{ "RVF", 0, 8 },
8848 	{ "PCIE_FID_VFID", 0x4274, 0 },
8855 		{ "RVF", 0, 8 },
8856 	{ "PCIE_FID_VFID", 0x4278, 0 },
8863 		{ "RVF", 0, 8 },
8864 	{ "PCIE_FID_VFID", 0x427c, 0 },
8871 		{ "RVF", 0, 8 },
8872 	{ "PCIE_FID_VFID", 0x4280, 0 },
8879 		{ "RVF", 0, 8 },
8880 	{ "PCIE_FID_VFID", 0x4284, 0 },
8887 		{ "RVF", 0, 8 },
8888 	{ "PCIE_FID_VFID", 0x4288, 0 },
8895 		{ "RVF", 0, 8 },
8896 	{ "PCIE_FID_VFID", 0x428c, 0 },
8903 		{ "RVF", 0, 8 },
8904 	{ "PCIE_FID_VFID", 0x4290, 0 },
8911 		{ "RVF", 0, 8 },
8912 	{ "PCIE_FID_VFID", 0x4294, 0 },
8919 		{ "RVF", 0, 8 },
8920 	{ "PCIE_FID_VFID", 0x4298, 0 },
8927 		{ "RVF", 0, 8 },
8928 	{ "PCIE_FID_VFID", 0x429c, 0 },
8935 		{ "RVF", 0, 8 },
8936 	{ "PCIE_FID_VFID", 0x42a0, 0 },
8943 		{ "RVF", 0, 8 },
8944 	{ "PCIE_FID_VFID", 0x42a4, 0 },
8951 		{ "RVF", 0, 8 },
8952 	{ "PCIE_FID_VFID", 0x42a8, 0 },
8959 		{ "RVF", 0, 8 },
8960 	{ "PCIE_FID_VFID", 0x42ac, 0 },
8967 		{ "RVF", 0, 8 },
8968 	{ "PCIE_FID_VFID", 0x42b0, 0 },
8975 		{ "RVF", 0, 8 },
8976 	{ "PCIE_FID_VFID", 0x42b4, 0 },
8983 		{ "RVF", 0, 8 },
8984 	{ "PCIE_FID_VFID", 0x42b8, 0 },
8991 		{ "RVF", 0, 8 },
8992 	{ "PCIE_FID_VFID", 0x42bc, 0 },
8999 		{ "RVF", 0, 8 },
9000 	{ "PCIE_FID_VFID", 0x42c0, 0 },
9007 		{ "RVF", 0, 8 },
9008 	{ "PCIE_FID_VFID", 0x42c4, 0 },
9015 		{ "RVF", 0, 8 },
9016 	{ "PCIE_FID_VFID", 0x42c8, 0 },
9023 		{ "RVF", 0, 8 },
9024 	{ "PCIE_FID_VFID", 0x42cc, 0 },
9031 		{ "RVF", 0, 8 },
9032 	{ "PCIE_FID_VFID", 0x42d0, 0 },
9039 		{ "RVF", 0, 8 },
9040 	{ "PCIE_FID_VFID", 0x42d4, 0 },
9047 		{ "RVF", 0, 8 },
9048 	{ "PCIE_FID_VFID", 0x42d8, 0 },
9055 		{ "RVF", 0, 8 },
9056 	{ "PCIE_FID_VFID", 0x42dc, 0 },
9063 		{ "RVF", 0, 8 },
9064 	{ "PCIE_FID_VFID", 0x42e0, 0 },
9071 		{ "RVF", 0, 8 },
9072 	{ "PCIE_FID_VFID", 0x42e4, 0 },
9079 		{ "RVF", 0, 8 },
9080 	{ "PCIE_FID_VFID", 0x42e8, 0 },
9087 		{ "RVF", 0, 8 },
9088 	{ "PCIE_FID_VFID", 0x42ec, 0 },
9095 		{ "RVF", 0, 8 },
9096 	{ "PCIE_FID_VFID", 0x42f0, 0 },
9103 		{ "RVF", 0, 8 },
9104 	{ "PCIE_FID_VFID", 0x42f4, 0 },
9111 		{ "RVF", 0, 8 },
9112 	{ "PCIE_FID_VFID", 0x42f8, 0 },
9119 		{ "RVF", 0, 8 },
9120 	{ "PCIE_FID_VFID", 0x42fc, 0 },
9127 		{ "RVF", 0, 8 },
9128 	{ "PCIE_FID_VFID", 0x4300, 0 },
9135 		{ "RVF", 0, 8 },
9136 	{ "PCIE_FID_VFID", 0x4304, 0 },
9143 		{ "RVF", 0, 8 },
9144 	{ "PCIE_FID_VFID", 0x4308, 0 },
9151 		{ "RVF", 0, 8 },
9152 	{ "PCIE_FID_VFID", 0x430c, 0 },
9159 		{ "RVF", 0, 8 },
9160 	{ "PCIE_FID_VFID", 0x4310, 0 },
9167 		{ "RVF", 0, 8 },
9168 	{ "PCIE_FID_VFID", 0x4314, 0 },
9175 		{ "RVF", 0, 8 },
9176 	{ "PCIE_FID_VFID", 0x4318, 0 },
9183 		{ "RVF", 0, 8 },
9184 	{ "PCIE_FID_VFID", 0x431c, 0 },
9191 		{ "RVF", 0, 8 },
9192 	{ "PCIE_FID_VFID", 0x4320, 0 },
9199 		{ "RVF", 0, 8 },
9200 	{ "PCIE_FID_VFID", 0x4324, 0 },
9207 		{ "RVF", 0, 8 },
9208 	{ "PCIE_FID_VFID", 0x4328, 0 },
9215 		{ "RVF", 0, 8 },
9216 	{ "PCIE_FID_VFID", 0x432c, 0 },
9223 		{ "RVF", 0, 8 },
9224 	{ "PCIE_FID_VFID", 0x4330, 0 },
9231 		{ "RVF", 0, 8 },
9232 	{ "PCIE_FID_VFID", 0x4334, 0 },
9239 		{ "RVF", 0, 8 },
9240 	{ "PCIE_FID_VFID", 0x4338, 0 },
9247 		{ "RVF", 0, 8 },
9248 	{ "PCIE_FID_VFID", 0x433c, 0 },
9255 		{ "RVF", 0, 8 },
9256 	{ "PCIE_FID_VFID", 0x4340, 0 },
9263 		{ "RVF", 0, 8 },
9264 	{ "PCIE_FID_VFID", 0x4344, 0 },
9271 		{ "RVF", 0, 8 },
9272 	{ "PCIE_FID_VFID", 0x4348, 0 },
9279 		{ "RVF", 0, 8 },
9280 	{ "PCIE_FID_VFID", 0x434c, 0 },
9287 		{ "RVF", 0, 8 },
9288 	{ "PCIE_FID_VFID", 0x4350, 0 },
9295 		{ "RVF", 0, 8 },
9296 	{ "PCIE_FID_VFID", 0x4354, 0 },
9303 		{ "RVF", 0, 8 },
9304 	{ "PCIE_FID_VFID", 0x4358, 0 },
9311 		{ "RVF", 0, 8 },
9312 	{ "PCIE_FID_VFID", 0x435c, 0 },
9319 		{ "RVF", 0, 8 },
9320 	{ "PCIE_FID_VFID", 0x4360, 0 },
9327 		{ "RVF", 0, 8 },
9328 	{ "PCIE_FID_VFID", 0x4364, 0 },
9335 		{ "RVF", 0, 8 },
9336 	{ "PCIE_FID_VFID", 0x4368, 0 },
9343 		{ "RVF", 0, 8 },
9344 	{ "PCIE_FID_VFID", 0x436c, 0 },
9351 		{ "RVF", 0, 8 },
9352 	{ "PCIE_FID_VFID", 0x4370, 0 },
9359 		{ "RVF", 0, 8 },
9360 	{ "PCIE_FID_VFID", 0x4374, 0 },
9367 		{ "RVF", 0, 8 },
9368 	{ "PCIE_FID_VFID", 0x4378, 0 },
9375 		{ "RVF", 0, 8 },
9376 	{ "PCIE_FID_VFID", 0x437c, 0 },
9383 		{ "RVF", 0, 8 },
9384 	{ "PCIE_FID_VFID", 0x4380, 0 },
9391 		{ "RVF", 0, 8 },
9392 	{ "PCIE_FID_VFID", 0x4384, 0 },
9399 		{ "RVF", 0, 8 },
9400 	{ "PCIE_FID_VFID", 0x4388, 0 },
9407 		{ "RVF", 0, 8 },
9408 	{ "PCIE_FID_VFID", 0x438c, 0 },
9415 		{ "RVF", 0, 8 },
9416 	{ "PCIE_FID_VFID", 0x4390, 0 },
9423 		{ "RVF", 0, 8 },
9424 	{ "PCIE_FID_VFID", 0x4394, 0 },
9431 		{ "RVF", 0, 8 },
9432 	{ "PCIE_FID_VFID", 0x4398, 0 },
9439 		{ "RVF", 0, 8 },
9440 	{ "PCIE_FID_VFID", 0x439c, 0 },
9447 		{ "RVF", 0, 8 },
9448 	{ "PCIE_FID_VFID", 0x43a0, 0 },
9455 		{ "RVF", 0, 8 },
9456 	{ "PCIE_FID_VFID", 0x43a4, 0 },
9463 		{ "RVF", 0, 8 },
9464 	{ "PCIE_FID_VFID", 0x43a8, 0 },
9471 		{ "RVF", 0, 8 },
9472 	{ "PCIE_FID_VFID", 0x43ac, 0 },
9479 		{ "RVF", 0, 8 },
9480 	{ "PCIE_FID_VFID", 0x43b0, 0 },
9487 		{ "RVF", 0, 8 },
9488 	{ "PCIE_FID_VFID", 0x43b4, 0 },
9495 		{ "RVF", 0, 8 },
9496 	{ "PCIE_FID_VFID", 0x43b8, 0 },
9503 		{ "RVF", 0, 8 },
9504 	{ "PCIE_FID_VFID", 0x43bc, 0 },
9511 		{ "RVF", 0, 8 },
9512 	{ "PCIE_FID_VFID", 0x43c0, 0 },
9519 		{ "RVF", 0, 8 },
9520 	{ "PCIE_FID_VFID", 0x43c4, 0 },
9527 		{ "RVF", 0, 8 },
9528 	{ "PCIE_FID_VFID", 0x43c8, 0 },
9535 		{ "RVF", 0, 8 },
9536 	{ "PCIE_FID_VFID", 0x43cc, 0 },
9543 		{ "RVF", 0, 8 },
9544 	{ "PCIE_FID_VFID", 0x43d0, 0 },
9551 		{ "RVF", 0, 8 },
9552 	{ "PCIE_FID_VFID", 0x43d4, 0 },
9559 		{ "RVF", 0, 8 },
9560 	{ "PCIE_FID_VFID", 0x43d8, 0 },
9567 		{ "RVF", 0, 8 },
9568 	{ "PCIE_FID_VFID", 0x43dc, 0 },
9575 		{ "RVF", 0, 8 },
9576 	{ "PCIE_FID_VFID", 0x43e0, 0 },
9583 		{ "RVF", 0, 8 },
9584 	{ "PCIE_FID_VFID", 0x43e4, 0 },
9591 		{ "RVF", 0, 8 },
9592 	{ "PCIE_FID_VFID", 0x43e8, 0 },
9599 		{ "RVF", 0, 8 },
9600 	{ "PCIE_FID_VFID", 0x43ec, 0 },
9607 		{ "RVF", 0, 8 },
9608 	{ "PCIE_FID_VFID", 0x43f0, 0 },
9615 		{ "RVF", 0, 8 },
9616 	{ "PCIE_FID_VFID", 0x43f4, 0 },
9623 		{ "RVF", 0, 8 },
9624 	{ "PCIE_FID_VFID", 0x43f8, 0 },
9631 		{ "RVF", 0, 8 },
9632 	{ "PCIE_FID_VFID", 0x43fc, 0 },
9639 		{ "RVF", 0, 8 },
9640 	{ "PCIE_FID_VFID", 0x4400, 0 },
9647 		{ "RVF", 0, 8 },
9648 	{ "PCIE_FID_VFID", 0x4404, 0 },
9655 		{ "RVF", 0, 8 },
9656 	{ "PCIE_FID_VFID", 0x4408, 0 },
9663 		{ "RVF", 0, 8 },
9664 	{ "PCIE_FID_VFID", 0x440c, 0 },
9671 		{ "RVF", 0, 8 },
9672 	{ "PCIE_FID_VFID", 0x4410, 0 },
9679 		{ "RVF", 0, 8 },
9680 	{ "PCIE_FID_VFID", 0x4414, 0 },
9687 		{ "RVF", 0, 8 },
9688 	{ "PCIE_FID_VFID", 0x4418, 0 },
9695 		{ "RVF", 0, 8 },
9696 	{ "PCIE_FID_VFID", 0x441c, 0 },
9703 		{ "RVF", 0, 8 },
9704 	{ "PCIE_FID_VFID", 0x4420, 0 },
9711 		{ "RVF", 0, 8 },
9712 	{ "PCIE_FID_VFID", 0x4424, 0 },
9719 		{ "RVF", 0, 8 },
9720 	{ "PCIE_FID_VFID", 0x4428, 0 },
9727 		{ "RVF", 0, 8 },
9728 	{ "PCIE_FID_VFID", 0x442c, 0 },
9735 		{ "RVF", 0, 8 },
9736 	{ "PCIE_FID_VFID", 0x4430, 0 },
9743 		{ "RVF", 0, 8 },
9744 	{ "PCIE_FID_VFID", 0x4434, 0 },
9751 		{ "RVF", 0, 8 },
9752 	{ "PCIE_FID_VFID", 0x4438, 0 },
9759 		{ "RVF", 0, 8 },
9760 	{ "PCIE_FID_VFID", 0x443c, 0 },
9767 		{ "RVF", 0, 8 },
9768 	{ "PCIE_FID_VFID", 0x4440, 0 },
9775 		{ "RVF", 0, 8 },
9776 	{ "PCIE_FID_VFID", 0x4444, 0 },
9783 		{ "RVF", 0, 8 },
9784 	{ "PCIE_FID_VFID", 0x4448, 0 },
9791 		{ "RVF", 0, 8 },
9792 	{ "PCIE_FID_VFID", 0x444c, 0 },
9799 		{ "RVF", 0, 8 },
9800 	{ "PCIE_FID_VFID", 0x4450, 0 },
9807 		{ "RVF", 0, 8 },
9808 	{ "PCIE_FID_VFID", 0x4454, 0 },
9815 		{ "RVF", 0, 8 },
9816 	{ "PCIE_FID_VFID", 0x4458, 0 },
9823 		{ "RVF", 0, 8 },
9824 	{ "PCIE_FID_VFID", 0x445c, 0 },
9831 		{ "RVF", 0, 8 },
9832 	{ "PCIE_FID_VFID", 0x4460, 0 },
9839 		{ "RVF", 0, 8 },
9840 	{ "PCIE_FID_VFID", 0x4464, 0 },
9847 		{ "RVF", 0, 8 },
9848 	{ "PCIE_FID_VFID", 0x4468, 0 },
9855 		{ "RVF", 0, 8 },
9856 	{ "PCIE_FID_VFID", 0x446c, 0 },
9863 		{ "RVF", 0, 8 },
9864 	{ "PCIE_FID_VFID", 0x4470, 0 },
9871 		{ "RVF", 0, 8 },
9872 	{ "PCIE_FID_VFID", 0x4474, 0 },
9879 		{ "RVF", 0, 8 },
9880 	{ "PCIE_FID_VFID", 0x4478, 0 },
9887 		{ "RVF", 0, 8 },
9888 	{ "PCIE_FID_VFID", 0x447c, 0 },
9895 		{ "RVF", 0, 8 },
9896 	{ "PCIE_FID_VFID", 0x4480, 0 },
9903 		{ "RVF", 0, 8 },
9904 	{ "PCIE_FID_VFID", 0x4484, 0 },
9911 		{ "RVF", 0, 8 },
9912 	{ "PCIE_FID_VFID", 0x4488, 0 },
9919 		{ "RVF", 0, 8 },
9920 	{ "PCIE_FID_VFID", 0x448c, 0 },
9927 		{ "RVF", 0, 8 },
9928 	{ "PCIE_FID_VFID", 0x4490, 0 },
9935 		{ "RVF", 0, 8 },
9936 	{ "PCIE_FID_VFID", 0x4494, 0 },
9943 		{ "RVF", 0, 8 },
9944 	{ "PCIE_FID_VFID", 0x4498, 0 },
9951 		{ "RVF", 0, 8 },
9952 	{ "PCIE_FID_VFID", 0x449c, 0 },
9959 		{ "RVF", 0, 8 },
9960 	{ "PCIE_FID_VFID", 0x44a0, 0 },
9967 		{ "RVF", 0, 8 },
9968 	{ "PCIE_FID_VFID", 0x44a4, 0 },
9975 		{ "RVF", 0, 8 },
9976 	{ "PCIE_FID_VFID", 0x44a8, 0 },
9983 		{ "RVF", 0, 8 },
9984 	{ "PCIE_FID_VFID", 0x44ac, 0 },
9991 		{ "RVF", 0, 8 },
9992 	{ "PCIE_FID_VFID", 0x44b0, 0 },
9999 		{ "RVF", 0, 8 },
10000 	{ "PCIE_FID_VFID", 0x44b4, 0 },
10007 		{ "RVF", 0, 8 },
10008 	{ "PCIE_FID_VFID", 0x44b8, 0 },
10015 		{ "RVF", 0, 8 },
10016 	{ "PCIE_FID_VFID", 0x44bc, 0 },
10023 		{ "RVF", 0, 8 },
10024 	{ "PCIE_FID_VFID", 0x44c0, 0 },
10031 		{ "RVF", 0, 8 },
10032 	{ "PCIE_FID_VFID", 0x44c4, 0 },
10039 		{ "RVF", 0, 8 },
10040 	{ "PCIE_FID_VFID", 0x44c8, 0 },
10047 		{ "RVF", 0, 8 },
10048 	{ "PCIE_FID_VFID", 0x44cc, 0 },
10055 		{ "RVF", 0, 8 },
10056 	{ "PCIE_FID_VFID", 0x44d0, 0 },
10063 		{ "RVF", 0, 8 },
10064 	{ "PCIE_FID_VFID", 0x44d4, 0 },
10071 		{ "RVF", 0, 8 },
10072 	{ "PCIE_FID_VFID", 0x44d8, 0 },
10079 		{ "RVF", 0, 8 },
10080 	{ "PCIE_FID_VFID", 0x44dc, 0 },
10087 		{ "RVF", 0, 8 },
10088 	{ "PCIE_FID_VFID", 0x44e0, 0 },
10095 		{ "RVF", 0, 8 },
10096 	{ "PCIE_FID_VFID", 0x44e4, 0 },
10103 		{ "RVF", 0, 8 },
10104 	{ "PCIE_FID_VFID", 0x44e8, 0 },
10111 		{ "RVF", 0, 8 },
10112 	{ "PCIE_FID_VFID", 0x44ec, 0 },
10119 		{ "RVF", 0, 8 },
10120 	{ "PCIE_FID_VFID", 0x44f0, 0 },
10127 		{ "RVF", 0, 8 },
10128 	{ "PCIE_FID_VFID", 0x44f4, 0 },
10135 		{ "RVF", 0, 8 },
10136 	{ "PCIE_FID_VFID", 0x44f8, 0 },
10143 		{ "RVF", 0, 8 },
10144 	{ "PCIE_FID_VFID", 0x44fc, 0 },
10151 		{ "RVF", 0, 8 },
10152 	{ "PCIE_FID_VFID", 0x4500, 0 },
10159 		{ "RVF", 0, 8 },
10160 	{ "PCIE_FID_VFID", 0x4504, 0 },
10167 		{ "RVF", 0, 8 },
10168 	{ "PCIE_FID_VFID", 0x4508, 0 },
10175 		{ "RVF", 0, 8 },
10176 	{ "PCIE_FID_VFID", 0x450c, 0 },
10183 		{ "RVF", 0, 8 },
10184 	{ "PCIE_FID_VFID", 0x4510, 0 },
10191 		{ "RVF", 0, 8 },
10192 	{ "PCIE_FID_VFID", 0x4514, 0 },
10199 		{ "RVF", 0, 8 },
10200 	{ "PCIE_FID_VFID", 0x4518, 0 },
10207 		{ "RVF", 0, 8 },
10208 	{ "PCIE_FID_VFID", 0x451c, 0 },
10215 		{ "RVF", 0, 8 },
10216 	{ "PCIE_FID_VFID", 0x4520, 0 },
10223 		{ "RVF", 0, 8 },
10224 	{ "PCIE_FID_VFID", 0x4524, 0 },
10231 		{ "RVF", 0, 8 },
10232 	{ "PCIE_FID_VFID", 0x4528, 0 },
10239 		{ "RVF", 0, 8 },
10240 	{ "PCIE_FID_VFID", 0x452c, 0 },
10247 		{ "RVF", 0, 8 },
10248 	{ "PCIE_FID_VFID", 0x4530, 0 },
10255 		{ "RVF", 0, 8 },
10256 	{ "PCIE_FID_VFID", 0x4534, 0 },
10263 		{ "RVF", 0, 8 },
10264 	{ "PCIE_FID_VFID", 0x4538, 0 },
10271 		{ "RVF", 0, 8 },
10272 	{ "PCIE_FID_VFID", 0x453c, 0 },
10279 		{ "RVF", 0, 8 },
10280 	{ "PCIE_FID_VFID", 0x4540, 0 },
10287 		{ "RVF", 0, 8 },
10288 	{ "PCIE_FID_VFID", 0x4544, 0 },
10295 		{ "RVF", 0, 8 },
10296 	{ "PCIE_FID_VFID", 0x4548, 0 },
10303 		{ "RVF", 0, 8 },
10304 	{ "PCIE_FID_VFID", 0x454c, 0 },
10311 		{ "RVF", 0, 8 },
10312 	{ "PCIE_FID_VFID", 0x4550, 0 },
10319 		{ "RVF", 0, 8 },
10320 	{ "PCIE_FID_VFID", 0x4554, 0 },
10327 		{ "RVF", 0, 8 },
10328 	{ "PCIE_FID_VFID", 0x4558, 0 },
10335 		{ "RVF", 0, 8 },
10336 	{ "PCIE_FID_VFID", 0x455c, 0 },
10343 		{ "RVF", 0, 8 },
10344 	{ "PCIE_FID_VFID", 0x4560, 0 },
10351 		{ "RVF", 0, 8 },
10352 	{ "PCIE_FID_VFID", 0x4564, 0 },
10359 		{ "RVF", 0, 8 },
10360 	{ "PCIE_FID_VFID", 0x4568, 0 },
10367 		{ "RVF", 0, 8 },
10368 	{ "PCIE_FID_VFID", 0x456c, 0 },
10375 		{ "RVF", 0, 8 },
10376 	{ "PCIE_FID_VFID", 0x4570, 0 },
10383 		{ "RVF", 0, 8 },
10384 	{ "PCIE_FID_VFID", 0x4574, 0 },
10391 		{ "RVF", 0, 8 },
10392 	{ "PCIE_FID_VFID", 0x4578, 0 },
10399 		{ "RVF", 0, 8 },
10400 	{ "PCIE_FID_VFID", 0x457c, 0 },
10407 		{ "RVF", 0, 8 },
10408 	{ "PCIE_FID_VFID", 0x4580, 0 },
10415 		{ "RVF", 0, 8 },
10416 	{ "PCIE_FID_VFID", 0x4584, 0 },
10423 		{ "RVF", 0, 8 },
10424 	{ "PCIE_FID_VFID", 0x4588, 0 },
10431 		{ "RVF", 0, 8 },
10432 	{ "PCIE_FID_VFID", 0x458c, 0 },
10439 		{ "RVF", 0, 8 },
10440 	{ "PCIE_FID_VFID", 0x4590, 0 },
10447 		{ "RVF", 0, 8 },
10448 	{ "PCIE_FID_VFID", 0x4594, 0 },
10455 		{ "RVF", 0, 8 },
10456 	{ "PCIE_FID_VFID", 0x4598, 0 },
10463 		{ "RVF", 0, 8 },
10464 	{ "PCIE_FID_VFID", 0x459c, 0 },
10471 		{ "RVF", 0, 8 },
10472 	{ "PCIE_FID_VFID", 0x45a0, 0 },
10479 		{ "RVF", 0, 8 },
10480 	{ "PCIE_FID_VFID", 0x45a4, 0 },
10487 		{ "RVF", 0, 8 },
10488 	{ "PCIE_FID_VFID", 0x45a8, 0 },
10495 		{ "RVF", 0, 8 },
10496 	{ "PCIE_FID_VFID", 0x45ac, 0 },
10503 		{ "RVF", 0, 8 },
10504 	{ "PCIE_FID_VFID", 0x45b0, 0 },
10511 		{ "RVF", 0, 8 },
10512 	{ "PCIE_FID_VFID", 0x45b4, 0 },
10519 		{ "RVF", 0, 8 },
10520 	{ "PCIE_FID_VFID", 0x45b8, 0 },
10527 		{ "RVF", 0, 8 },
10528 	{ "PCIE_FID_VFID", 0x45bc, 0 },
10535 		{ "RVF", 0, 8 },
10536 	{ "PCIE_FID_VFID", 0x45c0, 0 },
10543 		{ "RVF", 0, 8 },
10544 	{ "PCIE_FID_VFID", 0x45c4, 0 },
10551 		{ "RVF", 0, 8 },
10552 	{ "PCIE_FID_VFID", 0x45c8, 0 },
10559 		{ "RVF", 0, 8 },
10560 	{ "PCIE_FID_VFID", 0x45cc, 0 },
10567 		{ "RVF", 0, 8 },
10568 	{ "PCIE_FID_VFID", 0x45d0, 0 },
10575 		{ "RVF", 0, 8 },
10576 	{ "PCIE_FID_VFID", 0x45d4, 0 },
10583 		{ "RVF", 0, 8 },
10584 	{ "PCIE_FID_VFID", 0x45d8, 0 },
10591 		{ "RVF", 0, 8 },
10592 	{ "PCIE_FID_VFID", 0x45dc, 0 },
10599 		{ "RVF", 0, 8 },
10600 	{ "PCIE_FID_VFID", 0x45e0, 0 },
10607 		{ "RVF", 0, 8 },
10608 	{ "PCIE_FID_VFID", 0x45e4, 0 },
10615 		{ "RVF", 0, 8 },
10616 	{ "PCIE_FID_VFID", 0x45e8, 0 },
10623 		{ "RVF", 0, 8 },
10624 	{ "PCIE_FID_VFID", 0x45ec, 0 },
10631 		{ "RVF", 0, 8 },
10632 	{ "PCIE_FID_VFID", 0x45f0, 0 },
10639 		{ "RVF", 0, 8 },
10640 	{ "PCIE_FID_VFID", 0x45f4, 0 },
10647 		{ "RVF", 0, 8 },
10648 	{ "PCIE_FID_VFID", 0x45f8, 0 },
10655 		{ "RVF", 0, 8 },
10656 	{ "PCIE_FID_VFID", 0x45fc, 0 },
10663 		{ "RVF", 0, 8 },
10664 	{ "PCIE_FID_VFID", 0x4600, 0 },
10671 		{ "RVF", 0, 8 },
10672 	{ "PCIE_FID_VFID", 0x4604, 0 },
10679 		{ "RVF", 0, 8 },
10680 	{ "PCIE_FID_VFID", 0x4608, 0 },
10687 		{ "RVF", 0, 8 },
10688 	{ "PCIE_FID_VFID", 0x460c, 0 },
10695 		{ "RVF", 0, 8 },
10696 	{ "PCIE_FID_VFID", 0x4610, 0 },
10703 		{ "RVF", 0, 8 },
10704 	{ "PCIE_FID_VFID", 0x4614, 0 },
10711 		{ "RVF", 0, 8 },
10712 	{ "PCIE_FID_VFID", 0x4618, 0 },
10719 		{ "RVF", 0, 8 },
10720 	{ "PCIE_FID_VFID", 0x461c, 0 },
10727 		{ "RVF", 0, 8 },
10728 	{ "PCIE_FID_VFID", 0x4620, 0 },
10735 		{ "RVF", 0, 8 },
10736 	{ "PCIE_FID_VFID", 0x4624, 0 },
10743 		{ "RVF", 0, 8 },
10744 	{ "PCIE_FID_VFID", 0x4628, 0 },
10751 		{ "RVF", 0, 8 },
10752 	{ "PCIE_FID_VFID", 0x462c, 0 },
10759 		{ "RVF", 0, 8 },
10760 	{ "PCIE_FID_VFID", 0x4630, 0 },
10767 		{ "RVF", 0, 8 },
10768 	{ "PCIE_FID_VFID", 0x4634, 0 },
10775 		{ "RVF", 0, 8 },
10776 	{ "PCIE_FID_VFID", 0x4638, 0 },
10783 		{ "RVF", 0, 8 },
10784 	{ "PCIE_FID_VFID", 0x463c, 0 },
10791 		{ "RVF", 0, 8 },
10792 	{ "PCIE_FID_VFID", 0x4640, 0 },
10799 		{ "RVF", 0, 8 },
10800 	{ "PCIE_FID_VFID", 0x4644, 0 },
10807 		{ "RVF", 0, 8 },
10808 	{ "PCIE_FID_VFID", 0x4648, 0 },
10815 		{ "RVF", 0, 8 },
10816 	{ "PCIE_FID_VFID", 0x464c, 0 },
10823 		{ "RVF", 0, 8 },
10824 	{ "PCIE_FID_VFID", 0x4650, 0 },
10831 		{ "RVF", 0, 8 },
10832 	{ "PCIE_FID_VFID", 0x4654, 0 },
10839 		{ "RVF", 0, 8 },
10840 	{ "PCIE_FID_VFID", 0x4658, 0 },
10847 		{ "RVF", 0, 8 },
10848 	{ "PCIE_FID_VFID", 0x465c, 0 },
10855 		{ "RVF", 0, 8 },
10856 	{ "PCIE_FID_VFID", 0x4660, 0 },
10863 		{ "RVF", 0, 8 },
10864 	{ "PCIE_FID_VFID", 0x4664, 0 },
10871 		{ "RVF", 0, 8 },
10872 	{ "PCIE_FID_VFID", 0x4668, 0 },
10879 		{ "RVF", 0, 8 },
10880 	{ "PCIE_FID_VFID", 0x466c, 0 },
10887 		{ "RVF", 0, 8 },
10888 	{ "PCIE_FID_VFID", 0x4670, 0 },
10895 		{ "RVF", 0, 8 },
10896 	{ "PCIE_FID_VFID", 0x4674, 0 },
10903 		{ "RVF", 0, 8 },
10904 	{ "PCIE_FID_VFID", 0x4678, 0 },
10911 		{ "RVF", 0, 8 },
10912 	{ "PCIE_FID_VFID", 0x467c, 0 },
10919 		{ "RVF", 0, 8 },
10920 	{ "PCIE_FID_VFID", 0x4680, 0 },
10927 		{ "RVF", 0, 8 },
10928 	{ "PCIE_FID_VFID", 0x4684, 0 },
10935 		{ "RVF", 0, 8 },
10936 	{ "PCIE_FID_VFID", 0x4688, 0 },
10943 		{ "RVF", 0, 8 },
10944 	{ "PCIE_FID_VFID", 0x468c, 0 },
10951 		{ "RVF", 0, 8 },
10952 	{ "PCIE_FID_VFID", 0x4690, 0 },
10959 		{ "RVF", 0, 8 },
10960 	{ "PCIE_FID_VFID", 0x4694, 0 },
10967 		{ "RVF", 0, 8 },
10968 	{ "PCIE_FID_VFID", 0x4698, 0 },
10975 		{ "RVF", 0, 8 },
10976 	{ "PCIE_FID_VFID", 0x469c, 0 },
10983 		{ "RVF", 0, 8 },
10984 	{ "PCIE_FID_VFID", 0x46a0, 0 },
10991 		{ "RVF", 0, 8 },
10992 	{ "PCIE_FID_VFID", 0x46a4, 0 },
10999 		{ "RVF", 0, 8 },
11000 	{ "PCIE_FID_VFID", 0x46a8, 0 },
11007 		{ "RVF", 0, 8 },
11008 	{ "PCIE_FID_VFID", 0x46ac, 0 },
11015 		{ "RVF", 0, 8 },
11016 	{ "PCIE_FID_VFID", 0x46b0, 0 },
11023 		{ "RVF", 0, 8 },
11024 	{ "PCIE_FID_VFID", 0x46b4, 0 },
11031 		{ "RVF", 0, 8 },
11032 	{ "PCIE_FID_VFID", 0x46b8, 0 },
11039 		{ "RVF", 0, 8 },
11040 	{ "PCIE_FID_VFID", 0x46bc, 0 },
11047 		{ "RVF", 0, 8 },
11048 	{ "PCIE_FID_VFID", 0x46c0, 0 },
11055 		{ "RVF", 0, 8 },
11056 	{ "PCIE_FID_VFID", 0x46c4, 0 },
11063 		{ "RVF", 0, 8 },
11064 	{ "PCIE_FID_VFID", 0x46c8, 0 },
11071 		{ "RVF", 0, 8 },
11072 	{ "PCIE_FID_VFID", 0x46cc, 0 },
11079 		{ "RVF", 0, 8 },
11080 	{ "PCIE_FID_VFID", 0x46d0, 0 },
11087 		{ "RVF", 0, 8 },
11088 	{ "PCIE_FID_VFID", 0x46d4, 0 },
11095 		{ "RVF", 0, 8 },
11096 	{ "PCIE_FID_VFID", 0x46d8, 0 },
11103 		{ "RVF", 0, 8 },
11104 	{ "PCIE_FID_VFID", 0x46dc, 0 },
11111 		{ "RVF", 0, 8 },
11112 	{ "PCIE_FID_VFID", 0x46e0, 0 },
11119 		{ "RVF", 0, 8 },
11120 	{ "PCIE_FID_VFID", 0x46e4, 0 },
11127 		{ "RVF", 0, 8 },
11128 	{ "PCIE_FID_VFID", 0x46e8, 0 },
11135 		{ "RVF", 0, 8 },
11136 	{ "PCIE_FID_VFID", 0x46ec, 0 },
11143 		{ "RVF", 0, 8 },
11144 	{ "PCIE_FID_VFID", 0x46f0, 0 },
11151 		{ "RVF", 0, 8 },
11152 	{ "PCIE_FID_VFID", 0x46f4, 0 },
11159 		{ "RVF", 0, 8 },
11160 	{ "PCIE_FID_VFID", 0x46f8, 0 },
11167 		{ "RVF", 0, 8 },
11168 	{ "PCIE_FID_VFID", 0x46fc, 0 },
11175 		{ "RVF", 0, 8 },
11176 	{ "PCIE_FID_VFID", 0x4700, 0 },
11183 		{ "RVF", 0, 8 },
11184 	{ "PCIE_FID_VFID", 0x4704, 0 },
11191 		{ "RVF", 0, 8 },
11192 	{ "PCIE_FID_VFID", 0x4708, 0 },
11199 		{ "RVF", 0, 8 },
11200 	{ "PCIE_FID_VFID", 0x470c, 0 },
11207 		{ "RVF", 0, 8 },
11208 	{ "PCIE_FID_VFID", 0x4710, 0 },
11215 		{ "RVF", 0, 8 },
11216 	{ "PCIE_FID_VFID", 0x4714, 0 },
11223 		{ "RVF", 0, 8 },
11224 	{ "PCIE_FID_VFID", 0x4718, 0 },
11231 		{ "RVF", 0, 8 },
11232 	{ "PCIE_FID_VFID", 0x471c, 0 },
11239 		{ "RVF", 0, 8 },
11240 	{ "PCIE_FID_VFID", 0x4720, 0 },
11247 		{ "RVF", 0, 8 },
11248 	{ "PCIE_FID_VFID", 0x4724, 0 },
11255 		{ "RVF", 0, 8 },
11256 	{ "PCIE_FID_VFID", 0x4728, 0 },
11263 		{ "RVF", 0, 8 },
11264 	{ "PCIE_FID_VFID", 0x472c, 0 },
11271 		{ "RVF", 0, 8 },
11272 	{ "PCIE_FID_VFID", 0x4730, 0 },
11279 		{ "RVF", 0, 8 },
11280 	{ "PCIE_FID_VFID", 0x4734, 0 },
11287 		{ "RVF", 0, 8 },
11288 	{ "PCIE_FID_VFID", 0x4738, 0 },
11295 		{ "RVF", 0, 8 },
11296 	{ "PCIE_FID_VFID", 0x473c, 0 },
11303 		{ "RVF", 0, 8 },
11304 	{ "PCIE_FID_VFID", 0x4740, 0 },
11311 		{ "RVF", 0, 8 },
11312 	{ "PCIE_FID_VFID", 0x4744, 0 },
11319 		{ "RVF", 0, 8 },
11320 	{ "PCIE_FID_VFID", 0x4748, 0 },
11327 		{ "RVF", 0, 8 },
11328 	{ "PCIE_FID_VFID", 0x474c, 0 },
11335 		{ "RVF", 0, 8 },
11336 	{ "PCIE_FID_VFID", 0x4750, 0 },
11343 		{ "RVF", 0, 8 },
11344 	{ "PCIE_FID_VFID", 0x4754, 0 },
11351 		{ "RVF", 0, 8 },
11352 	{ "PCIE_FID_VFID", 0x4758, 0 },
11359 		{ "RVF", 0, 8 },
11360 	{ "PCIE_FID_VFID", 0x475c, 0 },
11367 		{ "RVF", 0, 8 },
11368 	{ "PCIE_FID_VFID", 0x4760, 0 },
11375 		{ "RVF", 0, 8 },
11376 	{ "PCIE_FID_VFID", 0x4764, 0 },
11383 		{ "RVF", 0, 8 },
11384 	{ "PCIE_FID_VFID", 0x4768, 0 },
11391 		{ "RVF", 0, 8 },
11392 	{ "PCIE_FID_VFID", 0x476c, 0 },
11399 		{ "RVF", 0, 8 },
11400 	{ "PCIE_FID_VFID", 0x4770, 0 },
11407 		{ "RVF", 0, 8 },
11408 	{ "PCIE_FID_VFID", 0x4774, 0 },
11415 		{ "RVF", 0, 8 },
11416 	{ "PCIE_FID_VFID", 0x4778, 0 },
11423 		{ "RVF", 0, 8 },
11424 	{ "PCIE_FID_VFID", 0x477c, 0 },
11431 		{ "RVF", 0, 8 },
11432 	{ "PCIE_FID_VFID", 0x4780, 0 },
11439 		{ "RVF", 0, 8 },
11440 	{ "PCIE_FID_VFID", 0x4784, 0 },
11447 		{ "RVF", 0, 8 },
11448 	{ "PCIE_FID_VFID", 0x4788, 0 },
11455 		{ "RVF", 0, 8 },
11456 	{ "PCIE_FID_VFID", 0x478c, 0 },
11463 		{ "RVF", 0, 8 },
11464 	{ "PCIE_FID_VFID", 0x4790, 0 },
11471 		{ "RVF", 0, 8 },
11472 	{ "PCIE_FID_VFID", 0x4794, 0 },
11479 		{ "RVF", 0, 8 },
11480 	{ "PCIE_FID_VFID", 0x4798, 0 },
11487 		{ "RVF", 0, 8 },
11488 	{ "PCIE_FID_VFID", 0x479c, 0 },
11495 		{ "RVF", 0, 8 },
11496 	{ "PCIE_FID_VFID", 0x47a0, 0 },
11503 		{ "RVF", 0, 8 },
11504 	{ "PCIE_FID_VFID", 0x47a4, 0 },
11511 		{ "RVF", 0, 8 },
11512 	{ "PCIE_FID_VFID", 0x47a8, 0 },
11519 		{ "RVF", 0, 8 },
11520 	{ "PCIE_FID_VFID", 0x47ac, 0 },
11527 		{ "RVF", 0, 8 },
11528 	{ "PCIE_FID_VFID", 0x47b0, 0 },
11535 		{ "RVF", 0, 8 },
11536 	{ "PCIE_FID_VFID", 0x47b4, 0 },
11543 		{ "RVF", 0, 8 },
11544 	{ "PCIE_FID_VFID", 0x47b8, 0 },
11551 		{ "RVF", 0, 8 },
11552 	{ "PCIE_FID_VFID", 0x47bc, 0 },
11559 		{ "RVF", 0, 8 },
11560 	{ "PCIE_FID_VFID", 0x47c0, 0 },
11567 		{ "RVF", 0, 8 },
11568 	{ "PCIE_FID_VFID", 0x47c4, 0 },
11575 		{ "RVF", 0, 8 },
11576 	{ "PCIE_FID_VFID", 0x47c8, 0 },
11583 		{ "RVF", 0, 8 },
11584 	{ "PCIE_FID_VFID", 0x47cc, 0 },
11591 		{ "RVF", 0, 8 },
11592 	{ "PCIE_FID_VFID", 0x47d0, 0 },
11599 		{ "RVF", 0, 8 },
11600 	{ "PCIE_FID_VFID", 0x47d4, 0 },
11607 		{ "RVF", 0, 8 },
11608 	{ "PCIE_FID_VFID", 0x47d8, 0 },
11615 		{ "RVF", 0, 8 },
11616 	{ "PCIE_FID_VFID", 0x47dc, 0 },
11623 		{ "RVF", 0, 8 },
11624 	{ "PCIE_FID_VFID", 0x47e0, 0 },
11631 		{ "RVF", 0, 8 },
11632 	{ "PCIE_FID_VFID", 0x47e4, 0 },
11639 		{ "RVF", 0, 8 },
11640 	{ "PCIE_FID_VFID", 0x47e8, 0 },
11647 		{ "RVF", 0, 8 },
11648 	{ "PCIE_FID_VFID", 0x47ec, 0 },
11655 		{ "RVF", 0, 8 },
11656 	{ "PCIE_FID_VFID", 0x47f0, 0 },
11663 		{ "RVF", 0, 8 },
11664 	{ "PCIE_FID_VFID", 0x47f4, 0 },
11671 		{ "RVF", 0, 8 },
11672 	{ "PCIE_FID_VFID", 0x47f8, 0 },
11679 		{ "RVF", 0, 8 },
11680 	{ "PCIE_FID_VFID", 0x47fc, 0 },
11687 		{ "RVF", 0, 8 },
11688 	{ "PCIE_FID_VFID", 0x4800, 0 },
11695 		{ "RVF", 0, 8 },
11696 	{ "PCIE_FID_VFID", 0x4804, 0 },
11703 		{ "RVF", 0, 8 },
11704 	{ "PCIE_FID_VFID", 0x4808, 0 },
11711 		{ "RVF", 0, 8 },
11712 	{ "PCIE_FID_VFID", 0x480c, 0 },
11719 		{ "RVF", 0, 8 },
11720 	{ "PCIE_FID_VFID", 0x4810, 0 },
11727 		{ "RVF", 0, 8 },
11728 	{ "PCIE_FID_VFID", 0x4814, 0 },
11735 		{ "RVF", 0, 8 },
11736 	{ "PCIE_FID_VFID", 0x4818, 0 },
11743 		{ "RVF", 0, 8 },
11744 	{ "PCIE_FID_VFID", 0x481c, 0 },
11751 		{ "RVF", 0, 8 },
11752 	{ "PCIE_FID_VFID", 0x4820, 0 },
11759 		{ "RVF", 0, 8 },
11760 	{ "PCIE_FID_VFID", 0x4824, 0 },
11767 		{ "RVF", 0, 8 },
11768 	{ "PCIE_FID_VFID", 0x4828, 0 },
11775 		{ "RVF", 0, 8 },
11776 	{ "PCIE_FID_VFID", 0x482c, 0 },
11783 		{ "RVF", 0, 8 },
11784 	{ "PCIE_FID_VFID", 0x4830, 0 },
11791 		{ "RVF", 0, 8 },
11792 	{ "PCIE_FID_VFID", 0x4834, 0 },
11799 		{ "RVF", 0, 8 },
11800 	{ "PCIE_FID_VFID", 0x4838, 0 },
11807 		{ "RVF", 0, 8 },
11808 	{ "PCIE_FID_VFID", 0x483c, 0 },
11815 		{ "RVF", 0, 8 },
11816 	{ "PCIE_FID_VFID", 0x4840, 0 },
11823 		{ "RVF", 0, 8 },
11824 	{ "PCIE_FID_VFID", 0x4844, 0 },
11831 		{ "RVF", 0, 8 },
11832 	{ "PCIE_FID_VFID", 0x4848, 0 },
11839 		{ "RVF", 0, 8 },
11840 	{ "PCIE_FID_VFID", 0x484c, 0 },
11847 		{ "RVF", 0, 8 },
11848 	{ "PCIE_FID_VFID", 0x4850, 0 },
11855 		{ "RVF", 0, 8 },
11856 	{ "PCIE_FID_VFID", 0x4854, 0 },
11863 		{ "RVF", 0, 8 },
11864 	{ "PCIE_FID_VFID", 0x4858, 0 },
11871 		{ "RVF", 0, 8 },
11872 	{ "PCIE_FID_VFID", 0x485c, 0 },
11879 		{ "RVF", 0, 8 },
11880 	{ "PCIE_FID_VFID", 0x4860, 0 },
11887 		{ "RVF", 0, 8 },
11888 	{ "PCIE_FID_VFID", 0x4864, 0 },
11895 		{ "RVF", 0, 8 },
11896 	{ "PCIE_FID_VFID", 0x4868, 0 },
11903 		{ "RVF", 0, 8 },
11904 	{ "PCIE_FID_VFID", 0x486c, 0 },
11911 		{ "RVF", 0, 8 },
11912 	{ "PCIE_FID_VFID", 0x4870, 0 },
11919 		{ "RVF", 0, 8 },
11920 	{ "PCIE_FID_VFID", 0x4874, 0 },
11927 		{ "RVF", 0, 8 },
11928 	{ "PCIE_FID_VFID", 0x4878, 0 },
11935 		{ "RVF", 0, 8 },
11936 	{ "PCIE_FID_VFID", 0x487c, 0 },
11943 		{ "RVF", 0, 8 },
11944 	{ "PCIE_FID_VFID", 0x4880, 0 },
11951 		{ "RVF", 0, 8 },
11952 	{ "PCIE_FID_VFID", 0x4884, 0 },
11959 		{ "RVF", 0, 8 },
11960 	{ "PCIE_FID_VFID", 0x4888, 0 },
11967 		{ "RVF", 0, 8 },
11968 	{ "PCIE_FID_VFID", 0x488c, 0 },
11975 		{ "RVF", 0, 8 },
11976 	{ "PCIE_FID_VFID", 0x4890, 0 },
11983 		{ "RVF", 0, 8 },
11984 	{ "PCIE_FID_VFID", 0x4894, 0 },
11991 		{ "RVF", 0, 8 },
11992 	{ "PCIE_FID_VFID", 0x4898, 0 },
11999 		{ "RVF", 0, 8 },
12000 	{ "PCIE_FID_VFID", 0x489c, 0 },
12007 		{ "RVF", 0, 8 },
12008 	{ "PCIE_FID_VFID", 0x48a0, 0 },
12015 		{ "RVF", 0, 8 },
12016 	{ "PCIE_FID_VFID", 0x48a4, 0 },
12023 		{ "RVF", 0, 8 },
12024 	{ "PCIE_FID_VFID", 0x48a8, 0 },
12031 		{ "RVF", 0, 8 },
12032 	{ "PCIE_FID_VFID", 0x48ac, 0 },
12039 		{ "RVF", 0, 8 },
12040 	{ "PCIE_FID_VFID", 0x48b0, 0 },
12047 		{ "RVF", 0, 8 },
12048 	{ "PCIE_FID_VFID", 0x48b4, 0 },
12055 		{ "RVF", 0, 8 },
12056 	{ "PCIE_FID_VFID", 0x48b8, 0 },
12063 		{ "RVF", 0, 8 },
12064 	{ "PCIE_FID_VFID", 0x48bc, 0 },
12071 		{ "RVF", 0, 8 },
12072 	{ "PCIE_FID_VFID", 0x48c0, 0 },
12079 		{ "RVF", 0, 8 },
12080 	{ "PCIE_FID_VFID", 0x48c4, 0 },
12087 		{ "RVF", 0, 8 },
12088 	{ "PCIE_FID_VFID", 0x48c8, 0 },
12095 		{ "RVF", 0, 8 },
12096 	{ "PCIE_FID_VFID", 0x48cc, 0 },
12103 		{ "RVF", 0, 8 },
12104 	{ "PCIE_FID_VFID", 0x48d0, 0 },
12111 		{ "RVF", 0, 8 },
12112 	{ "PCIE_FID_VFID", 0x48d4, 0 },
12119 		{ "RVF", 0, 8 },
12120 	{ "PCIE_FID_VFID", 0x48d8, 0 },
12127 		{ "RVF", 0, 8 },
12128 	{ "PCIE_FID_VFID", 0x48dc, 0 },
12135 		{ "RVF", 0, 8 },
12136 	{ "PCIE_FID_VFID", 0x48e0, 0 },
12143 		{ "RVF", 0, 8 },
12144 	{ "PCIE_FID_VFID", 0x48e4, 0 },
12151 		{ "RVF", 0, 8 },
12152 	{ "PCIE_FID_VFID", 0x48e8, 0 },
12159 		{ "RVF", 0, 8 },
12160 	{ "PCIE_FID_VFID", 0x48ec, 0 },
12167 		{ "RVF", 0, 8 },
12168 	{ "PCIE_FID_VFID", 0x48f0, 0 },
12175 		{ "RVF", 0, 8 },
12176 	{ "PCIE_FID_VFID", 0x48f4, 0 },
12183 		{ "RVF", 0, 8 },
12184 	{ "PCIE_FID_VFID", 0x48f8, 0 },
12191 		{ "RVF", 0, 8 },
12192 	{ "PCIE_FID_VFID", 0x48fc, 0 },
12199 		{ "RVF", 0, 8 },
12200 	{ "PCIE_FID_VFID", 0x4900, 0 },
12207 		{ "RVF", 0, 8 },
12208 	{ "PCIE_FID_VFID", 0x4904, 0 },
12215 		{ "RVF", 0, 8 },
12216 	{ "PCIE_FID_VFID", 0x4908, 0 },
12223 		{ "RVF", 0, 8 },
12224 	{ "PCIE_FID_VFID", 0x490c, 0 },
12231 		{ "RVF", 0, 8 },
12232 	{ "PCIE_FID_VFID", 0x4910, 0 },
12239 		{ "RVF", 0, 8 },
12240 	{ "PCIE_FID_VFID", 0x4914, 0 },
12247 		{ "RVF", 0, 8 },
12248 	{ "PCIE_FID_VFID", 0x4918, 0 },
12255 		{ "RVF", 0, 8 },
12256 	{ "PCIE_FID_VFID", 0x491c, 0 },
12263 		{ "RVF", 0, 8 },
12264 	{ "PCIE_FID_VFID", 0x4920, 0 },
12271 		{ "RVF", 0, 8 },
12272 	{ "PCIE_FID_VFID", 0x4924, 0 },
12279 		{ "RVF", 0, 8 },
12280 	{ "PCIE_FID_VFID", 0x4928, 0 },
12287 		{ "RVF", 0, 8 },
12288 	{ "PCIE_FID_VFID", 0x492c, 0 },
12295 		{ "RVF", 0, 8 },
12296 	{ "PCIE_FID_VFID", 0x4930, 0 },
12303 		{ "RVF", 0, 8 },
12304 	{ "PCIE_FID_VFID", 0x4934, 0 },
12311 		{ "RVF", 0, 8 },
12312 	{ "PCIE_FID_VFID", 0x4938, 0 },
12319 		{ "RVF", 0, 8 },
12320 	{ "PCIE_FID_VFID", 0x493c, 0 },
12327 		{ "RVF", 0, 8 },
12328 	{ "PCIE_FID_VFID", 0x4940, 0 },
12335 		{ "RVF", 0, 8 },
12336 	{ "PCIE_FID_VFID", 0x4944, 0 },
12343 		{ "RVF", 0, 8 },
12344 	{ "PCIE_FID_VFID", 0x4948, 0 },
12351 		{ "RVF", 0, 8 },
12352 	{ "PCIE_FID_VFID", 0x494c, 0 },
12359 		{ "RVF", 0, 8 },
12360 	{ "PCIE_FID_VFID", 0x4950, 0 },
12367 		{ "RVF", 0, 8 },
12368 	{ "PCIE_FID_VFID", 0x4954, 0 },
12375 		{ "RVF", 0, 8 },
12376 	{ "PCIE_FID_VFID", 0x4958, 0 },
12383 		{ "RVF", 0, 8 },
12384 	{ "PCIE_FID_VFID", 0x495c, 0 },
12391 		{ "RVF", 0, 8 },
12392 	{ "PCIE_FID_VFID", 0x4960, 0 },
12399 		{ "RVF", 0, 8 },
12400 	{ "PCIE_FID_VFID", 0x4964, 0 },
12407 		{ "RVF", 0, 8 },
12408 	{ "PCIE_FID_VFID", 0x4968, 0 },
12415 		{ "RVF", 0, 8 },
12416 	{ "PCIE_FID_VFID", 0x496c, 0 },
12423 		{ "RVF", 0, 8 },
12424 	{ "PCIE_FID_VFID", 0x4970, 0 },
12431 		{ "RVF", 0, 8 },
12432 	{ "PCIE_FID_VFID", 0x4974, 0 },
12439 		{ "RVF", 0, 8 },
12440 	{ "PCIE_FID_VFID", 0x4978, 0 },
12447 		{ "RVF", 0, 8 },
12448 	{ "PCIE_FID_VFID", 0x497c, 0 },
12455 		{ "RVF", 0, 8 },
12456 	{ "PCIE_FID_VFID", 0x4980, 0 },
12463 		{ "RVF", 0, 8 },
12464 	{ "PCIE_FID_VFID", 0x4984, 0 },
12471 		{ "RVF", 0, 8 },
12472 	{ "PCIE_FID_VFID", 0x4988, 0 },
12479 		{ "RVF", 0, 8 },
12480 	{ "PCIE_FID_VFID", 0x498c, 0 },
12487 		{ "RVF", 0, 8 },
12488 	{ "PCIE_FID_VFID", 0x4990, 0 },
12495 		{ "RVF", 0, 8 },
12496 	{ "PCIE_FID_VFID", 0x4994, 0 },
12503 		{ "RVF", 0, 8 },
12504 	{ "PCIE_FID_VFID", 0x4998, 0 },
12511 		{ "RVF", 0, 8 },
12512 	{ "PCIE_FID_VFID", 0x499c, 0 },
12519 		{ "RVF", 0, 8 },
12520 	{ "PCIE_FID_VFID", 0x49a0, 0 },
12527 		{ "RVF", 0, 8 },
12528 	{ "PCIE_FID_VFID", 0x49a4, 0 },
12535 		{ "RVF", 0, 8 },
12536 	{ "PCIE_FID_VFID", 0x49a8, 0 },
12543 		{ "RVF", 0, 8 },
12544 	{ "PCIE_FID_VFID", 0x49ac, 0 },
12551 		{ "RVF", 0, 8 },
12552 	{ "PCIE_FID_VFID", 0x49b0, 0 },
12559 		{ "RVF", 0, 8 },
12560 	{ "PCIE_FID_VFID", 0x49b4, 0 },
12567 		{ "RVF", 0, 8 },
12568 	{ "PCIE_FID_VFID", 0x49b8, 0 },
12575 		{ "RVF", 0, 8 },
12576 	{ "PCIE_FID_VFID", 0x49bc, 0 },
12583 		{ "RVF", 0, 8 },
12584 	{ "PCIE_FID_VFID", 0x49c0, 0 },
12591 		{ "RVF", 0, 8 },
12592 	{ "PCIE_FID_VFID", 0x49c4, 0 },
12599 		{ "RVF", 0, 8 },
12600 	{ "PCIE_FID_VFID", 0x49c8, 0 },
12607 		{ "RVF", 0, 8 },
12608 	{ "PCIE_FID_VFID", 0x49cc, 0 },
12615 		{ "RVF", 0, 8 },
12616 	{ "PCIE_FID_VFID", 0x49d0, 0 },
12623 		{ "RVF", 0, 8 },
12624 	{ "PCIE_FID_VFID", 0x49d4, 0 },
12631 		{ "RVF", 0, 8 },
12632 	{ "PCIE_FID_VFID", 0x49d8, 0 },
12639 		{ "RVF", 0, 8 },
12640 	{ "PCIE_FID_VFID", 0x49dc, 0 },
12647 		{ "RVF", 0, 8 },
12648 	{ "PCIE_FID_VFID", 0x49e0, 0 },
12655 		{ "RVF", 0, 8 },
12656 	{ "PCIE_FID_VFID", 0x49e4, 0 },
12663 		{ "RVF", 0, 8 },
12664 	{ "PCIE_FID_VFID", 0x49e8, 0 },
12671 		{ "RVF", 0, 8 },
12672 	{ "PCIE_FID_VFID", 0x49ec, 0 },
12679 		{ "RVF", 0, 8 },
12680 	{ "PCIE_FID_VFID", 0x49f0, 0 },
12687 		{ "RVF", 0, 8 },
12688 	{ "PCIE_FID_VFID", 0x49f4, 0 },
12695 		{ "RVF", 0, 8 },
12696 	{ "PCIE_FID_VFID", 0x49f8, 0 },
12703 		{ "RVF", 0, 8 },
12704 	{ "PCIE_FID_VFID", 0x49fc, 0 },
12711 		{ "RVF", 0, 8 },
12712 	{ "PCIE_FID_VFID", 0x4a00, 0 },
12719 		{ "RVF", 0, 8 },
12720 	{ "PCIE_FID_VFID", 0x4a04, 0 },
12727 		{ "RVF", 0, 8 },
12728 	{ "PCIE_FID_VFID", 0x4a08, 0 },
12735 		{ "RVF", 0, 8 },
12736 	{ "PCIE_FID_VFID", 0x4a0c, 0 },
12743 		{ "RVF", 0, 8 },
12744 	{ "PCIE_FID_VFID", 0x4a10, 0 },
12751 		{ "RVF", 0, 8 },
12752 	{ "PCIE_FID_VFID", 0x4a14, 0 },
12759 		{ "RVF", 0, 8 },
12760 	{ "PCIE_FID_VFID", 0x4a18, 0 },
12767 		{ "RVF", 0, 8 },
12768 	{ "PCIE_FID_VFID", 0x4a1c, 0 },
12775 		{ "RVF", 0, 8 },
12776 	{ "PCIE_FID_VFID", 0x4a20, 0 },
12783 		{ "RVF", 0, 8 },
12784 	{ "PCIE_FID_VFID", 0x4a24, 0 },
12791 		{ "RVF", 0, 8 },
12792 	{ "PCIE_FID_VFID", 0x4a28, 0 },
12799 		{ "RVF", 0, 8 },
12800 	{ "PCIE_FID_VFID", 0x4a2c, 0 },
12807 		{ "RVF", 0, 8 },
12808 	{ "PCIE_FID_VFID", 0x4a30, 0 },
12815 		{ "RVF", 0, 8 },
12816 	{ "PCIE_FID_VFID", 0x4a34, 0 },
12823 		{ "RVF", 0, 8 },
12824 	{ "PCIE_FID_VFID", 0x4a38, 0 },
12831 		{ "RVF", 0, 8 },
12832 	{ "PCIE_FID_VFID", 0x4a3c, 0 },
12839 		{ "RVF", 0, 8 },
12840 	{ "PCIE_FID_VFID", 0x4a40, 0 },
12847 		{ "RVF", 0, 8 },
12848 	{ "PCIE_FID_VFID", 0x4a44, 0 },
12855 		{ "RVF", 0, 8 },
12856 	{ "PCIE_FID_VFID", 0x4a48, 0 },
12863 		{ "RVF", 0, 8 },
12864 	{ "PCIE_FID_VFID", 0x4a4c, 0 },
12871 		{ "RVF", 0, 8 },
12872 	{ "PCIE_FID_VFID", 0x4a50, 0 },
12879 		{ "RVF", 0, 8 },
12880 	{ "PCIE_FID_VFID", 0x4a54, 0 },
12887 		{ "RVF", 0, 8 },
12888 	{ "PCIE_FID_VFID", 0x4a58, 0 },
12895 		{ "RVF", 0, 8 },
12896 	{ "PCIE_FID_VFID", 0x4a5c, 0 },
12903 		{ "RVF", 0, 8 },
12904 	{ "PCIE_FID_VFID", 0x4a60, 0 },
12911 		{ "RVF", 0, 8 },
12912 	{ "PCIE_FID_VFID", 0x4a64, 0 },
12919 		{ "RVF", 0, 8 },
12920 	{ "PCIE_FID_VFID", 0x4a68, 0 },
12927 		{ "RVF", 0, 8 },
12928 	{ "PCIE_FID_VFID", 0x4a6c, 0 },
12935 		{ "RVF", 0, 8 },
12936 	{ "PCIE_FID_VFID", 0x4a70, 0 },
12943 		{ "RVF", 0, 8 },
12944 	{ "PCIE_FID_VFID", 0x4a74, 0 },
12951 		{ "RVF", 0, 8 },
12952 	{ "PCIE_FID_VFID", 0x4a78, 0 },
12959 		{ "RVF", 0, 8 },
12960 	{ "PCIE_FID_VFID", 0x4a7c, 0 },
12967 		{ "RVF", 0, 8 },
12968 	{ "PCIE_FID_VFID", 0x4a80, 0 },
12975 		{ "RVF", 0, 8 },
12976 	{ "PCIE_FID_VFID", 0x4a84, 0 },
12983 		{ "RVF", 0, 8 },
12984 	{ "PCIE_FID_VFID", 0x4a88, 0 },
12991 		{ "RVF", 0, 8 },
12992 	{ "PCIE_FID_VFID", 0x4a8c, 0 },
12999 		{ "RVF", 0, 8 },
13000 	{ "PCIE_FID_VFID", 0x4a90, 0 },
13007 		{ "RVF", 0, 8 },
13008 	{ "PCIE_FID_VFID", 0x4a94, 0 },
13015 		{ "RVF", 0, 8 },
13016 	{ "PCIE_FID_VFID", 0x4a98, 0 },
13023 		{ "RVF", 0, 8 },
13024 	{ "PCIE_FID_VFID", 0x4a9c, 0 },
13031 		{ "RVF", 0, 8 },
13032 	{ "PCIE_FID_VFID", 0x4aa0, 0 },
13039 		{ "RVF", 0, 8 },
13040 	{ "PCIE_FID_VFID", 0x4aa4, 0 },
13047 		{ "RVF", 0, 8 },
13048 	{ "PCIE_FID_VFID", 0x4aa8, 0 },
13055 		{ "RVF", 0, 8 },
13056 	{ "PCIE_FID_VFID", 0x4aac, 0 },
13063 		{ "RVF", 0, 8 },
13064 	{ "PCIE_FID_VFID", 0x4ab0, 0 },
13071 		{ "RVF", 0, 8 },
13072 	{ "PCIE_FID_VFID", 0x4ab4, 0 },
13079 		{ "RVF", 0, 8 },
13080 	{ "PCIE_FID_VFID", 0x4ab8, 0 },
13087 		{ "RVF", 0, 8 },
13088 	{ "PCIE_FID_VFID", 0x4abc, 0 },
13095 		{ "RVF", 0, 8 },
13096 	{ "PCIE_FID_VFID", 0x4ac0, 0 },
13103 		{ "RVF", 0, 8 },
13104 	{ "PCIE_FID_VFID", 0x4ac4, 0 },
13111 		{ "RVF", 0, 8 },
13112 	{ "PCIE_FID_VFID", 0x4ac8, 0 },
13119 		{ "RVF", 0, 8 },
13120 	{ "PCIE_FID_VFID", 0x4acc, 0 },
13127 		{ "RVF", 0, 8 },
13128 	{ "PCIE_FID_VFID", 0x4ad0, 0 },
13135 		{ "RVF", 0, 8 },
13136 	{ "PCIE_FID_VFID", 0x4ad4, 0 },
13143 		{ "RVF", 0, 8 },
13144 	{ "PCIE_FID_VFID", 0x4ad8, 0 },
13151 		{ "RVF", 0, 8 },
13152 	{ "PCIE_FID_VFID", 0x4adc, 0 },
13159 		{ "RVF", 0, 8 },
13160 	{ "PCIE_FID_VFID", 0x4ae0, 0 },
13167 		{ "RVF", 0, 8 },
13168 	{ "PCIE_FID_VFID", 0x4ae4, 0 },
13175 		{ "RVF", 0, 8 },
13176 	{ "PCIE_FID_VFID", 0x4ae8, 0 },
13183 		{ "RVF", 0, 8 },
13184 	{ "PCIE_FID_VFID", 0x4aec, 0 },
13191 		{ "RVF", 0, 8 },
13192 	{ "PCIE_FID_VFID", 0x4af0, 0 },
13199 		{ "RVF", 0, 8 },
13200 	{ "PCIE_FID_VFID", 0x4af4, 0 },
13207 		{ "RVF", 0, 8 },
13208 	{ "PCIE_FID_VFID", 0x4af8, 0 },
13215 		{ "RVF", 0, 8 },
13216 	{ "PCIE_FID_VFID", 0x4afc, 0 },
13223 		{ "RVF", 0, 8 },
13224 	{ "PCIE_FID_VFID", 0x4b00, 0 },
13231 		{ "RVF", 0, 8 },
13232 	{ "PCIE_FID_VFID", 0x4b04, 0 },
13239 		{ "RVF", 0, 8 },
13240 	{ "PCIE_FID_VFID", 0x4b08, 0 },
13247 		{ "RVF", 0, 8 },
13248 	{ "PCIE_FID_VFID", 0x4b0c, 0 },
13255 		{ "RVF", 0, 8 },
13256 	{ "PCIE_FID_VFID", 0x4b10, 0 },
13263 		{ "RVF", 0, 8 },
13264 	{ "PCIE_FID_VFID", 0x4b14, 0 },
13271 		{ "RVF", 0, 8 },
13272 	{ "PCIE_FID_VFID", 0x4b18, 0 },
13279 		{ "RVF", 0, 8 },
13280 	{ "PCIE_FID_VFID", 0x4b1c, 0 },
13287 		{ "RVF", 0, 8 },
13288 	{ "PCIE_FID_VFID", 0x4b20, 0 },
13295 		{ "RVF", 0, 8 },
13296 	{ "PCIE_FID_VFID", 0x4b24, 0 },
13303 		{ "RVF", 0, 8 },
13304 	{ "PCIE_FID_VFID", 0x4b28, 0 },
13311 		{ "RVF", 0, 8 },
13312 	{ "PCIE_FID_VFID", 0x4b2c, 0 },
13319 		{ "RVF", 0, 8 },
13320 	{ "PCIE_FID_VFID", 0x4b30, 0 },
13327 		{ "RVF", 0, 8 },
13328 	{ "PCIE_FID_VFID", 0x4b34, 0 },
13335 		{ "RVF", 0, 8 },
13336 	{ "PCIE_FID_VFID", 0x4b38, 0 },
13343 		{ "RVF", 0, 8 },
13344 	{ "PCIE_FID_VFID", 0x4b3c, 0 },
13351 		{ "RVF", 0, 8 },
13352 	{ "PCIE_FID_VFID", 0x4b40, 0 },
13359 		{ "RVF", 0, 8 },
13360 	{ "PCIE_FID_VFID", 0x4b44, 0 },
13367 		{ "RVF", 0, 8 },
13368 	{ "PCIE_FID_VFID", 0x4b48, 0 },
13375 		{ "RVF", 0, 8 },
13376 	{ "PCIE_FID_VFID", 0x4b4c, 0 },
13383 		{ "RVF", 0, 8 },
13384 	{ "PCIE_FID_VFID", 0x4b50, 0 },
13391 		{ "RVF", 0, 8 },
13392 	{ "PCIE_FID_VFID", 0x4b54, 0 },
13399 		{ "RVF", 0, 8 },
13400 	{ "PCIE_FID_VFID", 0x4b58, 0 },
13407 		{ "RVF", 0, 8 },
13408 	{ "PCIE_FID_VFID", 0x4b5c, 0 },
13415 		{ "RVF", 0, 8 },
13416 	{ "PCIE_FID_VFID", 0x4b60, 0 },
13423 		{ "RVF", 0, 8 },
13424 	{ "PCIE_FID_VFID", 0x4b64, 0 },
13431 		{ "RVF", 0, 8 },
13432 	{ "PCIE_FID_VFID", 0x4b68, 0 },
13439 		{ "RVF", 0, 8 },
13440 	{ "PCIE_FID_VFID", 0x4b6c, 0 },
13447 		{ "RVF", 0, 8 },
13448 	{ "PCIE_FID_VFID", 0x4b70, 0 },
13455 		{ "RVF", 0, 8 },
13456 	{ "PCIE_FID_VFID", 0x4b74, 0 },
13463 		{ "RVF", 0, 8 },
13464 	{ "PCIE_FID_VFID", 0x4b78, 0 },
13471 		{ "RVF", 0, 8 },
13472 	{ "PCIE_FID_VFID", 0x4b7c, 0 },
13479 		{ "RVF", 0, 8 },
13480 	{ "PCIE_FID_VFID", 0x4b80, 0 },
13487 		{ "RVF", 0, 8 },
13488 	{ "PCIE_FID_VFID", 0x4b84, 0 },
13495 		{ "RVF", 0, 8 },
13496 	{ "PCIE_FID_VFID", 0x4b88, 0 },
13503 		{ "RVF", 0, 8 },
13504 	{ "PCIE_FID_VFID", 0x4b8c, 0 },
13511 		{ "RVF", 0, 8 },
13512 	{ "PCIE_FID_VFID", 0x4b90, 0 },
13519 		{ "RVF", 0, 8 },
13520 	{ "PCIE_FID_VFID", 0x4b94, 0 },
13527 		{ "RVF", 0, 8 },
13528 	{ "PCIE_FID_VFID", 0x4b98, 0 },
13535 		{ "RVF", 0, 8 },
13536 	{ "PCIE_FID_VFID", 0x4b9c, 0 },
13543 		{ "RVF", 0, 8 },
13544 	{ "PCIE_FID_VFID", 0x4ba0, 0 },
13551 		{ "RVF", 0, 8 },
13552 	{ "PCIE_FID_VFID", 0x4ba4, 0 },
13559 		{ "RVF", 0, 8 },
13560 	{ "PCIE_FID_VFID", 0x4ba8, 0 },
13567 		{ "RVF", 0, 8 },
13568 	{ "PCIE_FID_VFID", 0x4bac, 0 },
13575 		{ "RVF", 0, 8 },
13576 	{ "PCIE_FID_VFID", 0x4bb0, 0 },
13583 		{ "RVF", 0, 8 },
13584 	{ "PCIE_FID_VFID", 0x4bb4, 0 },
13591 		{ "RVF", 0, 8 },
13592 	{ "PCIE_FID_VFID", 0x4bb8, 0 },
13599 		{ "RVF", 0, 8 },
13600 	{ "PCIE_FID_VFID", 0x4bbc, 0 },
13607 		{ "RVF", 0, 8 },
13608 	{ "PCIE_FID_VFID", 0x4bc0, 0 },
13615 		{ "RVF", 0, 8 },
13616 	{ "PCIE_FID_VFID", 0x4bc4, 0 },
13623 		{ "RVF", 0, 8 },
13624 	{ "PCIE_FID_VFID", 0x4bc8, 0 },
13631 		{ "RVF", 0, 8 },
13632 	{ "PCIE_FID_VFID", 0x4bcc, 0 },
13639 		{ "RVF", 0, 8 },
13640 	{ "PCIE_FID_VFID", 0x4bd0, 0 },
13647 		{ "RVF", 0, 8 },
13648 	{ "PCIE_FID_VFID", 0x4bd4, 0 },
13655 		{ "RVF", 0, 8 },
13656 	{ "PCIE_FID_VFID", 0x4bd8, 0 },
13663 		{ "RVF", 0, 8 },
13664 	{ "PCIE_FID_VFID", 0x4bdc, 0 },
13671 		{ "RVF", 0, 8 },
13672 	{ "PCIE_FID_VFID", 0x4be0, 0 },
13679 		{ "RVF", 0, 8 },
13680 	{ "PCIE_FID_VFID", 0x4be4, 0 },
13687 		{ "RVF", 0, 8 },
13688 	{ "PCIE_FID_VFID", 0x4be8, 0 },
13695 		{ "RVF", 0, 8 },
13696 	{ "PCIE_FID_VFID", 0x4bec, 0 },
13703 		{ "RVF", 0, 8 },
13704 	{ "PCIE_FID_VFID", 0x4bf0, 0 },
13711 		{ "RVF", 0, 8 },
13712 	{ "PCIE_FID_VFID", 0x4bf4, 0 },
13719 		{ "RVF", 0, 8 },
13720 	{ "PCIE_FID_VFID", 0x4bf8, 0 },
13727 		{ "RVF", 0, 8 },
13728 	{ "PCIE_FID_VFID", 0x4bfc, 0 },
13735 		{ "RVF", 0, 8 },
13736 	{ "PCIE_FID_VFID", 0x4c00, 0 },
13743 		{ "RVF", 0, 8 },
13744 	{ "PCIE_FID_VFID", 0x4c04, 0 },
13751 		{ "RVF", 0, 8 },
13752 	{ "PCIE_FID_VFID", 0x4c08, 0 },
13759 		{ "RVF", 0, 8 },
13760 	{ "PCIE_FID_VFID", 0x4c0c, 0 },
13767 		{ "RVF", 0, 8 },
13768 	{ "PCIE_FID_VFID", 0x4c10, 0 },
13775 		{ "RVF", 0, 8 },
13776 	{ "PCIE_FID_VFID", 0x4c14, 0 },
13783 		{ "RVF", 0, 8 },
13784 	{ "PCIE_FID_VFID", 0x4c18, 0 },
13791 		{ "RVF", 0, 8 },
13792 	{ "PCIE_FID_VFID", 0x4c1c, 0 },
13799 		{ "RVF", 0, 8 },
13800 	{ "PCIE_FID_VFID", 0x4c20, 0 },
13807 		{ "RVF", 0, 8 },
13808 	{ "PCIE_FID_VFID", 0x4c24, 0 },
13815 		{ "RVF", 0, 8 },
13816 	{ "PCIE_FID_VFID", 0x4c28, 0 },
13823 		{ "RVF", 0, 8 },
13824 	{ "PCIE_FID_VFID", 0x4c2c, 0 },
13831 		{ "RVF", 0, 8 },
13832 	{ "PCIE_FID_VFID", 0x4c30, 0 },
13839 		{ "RVF", 0, 8 },
13840 	{ "PCIE_FID_VFID", 0x4c34, 0 },
13847 		{ "RVF", 0, 8 },
13848 	{ "PCIE_FID_VFID", 0x4c38, 0 },
13855 		{ "RVF", 0, 8 },
13856 	{ "PCIE_FID_VFID", 0x4c3c, 0 },
13863 		{ "RVF", 0, 8 },
13864 	{ "PCIE_FID_VFID", 0x4c40, 0 },
13871 		{ "RVF", 0, 8 },
13872 	{ "PCIE_FID_VFID", 0x4c44, 0 },
13879 		{ "RVF", 0, 8 },
13880 	{ "PCIE_FID_VFID", 0x4c48, 0 },
13887 		{ "RVF", 0, 8 },
13888 	{ "PCIE_FID_VFID", 0x4c4c, 0 },
13895 		{ "RVF", 0, 8 },
13896 	{ "PCIE_FID_VFID", 0x4c50, 0 },
13903 		{ "RVF", 0, 8 },
13904 	{ "PCIE_FID_VFID", 0x4c54, 0 },
13911 		{ "RVF", 0, 8 },
13912 	{ "PCIE_FID_VFID", 0x4c58, 0 },
13919 		{ "RVF", 0, 8 },
13920 	{ "PCIE_FID_VFID", 0x4c5c, 0 },
13927 		{ "RVF", 0, 8 },
13928 	{ "PCIE_FID_VFID", 0x4c60, 0 },
13935 		{ "RVF", 0, 8 },
13936 	{ "PCIE_FID_VFID", 0x4c64, 0 },
13943 		{ "RVF", 0, 8 },
13944 	{ "PCIE_FID_VFID", 0x4c68, 0 },
13951 		{ "RVF", 0, 8 },
13952 	{ "PCIE_FID_VFID", 0x4c6c, 0 },
13959 		{ "RVF", 0, 8 },
13960 	{ "PCIE_FID_VFID", 0x4c70, 0 },
13967 		{ "RVF", 0, 8 },
13968 	{ "PCIE_FID_VFID", 0x4c74, 0 },
13975 		{ "RVF", 0, 8 },
13976 	{ "PCIE_FID_VFID", 0x4c78, 0 },
13983 		{ "RVF", 0, 8 },
13984 	{ "PCIE_FID_VFID", 0x4c7c, 0 },
13991 		{ "RVF", 0, 8 },
13992 	{ "PCIE_FID_VFID", 0x4c80, 0 },
13999 		{ "RVF", 0, 8 },
14000 	{ "PCIE_FID_VFID", 0x4c84, 0 },
14007 		{ "RVF", 0, 8 },
14008 	{ "PCIE_FID_VFID", 0x4c88, 0 },
14015 		{ "RVF", 0, 8 },
14016 	{ "PCIE_FID_VFID", 0x4c8c, 0 },
14023 		{ "RVF", 0, 8 },
14024 	{ "PCIE_FID_VFID", 0x4c90, 0 },
14031 		{ "RVF", 0, 8 },
14032 	{ "PCIE_FID_VFID", 0x4c94, 0 },
14039 		{ "RVF", 0, 8 },
14040 	{ "PCIE_FID_VFID", 0x4c98, 0 },
14047 		{ "RVF", 0, 8 },
14048 	{ "PCIE_FID_VFID", 0x4c9c, 0 },
14055 		{ "RVF", 0, 8 },
14056 	{ "PCIE_FID_VFID", 0x4ca0, 0 },
14063 		{ "RVF", 0, 8 },
14064 	{ "PCIE_FID_VFID", 0x4ca4, 0 },
14071 		{ "RVF", 0, 8 },
14072 	{ "PCIE_FID_VFID", 0x4ca8, 0 },
14079 		{ "RVF", 0, 8 },
14080 	{ "PCIE_FID_VFID", 0x4cac, 0 },
14087 		{ "RVF", 0, 8 },
14088 	{ "PCIE_FID_VFID", 0x4cb0, 0 },
14095 		{ "RVF", 0, 8 },
14096 	{ "PCIE_FID_VFID", 0x4cb4, 0 },
14103 		{ "RVF", 0, 8 },
14104 	{ "PCIE_FID_VFID", 0x4cb8, 0 },
14111 		{ "RVF", 0, 8 },
14112 	{ "PCIE_FID_VFID", 0x4cbc, 0 },
14119 		{ "RVF", 0, 8 },
14120 	{ "PCIE_FID_VFID", 0x4cc0, 0 },
14127 		{ "RVF", 0, 8 },
14128 	{ "PCIE_FID_VFID", 0x4cc4, 0 },
14135 		{ "RVF", 0, 8 },
14136 	{ "PCIE_FID_VFID", 0x4cc8, 0 },
14143 		{ "RVF", 0, 8 },
14144 	{ "PCIE_FID_VFID", 0x4ccc, 0 },
14151 		{ "RVF", 0, 8 },
14152 	{ "PCIE_FID_VFID", 0x4cd0, 0 },
14159 		{ "RVF", 0, 8 },
14160 	{ "PCIE_FID_VFID", 0x4cd4, 0 },
14167 		{ "RVF", 0, 8 },
14168 	{ "PCIE_FID_VFID", 0x4cd8, 0 },
14175 		{ "RVF", 0, 8 },
14176 	{ "PCIE_FID_VFID", 0x4cdc, 0 },
14183 		{ "RVF", 0, 8 },
14184 	{ "PCIE_FID_VFID", 0x4ce0, 0 },
14191 		{ "RVF", 0, 8 },
14192 	{ "PCIE_FID_VFID", 0x4ce4, 0 },
14199 		{ "RVF", 0, 8 },
14200 	{ "PCIE_FID_VFID", 0x4ce8, 0 },
14207 		{ "RVF", 0, 8 },
14208 	{ "PCIE_FID_VFID", 0x4cec, 0 },
14215 		{ "RVF", 0, 8 },
14216 	{ "PCIE_FID_VFID", 0x4cf0, 0 },
14223 		{ "RVF", 0, 8 },
14224 	{ "PCIE_FID_VFID", 0x4cf4, 0 },
14231 		{ "RVF", 0, 8 },
14232 	{ "PCIE_FID_VFID", 0x4cf8, 0 },
14239 		{ "RVF", 0, 8 },
14240 	{ "PCIE_FID_VFID", 0x4cfc, 0 },
14247 		{ "RVF", 0, 8 },
14248 	{ "PCIE_FID_VFID", 0x4d00, 0 },
14255 		{ "RVF", 0, 8 },
14256 	{ "PCIE_FID_VFID", 0x4d04, 0 },
14263 		{ "RVF", 0, 8 },
14264 	{ "PCIE_FID_VFID", 0x4d08, 0 },
14271 		{ "RVF", 0, 8 },
14272 	{ "PCIE_FID_VFID", 0x4d0c, 0 },
14279 		{ "RVF", 0, 8 },
14280 	{ "PCIE_FID_VFID", 0x4d10, 0 },
14287 		{ "RVF", 0, 8 },
14288 	{ "PCIE_FID_VFID", 0x4d14, 0 },
14295 		{ "RVF", 0, 8 },
14296 	{ "PCIE_FID_VFID", 0x4d18, 0 },
14303 		{ "RVF", 0, 8 },
14304 	{ "PCIE_FID_VFID", 0x4d1c, 0 },
14311 		{ "RVF", 0, 8 },
14312 	{ "PCIE_FID_VFID", 0x4d20, 0 },
14319 		{ "RVF", 0, 8 },
14320 	{ "PCIE_FID_VFID", 0x4d24, 0 },
14327 		{ "RVF", 0, 8 },
14328 	{ "PCIE_FID_VFID", 0x4d28, 0 },
14335 		{ "RVF", 0, 8 },
14336 	{ "PCIE_FID_VFID", 0x4d2c, 0 },
14343 		{ "RVF", 0, 8 },
14344 	{ "PCIE_FID_VFID", 0x4d30, 0 },
14351 		{ "RVF", 0, 8 },
14352 	{ "PCIE_FID_VFID", 0x4d34, 0 },
14359 		{ "RVF", 0, 8 },
14360 	{ "PCIE_FID_VFID", 0x4d38, 0 },
14367 		{ "RVF", 0, 8 },
14368 	{ "PCIE_FID_VFID", 0x4d3c, 0 },
14375 		{ "RVF", 0, 8 },
14376 	{ "PCIE_FID_VFID", 0x4d40, 0 },
14383 		{ "RVF", 0, 8 },
14384 	{ "PCIE_FID_VFID", 0x4d44, 0 },
14391 		{ "RVF", 0, 8 },
14392 	{ "PCIE_FID_VFID", 0x4d48, 0 },
14399 		{ "RVF", 0, 8 },
14400 	{ "PCIE_FID_VFID", 0x4d4c, 0 },
14407 		{ "RVF", 0, 8 },
14408 	{ "PCIE_FID_VFID", 0x4d50, 0 },
14415 		{ "RVF", 0, 8 },
14416 	{ "PCIE_FID_VFID", 0x4d54, 0 },
14423 		{ "RVF", 0, 8 },
14424 	{ "PCIE_FID_VFID", 0x4d58, 0 },
14431 		{ "RVF", 0, 8 },
14432 	{ "PCIE_FID_VFID", 0x4d5c, 0 },
14439 		{ "RVF", 0, 8 },
14440 	{ "PCIE_FID_VFID", 0x4d60, 0 },
14447 		{ "RVF", 0, 8 },
14448 	{ "PCIE_FID_VFID", 0x4d64, 0 },
14455 		{ "RVF", 0, 8 },
14456 	{ "PCIE_FID_VFID", 0x4d68, 0 },
14463 		{ "RVF", 0, 8 },
14464 	{ "PCIE_FID_VFID", 0x4d6c, 0 },
14471 		{ "RVF", 0, 8 },
14472 	{ "PCIE_FID_VFID", 0x4d70, 0 },
14479 		{ "RVF", 0, 8 },
14480 	{ "PCIE_FID_VFID", 0x4d74, 0 },
14487 		{ "RVF", 0, 8 },
14488 	{ "PCIE_FID_VFID", 0x4d78, 0 },
14495 		{ "RVF", 0, 8 },
14496 	{ "PCIE_FID_VFID", 0x4d7c, 0 },
14503 		{ "RVF", 0, 8 },
14504 	{ "PCIE_FID_VFID", 0x4d80, 0 },
14511 		{ "RVF", 0, 8 },
14512 	{ "PCIE_FID_VFID", 0x4d84, 0 },
14519 		{ "RVF", 0, 8 },
14520 	{ "PCIE_FID_VFID", 0x4d88, 0 },
14527 		{ "RVF", 0, 8 },
14528 	{ "PCIE_FID_VFID", 0x4d8c, 0 },
14535 		{ "RVF", 0, 8 },
14536 	{ "PCIE_FID_VFID", 0x4d90, 0 },
14543 		{ "RVF", 0, 8 },
14544 	{ "PCIE_FID_VFID", 0x4d94, 0 },
14551 		{ "RVF", 0, 8 },
14552 	{ "PCIE_FID_VFID", 0x4d98, 0 },
14559 		{ "RVF", 0, 8 },
14560 	{ "PCIE_FID_VFID", 0x4d9c, 0 },
14567 		{ "RVF", 0, 8 },
14568 	{ "PCIE_FID_VFID", 0x4da0, 0 },
14575 		{ "RVF", 0, 8 },
14576 	{ "PCIE_FID_VFID", 0x4da4, 0 },
14583 		{ "RVF", 0, 8 },
14584 	{ "PCIE_FID_VFID", 0x4da8, 0 },
14591 		{ "RVF", 0, 8 },
14592 	{ "PCIE_FID_VFID", 0x4dac, 0 },
14599 		{ "RVF", 0, 8 },
14600 	{ "PCIE_FID_VFID", 0x4db0, 0 },
14607 		{ "RVF", 0, 8 },
14608 	{ "PCIE_FID_VFID", 0x4db4, 0 },
14615 		{ "RVF", 0, 8 },
14616 	{ "PCIE_FID_VFID", 0x4db8, 0 },
14623 		{ "RVF", 0, 8 },
14624 	{ "PCIE_FID_VFID", 0x4dbc, 0 },
14631 		{ "RVF", 0, 8 },
14632 	{ "PCIE_FID_VFID", 0x4dc0, 0 },
14639 		{ "RVF", 0, 8 },
14640 	{ "PCIE_FID_VFID", 0x4dc4, 0 },
14647 		{ "RVF", 0, 8 },
14648 	{ "PCIE_FID_VFID", 0x4dc8, 0 },
14655 		{ "RVF", 0, 8 },
14656 	{ "PCIE_FID_VFID", 0x4dcc, 0 },
14663 		{ "RVF", 0, 8 },
14664 	{ "PCIE_FID_VFID", 0x4dd0, 0 },
14671 		{ "RVF", 0, 8 },
14672 	{ "PCIE_FID_VFID", 0x4dd4, 0 },
14679 		{ "RVF", 0, 8 },
14680 	{ "PCIE_FID_VFID", 0x4dd8, 0 },
14687 		{ "RVF", 0, 8 },
14688 	{ "PCIE_FID_VFID", 0x4ddc, 0 },
14695 		{ "RVF", 0, 8 },
14696 	{ "PCIE_FID_VFID", 0x4de0, 0 },
14703 		{ "RVF", 0, 8 },
14704 	{ "PCIE_FID_VFID", 0x4de4, 0 },
14711 		{ "RVF", 0, 8 },
14712 	{ "PCIE_FID_VFID", 0x4de8, 0 },
14719 		{ "RVF", 0, 8 },
14720 	{ "PCIE_FID_VFID", 0x4dec, 0 },
14727 		{ "RVF", 0, 8 },
14728 	{ "PCIE_FID_VFID", 0x4df0, 0 },
14735 		{ "RVF", 0, 8 },
14736 	{ "PCIE_FID_VFID", 0x4df4, 0 },
14743 		{ "RVF", 0, 8 },
14744 	{ "PCIE_FID_VFID", 0x4df8, 0 },
14751 		{ "RVF", 0, 8 },
14752 	{ "PCIE_FID_VFID", 0x4dfc, 0 },
14759 		{ "RVF", 0, 8 },
14760 	{ "PCIE_FID_VFID", 0x4e00, 0 },
14767 		{ "RVF", 0, 8 },
14768 	{ "PCIE_FID_VFID", 0x4e04, 0 },
14775 		{ "RVF", 0, 8 },
14776 	{ "PCIE_FID_VFID", 0x4e08, 0 },
14783 		{ "RVF", 0, 8 },
14784 	{ "PCIE_FID_VFID", 0x4e0c, 0 },
14791 		{ "RVF", 0, 8 },
14792 	{ "PCIE_FID_VFID", 0x4e10, 0 },
14799 		{ "RVF", 0, 8 },
14800 	{ "PCIE_FID_VFID", 0x4e14, 0 },
14807 		{ "RVF", 0, 8 },
14808 	{ "PCIE_FID_VFID", 0x4e18, 0 },
14815 		{ "RVF", 0, 8 },
14816 	{ "PCIE_FID_VFID", 0x4e1c, 0 },
14823 		{ "RVF", 0, 8 },
14824 	{ "PCIE_FID_VFID", 0x4e20, 0 },
14831 		{ "RVF", 0, 8 },
14832 	{ "PCIE_FID_VFID", 0x4e24, 0 },
14839 		{ "RVF", 0, 8 },
14840 	{ "PCIE_FID_VFID", 0x4e28, 0 },
14847 		{ "RVF", 0, 8 },
14848 	{ "PCIE_FID_VFID", 0x4e2c, 0 },
14855 		{ "RVF", 0, 8 },
14856 	{ "PCIE_FID_VFID", 0x4e30, 0 },
14863 		{ "RVF", 0, 8 },
14864 	{ "PCIE_FID_VFID", 0x4e34, 0 },
14871 		{ "RVF", 0, 8 },
14872 	{ "PCIE_FID_VFID", 0x4e38, 0 },
14879 		{ "RVF", 0, 8 },
14880 	{ "PCIE_FID_VFID", 0x4e3c, 0 },
14887 		{ "RVF", 0, 8 },
14888 	{ "PCIE_FID_VFID", 0x4e40, 0 },
14895 		{ "RVF", 0, 8 },
14896 	{ "PCIE_FID_VFID", 0x4e44, 0 },
14903 		{ "RVF", 0, 8 },
14904 	{ "PCIE_FID_VFID", 0x4e48, 0 },
14911 		{ "RVF", 0, 8 },
14912 	{ "PCIE_FID_VFID", 0x4e4c, 0 },
14919 		{ "RVF", 0, 8 },
14920 	{ "PCIE_FID_VFID", 0x4e50, 0 },
14927 		{ "RVF", 0, 8 },
14928 	{ "PCIE_FID_VFID", 0x4e54, 0 },
14935 		{ "RVF", 0, 8 },
14936 	{ "PCIE_FID_VFID", 0x4e58, 0 },
14943 		{ "RVF", 0, 8 },
14944 	{ "PCIE_FID_VFID", 0x4e5c, 0 },
14951 		{ "RVF", 0, 8 },
14952 	{ "PCIE_FID_VFID", 0x4e60, 0 },
14959 		{ "RVF", 0, 8 },
14960 	{ "PCIE_FID_VFID", 0x4e64, 0 },
14967 		{ "RVF", 0, 8 },
14968 	{ "PCIE_FID_VFID", 0x4e68, 0 },
14975 		{ "RVF", 0, 8 },
14976 	{ "PCIE_FID_VFID", 0x4e6c, 0 },
14983 		{ "RVF", 0, 8 },
14984 	{ "PCIE_FID_VFID", 0x4e70, 0 },
14991 		{ "RVF", 0, 8 },
14992 	{ "PCIE_FID_VFID", 0x4e74, 0 },
14999 		{ "RVF", 0, 8 },
15000 	{ "PCIE_FID_VFID", 0x4e78, 0 },
15007 		{ "RVF", 0, 8 },
15008 	{ "PCIE_FID_VFID", 0x4e7c, 0 },
15015 		{ "RVF", 0, 8 },
15016 	{ "PCIE_FID_VFID", 0x4e80, 0 },
15023 		{ "RVF", 0, 8 },
15024 	{ "PCIE_FID_VFID", 0x4e84, 0 },
15031 		{ "RVF", 0, 8 },
15032 	{ "PCIE_FID_VFID", 0x4e88, 0 },
15039 		{ "RVF", 0, 8 },
15040 	{ "PCIE_FID_VFID", 0x4e8c, 0 },
15047 		{ "RVF", 0, 8 },
15048 	{ "PCIE_FID_VFID", 0x4e90, 0 },
15055 		{ "RVF", 0, 8 },
15056 	{ "PCIE_FID_VFID", 0x4e94, 0 },
15063 		{ "RVF", 0, 8 },
15064 	{ "PCIE_FID_VFID", 0x4e98, 0 },
15071 		{ "RVF", 0, 8 },
15072 	{ "PCIE_FID_VFID", 0x4e9c, 0 },
15079 		{ "RVF", 0, 8 },
15080 	{ "PCIE_FID_VFID", 0x4ea0, 0 },
15087 		{ "RVF", 0, 8 },
15088 	{ "PCIE_FID_VFID", 0x4ea4, 0 },
15095 		{ "RVF", 0, 8 },
15096 	{ "PCIE_FID_VFID", 0x4ea8, 0 },
15103 		{ "RVF", 0, 8 },
15104 	{ "PCIE_FID_VFID", 0x4eac, 0 },
15111 		{ "RVF", 0, 8 },
15112 	{ "PCIE_FID_VFID", 0x4eb0, 0 },
15119 		{ "RVF", 0, 8 },
15120 	{ "PCIE_FID_VFID", 0x4eb4, 0 },
15127 		{ "RVF", 0, 8 },
15128 	{ "PCIE_FID_VFID", 0x4eb8, 0 },
15135 		{ "RVF", 0, 8 },
15136 	{ "PCIE_FID_VFID", 0x4ebc, 0 },
15143 		{ "RVF", 0, 8 },
15144 	{ "PCIE_FID_VFID", 0x4ec0, 0 },
15151 		{ "RVF", 0, 8 },
15152 	{ "PCIE_FID_VFID", 0x4ec4, 0 },
15159 		{ "RVF", 0, 8 },
15160 	{ "PCIE_FID_VFID", 0x4ec8, 0 },
15167 		{ "RVF", 0, 8 },
15168 	{ "PCIE_FID_VFID", 0x4ecc, 0 },
15175 		{ "RVF", 0, 8 },
15176 	{ "PCIE_FID_VFID", 0x4ed0, 0 },
15183 		{ "RVF", 0, 8 },
15184 	{ "PCIE_FID_VFID", 0x4ed4, 0 },
15191 		{ "RVF", 0, 8 },
15192 	{ "PCIE_FID_VFID", 0x4ed8, 0 },
15199 		{ "RVF", 0, 8 },
15200 	{ "PCIE_FID_VFID", 0x4edc, 0 },
15207 		{ "RVF", 0, 8 },
15208 	{ "PCIE_FID_VFID", 0x4ee0, 0 },
15215 		{ "RVF", 0, 8 },
15216 	{ "PCIE_FID_VFID", 0x4ee4, 0 },
15223 		{ "RVF", 0, 8 },
15224 	{ "PCIE_FID_VFID", 0x4ee8, 0 },
15231 		{ "RVF", 0, 8 },
15232 	{ "PCIE_FID_VFID", 0x4eec, 0 },
15239 		{ "RVF", 0, 8 },
15240 	{ "PCIE_FID_VFID", 0x4ef0, 0 },
15247 		{ "RVF", 0, 8 },
15248 	{ "PCIE_FID_VFID", 0x4ef4, 0 },
15255 		{ "RVF", 0, 8 },
15256 	{ "PCIE_FID_VFID", 0x4ef8, 0 },
15263 		{ "RVF", 0, 8 },
15264 	{ "PCIE_FID_VFID", 0x4efc, 0 },
15271 		{ "RVF", 0, 8 },
15272 	{ "PCIE_FID_VFID", 0x4f00, 0 },
15279 		{ "RVF", 0, 8 },
15280 	{ "PCIE_FID_VFID", 0x4f04, 0 },
15287 		{ "RVF", 0, 8 },
15288 	{ "PCIE_FID_VFID", 0x4f08, 0 },
15295 		{ "RVF", 0, 8 },
15296 	{ "PCIE_FID_VFID", 0x4f0c, 0 },
15303 		{ "RVF", 0, 8 },
15304 	{ "PCIE_FID_VFID", 0x4f10, 0 },
15311 		{ "RVF", 0, 8 },
15312 	{ "PCIE_FID_VFID", 0x4f14, 0 },
15319 		{ "RVF", 0, 8 },
15320 	{ "PCIE_FID_VFID", 0x4f18, 0 },
15327 		{ "RVF", 0, 8 },
15328 	{ "PCIE_FID_VFID", 0x4f1c, 0 },
15335 		{ "RVF", 0, 8 },
15336 	{ "PCIE_FID_VFID", 0x4f20, 0 },
15343 		{ "RVF", 0, 8 },
15344 	{ "PCIE_FID_VFID", 0x4f24, 0 },
15351 		{ "RVF", 0, 8 },
15352 	{ "PCIE_FID_VFID", 0x4f28, 0 },
15359 		{ "RVF", 0, 8 },
15360 	{ "PCIE_FID_VFID", 0x4f2c, 0 },
15367 		{ "RVF", 0, 8 },
15368 	{ "PCIE_FID_VFID", 0x4f30, 0 },
15375 		{ "RVF", 0, 8 },
15376 	{ "PCIE_FID_VFID", 0x4f34, 0 },
15383 		{ "RVF", 0, 8 },
15384 	{ "PCIE_FID_VFID", 0x4f38, 0 },
15391 		{ "RVF", 0, 8 },
15392 	{ "PCIE_FID_VFID", 0x4f3c, 0 },
15399 		{ "RVF", 0, 8 },
15400 	{ "PCIE_FID_VFID", 0x4f40, 0 },
15407 		{ "RVF", 0, 8 },
15408 	{ "PCIE_FID_VFID", 0x4f44, 0 },
15415 		{ "RVF", 0, 8 },
15416 	{ "PCIE_FID_VFID", 0x4f48, 0 },
15423 		{ "RVF", 0, 8 },
15424 	{ "PCIE_FID_VFID", 0x4f4c, 0 },
15431 		{ "RVF", 0, 8 },
15432 	{ "PCIE_FID_VFID", 0x4f50, 0 },
15439 		{ "RVF", 0, 8 },
15440 	{ "PCIE_FID_VFID", 0x4f54, 0 },
15447 		{ "RVF", 0, 8 },
15448 	{ "PCIE_FID_VFID", 0x4f58, 0 },
15455 		{ "RVF", 0, 8 },
15456 	{ "PCIE_FID_VFID", 0x4f5c, 0 },
15463 		{ "RVF", 0, 8 },
15464 	{ "PCIE_FID_VFID", 0x4f60, 0 },
15471 		{ "RVF", 0, 8 },
15472 	{ "PCIE_FID_VFID", 0x4f64, 0 },
15479 		{ "RVF", 0, 8 },
15480 	{ "PCIE_FID_VFID", 0x4f68, 0 },
15487 		{ "RVF", 0, 8 },
15488 	{ "PCIE_FID_VFID", 0x4f6c, 0 },
15495 		{ "RVF", 0, 8 },
15496 	{ "PCIE_FID_VFID", 0x4f70, 0 },
15503 		{ "RVF", 0, 8 },
15504 	{ "PCIE_FID_VFID", 0x4f74, 0 },
15511 		{ "RVF", 0, 8 },
15512 	{ "PCIE_FID_VFID", 0x4f78, 0 },
15519 		{ "RVF", 0, 8 },
15520 	{ "PCIE_FID_VFID", 0x4f7c, 0 },
15527 		{ "RVF", 0, 8 },
15528 	{ "PCIE_FID_VFID", 0x4f80, 0 },
15535 		{ "RVF", 0, 8 },
15536 	{ "PCIE_FID_VFID", 0x4f84, 0 },
15543 		{ "RVF", 0, 8 },
15544 	{ "PCIE_FID_VFID", 0x4f88, 0 },
15551 		{ "RVF", 0, 8 },
15552 	{ "PCIE_FID_VFID", 0x4f8c, 0 },
15559 		{ "RVF", 0, 8 },
15560 	{ "PCIE_FID_VFID", 0x4f90, 0 },
15567 		{ "RVF", 0, 8 },
15568 	{ "PCIE_FID_VFID", 0x4f94, 0 },
15575 		{ "RVF", 0, 8 },
15576 	{ "PCIE_FID_VFID", 0x4f98, 0 },
15583 		{ "RVF", 0, 8 },
15584 	{ "PCIE_FID_VFID", 0x4f9c, 0 },
15591 		{ "RVF", 0, 8 },
15592 	{ "PCIE_FID_VFID", 0x4fa0, 0 },
15599 		{ "RVF", 0, 8 },
15600 	{ "PCIE_FID_VFID", 0x4fa4, 0 },
15607 		{ "RVF", 0, 8 },
15608 	{ "PCIE_FID_VFID", 0x4fa8, 0 },
15615 		{ "RVF", 0, 8 },
15616 	{ "PCIE_FID_VFID", 0x4fac, 0 },
15623 		{ "RVF", 0, 8 },
15624 	{ "PCIE_FID_VFID", 0x4fb0, 0 },
15631 		{ "RVF", 0, 8 },
15632 	{ "PCIE_FID_VFID", 0x4fb4, 0 },
15639 		{ "RVF", 0, 8 },
15640 	{ "PCIE_FID_VFID", 0x4fb8, 0 },
15647 		{ "RVF", 0, 8 },
15648 	{ "PCIE_FID_VFID", 0x4fbc, 0 },
15655 		{ "RVF", 0, 8 },
15656 	{ "PCIE_FID_VFID", 0x4fc0, 0 },
15663 		{ "RVF", 0, 8 },
15664 	{ "PCIE_FID_VFID", 0x4fc4, 0 },
15671 		{ "RVF", 0, 8 },
15672 	{ "PCIE_FID_VFID", 0x4fc8, 0 },
15679 		{ "RVF", 0, 8 },
15680 	{ "PCIE_FID_VFID", 0x4fcc, 0 },
15687 		{ "RVF", 0, 8 },
15688 	{ "PCIE_FID_VFID", 0x4fd0, 0 },
15695 		{ "RVF", 0, 8 },
15696 	{ "PCIE_FID_VFID", 0x4fd4, 0 },
15703 		{ "RVF", 0, 8 },
15704 	{ "PCIE_FID_VFID", 0x4fd8, 0 },
15711 		{ "RVF", 0, 8 },
15712 	{ "PCIE_FID_VFID", 0x4fdc, 0 },
15719 		{ "RVF", 0, 8 },
15720 	{ "PCIE_FID_VFID", 0x4fe0, 0 },
15727 		{ "RVF", 0, 8 },
15728 	{ "PCIE_FID_VFID", 0x4fe4, 0 },
15735 		{ "RVF", 0, 8 },
15736 	{ "PCIE_FID_VFID", 0x4fe8, 0 },
15743 		{ "RVF", 0, 8 },
15744 	{ "PCIE_FID_VFID", 0x4fec, 0 },
15751 		{ "RVF", 0, 8 },
15752 	{ "PCIE_FID_VFID", 0x4ff0, 0 },
15759 		{ "RVF", 0, 8 },
15760 	{ "PCIE_FID_VFID", 0x4ff4, 0 },
15767 		{ "RVF", 0, 8 },
15768 	{ "PCIE_FID_VFID", 0x4ff8, 0 },
15775 		{ "RVF", 0, 8 },
15776 	{ "PCIE_FID_VFID", 0x4ffc, 0 },
15783 		{ "RVF", 0, 8 },
15784 	{ "PCIE_FID_VFID", 0x5000, 0 },
15791 		{ "RVF", 0, 8 },
15792 	{ "PCIE_FID_VFID", 0x5004, 0 },
15799 		{ "RVF", 0, 8 },
15800 	{ "PCIE_FID_VFID", 0x5008, 0 },
15807 		{ "RVF", 0, 8 },
15808 	{ "PCIE_FID_VFID", 0x500c, 0 },
15815 		{ "RVF", 0, 8 },
15816 	{ "PCIE_FID_VFID", 0x5010, 0 },
15823 		{ "RVF", 0, 8 },
15824 	{ "PCIE_FID_VFID", 0x5014, 0 },
15831 		{ "RVF", 0, 8 },
15832 	{ "PCIE_FID_VFID", 0x5018, 0 },
15839 		{ "RVF", 0, 8 },
15840 	{ "PCIE_FID_VFID", 0x501c, 0 },
15847 		{ "RVF", 0, 8 },
15848 	{ "PCIE_FID_VFID", 0x5020, 0 },
15855 		{ "RVF", 0, 8 },
15856 	{ "PCIE_FID_VFID", 0x5024, 0 },
15863 		{ "RVF", 0, 8 },
15864 	{ "PCIE_FID_VFID", 0x5028, 0 },
15871 		{ "RVF", 0, 8 },
15872 	{ "PCIE_FID_VFID", 0x502c, 0 },
15879 		{ "RVF", 0, 8 },
15880 	{ "PCIE_FID_VFID", 0x5030, 0 },
15887 		{ "RVF", 0, 8 },
15888 	{ "PCIE_FID_VFID", 0x5034, 0 },
15895 		{ "RVF", 0, 8 },
15896 	{ "PCIE_FID_VFID", 0x5038, 0 },
15903 		{ "RVF", 0, 8 },
15904 	{ "PCIE_FID_VFID", 0x503c, 0 },
15911 		{ "RVF", 0, 8 },
15912 	{ "PCIE_FID_VFID", 0x5040, 0 },
15919 		{ "RVF", 0, 8 },
15920 	{ "PCIE_FID_VFID", 0x5044, 0 },
15927 		{ "RVF", 0, 8 },
15928 	{ "PCIE_FID_VFID", 0x5048, 0 },
15935 		{ "RVF", 0, 8 },
15936 	{ "PCIE_FID_VFID", 0x504c, 0 },
15943 		{ "RVF", 0, 8 },
15944 	{ "PCIE_FID_VFID", 0x5050, 0 },
15951 		{ "RVF", 0, 8 },
15952 	{ "PCIE_FID_VFID", 0x5054, 0 },
15959 		{ "RVF", 0, 8 },
15960 	{ "PCIE_FID_VFID", 0x5058, 0 },
15967 		{ "RVF", 0, 8 },
15968 	{ "PCIE_FID_VFID", 0x505c, 0 },
15975 		{ "RVF", 0, 8 },
15976 	{ "PCIE_FID_VFID", 0x5060, 0 },
15983 		{ "RVF", 0, 8 },
15984 	{ "PCIE_FID_VFID", 0x5064, 0 },
15991 		{ "RVF", 0, 8 },
15992 	{ "PCIE_FID_VFID", 0x5068, 0 },
15999 		{ "RVF", 0, 8 },
16000 	{ "PCIE_FID_VFID", 0x506c, 0 },
16007 		{ "RVF", 0, 8 },
16008 	{ "PCIE_FID_VFID", 0x5070, 0 },
16015 		{ "RVF", 0, 8 },
16016 	{ "PCIE_FID_VFID", 0x5074, 0 },
16023 		{ "RVF", 0, 8 },
16024 	{ "PCIE_FID_VFID", 0x5078, 0 },
16031 		{ "RVF", 0, 8 },
16032 	{ "PCIE_FID_VFID", 0x507c, 0 },
16039 		{ "RVF", 0, 8 },
16040 	{ "PCIE_FID_VFID", 0x5080, 0 },
16047 		{ "RVF", 0, 8 },
16048 	{ "PCIE_FID_VFID", 0x5084, 0 },
16055 		{ "RVF", 0, 8 },
16056 	{ "PCIE_FID_VFID", 0x5088, 0 },
16063 		{ "RVF", 0, 8 },
16064 	{ "PCIE_FID_VFID", 0x508c, 0 },
16071 		{ "RVF", 0, 8 },
16072 	{ "PCIE_FID_VFID", 0x5090, 0 },
16079 		{ "RVF", 0, 8 },
16080 	{ "PCIE_FID_VFID", 0x5094, 0 },
16087 		{ "RVF", 0, 8 },
16088 	{ "PCIE_FID_VFID", 0x5098, 0 },
16095 		{ "RVF", 0, 8 },
16096 	{ "PCIE_FID_VFID", 0x509c, 0 },
16103 		{ "RVF", 0, 8 },
16104 	{ "PCIE_FID_VFID", 0x50a0, 0 },
16111 		{ "RVF", 0, 8 },
16112 	{ "PCIE_FID_VFID", 0x50a4, 0 },
16119 		{ "RVF", 0, 8 },
16120 	{ "PCIE_FID_VFID", 0x50a8, 0 },
16127 		{ "RVF", 0, 8 },
16128 	{ "PCIE_FID_VFID", 0x50ac, 0 },
16135 		{ "RVF", 0, 8 },
16136 	{ "PCIE_FID_VFID", 0x50b0, 0 },
16143 		{ "RVF", 0, 8 },
16144 	{ "PCIE_FID_VFID", 0x50b4, 0 },
16151 		{ "RVF", 0, 8 },
16152 	{ "PCIE_FID_VFID", 0x50b8, 0 },
16159 		{ "RVF", 0, 8 },
16160 	{ "PCIE_FID_VFID", 0x50bc, 0 },
16167 		{ "RVF", 0, 8 },
16168 	{ "PCIE_FID_VFID", 0x50c0, 0 },
16175 		{ "RVF", 0, 8 },
16176 	{ "PCIE_FID_VFID", 0x50c4, 0 },
16183 		{ "RVF", 0, 8 },
16184 	{ "PCIE_FID_VFID", 0x50c8, 0 },
16191 		{ "RVF", 0, 8 },
16192 	{ "PCIE_FID_VFID", 0x50cc, 0 },
16199 		{ "RVF", 0, 8 },
16200 	{ "PCIE_FID_VFID", 0x50d0, 0 },
16207 		{ "RVF", 0, 8 },
16208 	{ "PCIE_FID_VFID", 0x50d4, 0 },
16215 		{ "RVF", 0, 8 },
16216 	{ "PCIE_FID_VFID", 0x50d8, 0 },
16223 		{ "RVF", 0, 8 },
16224 	{ "PCIE_FID_VFID", 0x50dc, 0 },
16231 		{ "RVF", 0, 8 },
16232 	{ "PCIE_FID_VFID", 0x50e0, 0 },
16239 		{ "RVF", 0, 8 },
16240 	{ "PCIE_FID_VFID", 0x50e4, 0 },
16247 		{ "RVF", 0, 8 },
16248 	{ "PCIE_FID_VFID", 0x50e8, 0 },
16255 		{ "RVF", 0, 8 },
16256 	{ "PCIE_FID_VFID", 0x50ec, 0 },
16263 		{ "RVF", 0, 8 },
16264 	{ "PCIE_FID_VFID", 0x50f0, 0 },
16271 		{ "RVF", 0, 8 },
16272 	{ "PCIE_FID_VFID", 0x50f4, 0 },
16279 		{ "RVF", 0, 8 },
16280 	{ "PCIE_FID_VFID", 0x50f8, 0 },
16287 		{ "RVF", 0, 8 },
16288 	{ "PCIE_FID_VFID", 0x50fc, 0 },
16295 		{ "RVF", 0, 8 },
16296 	{ "PCIE_FID_VFID", 0x5100, 0 },
16303 		{ "RVF", 0, 8 },
16304 	{ "PCIE_FID_VFID", 0x5104, 0 },
16311 		{ "RVF", 0, 8 },
16312 	{ "PCIE_FID_VFID", 0x5108, 0 },
16319 		{ "RVF", 0, 8 },
16320 	{ "PCIE_FID_VFID", 0x510c, 0 },
16327 		{ "RVF", 0, 8 },
16328 	{ "PCIE_FID_VFID", 0x5110, 0 },
16335 		{ "RVF", 0, 8 },
16336 	{ "PCIE_FID_VFID", 0x5114, 0 },
16343 		{ "RVF", 0, 8 },
16344 	{ "PCIE_FID_VFID", 0x5118, 0 },
16351 		{ "RVF", 0, 8 },
16352 	{ "PCIE_FID_VFID", 0x511c, 0 },
16359 		{ "RVF", 0, 8 },
16360 	{ "PCIE_FID_VFID", 0x5120, 0 },
16367 		{ "RVF", 0, 8 },
16368 	{ "PCIE_FID_VFID", 0x5124, 0 },
16375 		{ "RVF", 0, 8 },
16376 	{ "PCIE_FID_VFID", 0x5128, 0 },
16383 		{ "RVF", 0, 8 },
16384 	{ "PCIE_FID_VFID", 0x512c, 0 },
16391 		{ "RVF", 0, 8 },
16392 	{ "PCIE_FID_VFID", 0x5130, 0 },
16399 		{ "RVF", 0, 8 },
16400 	{ "PCIE_FID_VFID", 0x5134, 0 },
16407 		{ "RVF", 0, 8 },
16408 	{ "PCIE_FID_VFID", 0x5138, 0 },
16415 		{ "RVF", 0, 8 },
16416 	{ "PCIE_FID_VFID", 0x513c, 0 },
16423 		{ "RVF", 0, 8 },
16424 	{ "PCIE_FID_VFID", 0x5140, 0 },
16431 		{ "RVF", 0, 8 },
16432 	{ "PCIE_FID_VFID", 0x5144, 0 },
16439 		{ "RVF", 0, 8 },
16440 	{ "PCIE_FID_VFID", 0x5148, 0 },
16447 		{ "RVF", 0, 8 },
16448 	{ "PCIE_FID_VFID", 0x514c, 0 },
16455 		{ "RVF", 0, 8 },
16456 	{ "PCIE_FID_VFID", 0x5150, 0 },
16463 		{ "RVF", 0, 8 },
16464 	{ "PCIE_FID_VFID", 0x5154, 0 },
16471 		{ "RVF", 0, 8 },
16472 	{ "PCIE_FID_VFID", 0x5158, 0 },
16479 		{ "RVF", 0, 8 },
16480 	{ "PCIE_FID_VFID", 0x515c, 0 },
16487 		{ "RVF", 0, 8 },
16488 	{ "PCIE_FID_VFID", 0x5160, 0 },
16495 		{ "RVF", 0, 8 },
16496 	{ "PCIE_FID_VFID", 0x5164, 0 },
16503 		{ "RVF", 0, 8 },
16504 	{ "PCIE_FID_VFID", 0x5168, 0 },
16511 		{ "RVF", 0, 8 },
16512 	{ "PCIE_FID_VFID", 0x516c, 0 },
16519 		{ "RVF", 0, 8 },
16520 	{ "PCIE_FID_VFID", 0x5170, 0 },
16527 		{ "RVF", 0, 8 },
16528 	{ "PCIE_FID_VFID", 0x5174, 0 },
16535 		{ "RVF", 0, 8 },
16536 	{ "PCIE_FID_VFID", 0x5178, 0 },
16543 		{ "RVF", 0, 8 },
16544 	{ "PCIE_FID_VFID", 0x517c, 0 },
16551 		{ "RVF", 0, 8 },
16552 	{ "PCIE_FID_VFID", 0x5180, 0 },
16559 		{ "RVF", 0, 8 },
16560 	{ "PCIE_FID_VFID", 0x5184, 0 },
16567 		{ "RVF", 0, 8 },
16568 	{ "PCIE_FID_VFID", 0x5188, 0 },
16575 		{ "RVF", 0, 8 },
16576 	{ "PCIE_FID_VFID", 0x518c, 0 },
16583 		{ "RVF", 0, 8 },
16584 	{ "PCIE_FID_VFID", 0x5190, 0 },
16591 		{ "RVF", 0, 8 },
16592 	{ "PCIE_FID_VFID", 0x5194, 0 },
16599 		{ "RVF", 0, 8 },
16600 	{ "PCIE_FID_VFID", 0x5198, 0 },
16607 		{ "RVF", 0, 8 },
16608 	{ "PCIE_FID_VFID", 0x519c, 0 },
16615 		{ "RVF", 0, 8 },
16616 	{ "PCIE_FID_VFID", 0x51a0, 0 },
16623 		{ "RVF", 0, 8 },
16624 	{ "PCIE_FID_VFID", 0x51a4, 0 },
16631 		{ "RVF", 0, 8 },
16632 	{ "PCIE_FID_VFID", 0x51a8, 0 },
16639 		{ "RVF", 0, 8 },
16640 	{ "PCIE_FID_VFID", 0x51ac, 0 },
16647 		{ "RVF", 0, 8 },
16648 	{ "PCIE_FID_VFID", 0x51b0, 0 },
16655 		{ "RVF", 0, 8 },
16656 	{ "PCIE_FID_VFID", 0x51b4, 0 },
16663 		{ "RVF", 0, 8 },
16664 	{ "PCIE_FID_VFID", 0x51b8, 0 },
16671 		{ "RVF", 0, 8 },
16672 	{ "PCIE_FID_VFID", 0x51bc, 0 },
16679 		{ "RVF", 0, 8 },
16680 	{ "PCIE_FID_VFID", 0x51c0, 0 },
16687 		{ "RVF", 0, 8 },
16688 	{ "PCIE_FID_VFID", 0x51c4, 0 },
16695 		{ "RVF", 0, 8 },
16696 	{ "PCIE_FID_VFID", 0x51c8, 0 },
16703 		{ "RVF", 0, 8 },
16704 	{ "PCIE_FID_VFID", 0x51cc, 0 },
16711 		{ "RVF", 0, 8 },
16712 	{ "PCIE_FID_VFID", 0x51d0, 0 },
16719 		{ "RVF", 0, 8 },
16720 	{ "PCIE_FID_VFID", 0x51d4, 0 },
16727 		{ "RVF", 0, 8 },
16728 	{ "PCIE_FID_VFID", 0x51d8, 0 },
16735 		{ "RVF", 0, 8 },
16736 	{ "PCIE_FID_VFID", 0x51dc, 0 },
16743 		{ "RVF", 0, 8 },
16744 	{ "PCIE_FID_VFID", 0x51e0, 0 },
16751 		{ "RVF", 0, 8 },
16752 	{ "PCIE_FID_VFID", 0x51e4, 0 },
16759 		{ "RVF", 0, 8 },
16760 	{ "PCIE_FID_VFID", 0x51e8, 0 },
16767 		{ "RVF", 0, 8 },
16768 	{ "PCIE_FID_VFID", 0x51ec, 0 },
16775 		{ "RVF", 0, 8 },
16776 	{ "PCIE_FID_VFID", 0x51f0, 0 },
16783 		{ "RVF", 0, 8 },
16784 	{ "PCIE_FID_VFID", 0x51f4, 0 },
16791 		{ "RVF", 0, 8 },
16792 	{ "PCIE_FID_VFID", 0x51f8, 0 },
16799 		{ "RVF", 0, 8 },
16800 	{ "PCIE_FID_VFID", 0x51fc, 0 },
16807 		{ "RVF", 0, 8 },
16808 	{ "PCIE_FID_VFID", 0x5200, 0 },
16815 		{ "RVF", 0, 8 },
16816 	{ "PCIE_FID_VFID", 0x5204, 0 },
16823 		{ "RVF", 0, 8 },
16824 	{ "PCIE_FID_VFID", 0x5208, 0 },
16831 		{ "RVF", 0, 8 },
16832 	{ "PCIE_FID_VFID", 0x520c, 0 },
16839 		{ "RVF", 0, 8 },
16840 	{ "PCIE_FID_VFID", 0x5210, 0 },
16847 		{ "RVF", 0, 8 },
16848 	{ "PCIE_FID_VFID", 0x5214, 0 },
16855 		{ "RVF", 0, 8 },
16856 	{ "PCIE_FID_VFID", 0x5218, 0 },
16863 		{ "RVF", 0, 8 },
16864 	{ "PCIE_FID_VFID", 0x521c, 0 },
16871 		{ "RVF", 0, 8 },
16872 	{ "PCIE_FID_VFID", 0x5220, 0 },
16879 		{ "RVF", 0, 8 },
16880 	{ "PCIE_FID_VFID", 0x5224, 0 },
16887 		{ "RVF", 0, 8 },
16888 	{ "PCIE_FID_VFID", 0x5228, 0 },
16895 		{ "RVF", 0, 8 },
16896 	{ "PCIE_FID_VFID", 0x522c, 0 },
16903 		{ "RVF", 0, 8 },
16904 	{ "PCIE_FID_VFID", 0x5230, 0 },
16911 		{ "RVF", 0, 8 },
16912 	{ "PCIE_FID_VFID", 0x5234, 0 },
16919 		{ "RVF", 0, 8 },
16920 	{ "PCIE_FID_VFID", 0x5238, 0 },
16927 		{ "RVF", 0, 8 },
16928 	{ "PCIE_FID_VFID", 0x523c, 0 },
16935 		{ "RVF", 0, 8 },
16936 	{ "PCIE_FID_VFID", 0x5240, 0 },
16943 		{ "RVF", 0, 8 },
16944 	{ "PCIE_FID_VFID", 0x5244, 0 },
16951 		{ "RVF", 0, 8 },
16952 	{ "PCIE_FID_VFID", 0x5248, 0 },
16959 		{ "RVF", 0, 8 },
16960 	{ "PCIE_FID_VFID", 0x524c, 0 },
16967 		{ "RVF", 0, 8 },
16968 	{ "PCIE_FID_VFID", 0x5250, 0 },
16975 		{ "RVF", 0, 8 },
16976 	{ "PCIE_FID_VFID", 0x5254, 0 },
16983 		{ "RVF", 0, 8 },
16984 	{ "PCIE_FID_VFID", 0x5258, 0 },
16991 		{ "RVF", 0, 8 },
16992 	{ "PCIE_FID_VFID", 0x525c, 0 },
16999 		{ "RVF", 0, 8 },
17000 	{ "PCIE_FID_VFID", 0x5260, 0 },
17007 		{ "RVF", 0, 8 },
17008 	{ "PCIE_FID_VFID", 0x5264, 0 },
17015 		{ "RVF", 0, 8 },
17016 	{ "PCIE_FID_VFID", 0x5268, 0 },
17023 		{ "RVF", 0, 8 },
17024 	{ "PCIE_FID_VFID", 0x526c, 0 },
17031 		{ "RVF", 0, 8 },
17032 	{ "PCIE_FID_VFID", 0x5270, 0 },
17039 		{ "RVF", 0, 8 },
17040 	{ "PCIE_FID_VFID", 0x5274, 0 },
17047 		{ "RVF", 0, 8 },
17048 	{ "PCIE_FID_VFID", 0x5278, 0 },
17055 		{ "RVF", 0, 8 },
17056 	{ "PCIE_FID_VFID", 0x527c, 0 },
17063 		{ "RVF", 0, 8 },
17064 	{ "PCIE_FID_VFID", 0x5280, 0 },
17071 		{ "RVF", 0, 8 },
17072 	{ "PCIE_FID_VFID", 0x5284, 0 },
17079 		{ "RVF", 0, 8 },
17080 	{ "PCIE_FID_VFID", 0x5288, 0 },
17087 		{ "RVF", 0, 8 },
17088 	{ "PCIE_FID_VFID", 0x528c, 0 },
17095 		{ "RVF", 0, 8 },
17096 	{ "PCIE_FID_VFID", 0x5290, 0 },
17103 		{ "RVF", 0, 8 },
17104 	{ "PCIE_FID_VFID", 0x5294, 0 },
17111 		{ "RVF", 0, 8 },
17112 	{ "PCIE_FID_VFID", 0x5298, 0 },
17119 		{ "RVF", 0, 8 },
17120 	{ "PCIE_FID_VFID", 0x529c, 0 },
17127 		{ "RVF", 0, 8 },
17128 	{ "PCIE_FID_VFID", 0x52a0, 0 },
17135 		{ "RVF", 0, 8 },
17136 	{ "PCIE_FID_VFID", 0x52a4, 0 },
17143 		{ "RVF", 0, 8 },
17144 	{ "PCIE_FID_VFID", 0x52a8, 0 },
17151 		{ "RVF", 0, 8 },
17152 	{ "PCIE_FID_VFID", 0x52ac, 0 },
17159 		{ "RVF", 0, 8 },
17160 	{ "PCIE_FID_VFID", 0x52b0, 0 },
17167 		{ "RVF", 0, 8 },
17168 	{ "PCIE_FID_VFID", 0x52b4, 0 },
17175 		{ "RVF", 0, 8 },
17176 	{ "PCIE_FID_VFID", 0x52b8, 0 },
17183 		{ "RVF", 0, 8 },
17184 	{ "PCIE_FID_VFID", 0x52bc, 0 },
17191 		{ "RVF", 0, 8 },
17192 	{ "PCIE_FID_VFID", 0x52c0, 0 },
17199 		{ "RVF", 0, 8 },
17200 	{ "PCIE_FID_VFID", 0x52c4, 0 },
17207 		{ "RVF", 0, 8 },
17208 	{ "PCIE_FID_VFID", 0x52c8, 0 },
17215 		{ "RVF", 0, 8 },
17216 	{ "PCIE_FID_VFID", 0x52cc, 0 },
17223 		{ "RVF", 0, 8 },
17224 	{ "PCIE_FID_VFID", 0x52d0, 0 },
17231 		{ "RVF", 0, 8 },
17232 	{ "PCIE_FID_VFID", 0x52d4, 0 },
17239 		{ "RVF", 0, 8 },
17240 	{ "PCIE_FID_VFID", 0x52d8, 0 },
17247 		{ "RVF", 0, 8 },
17248 	{ "PCIE_FID_VFID", 0x52dc, 0 },
17255 		{ "RVF", 0, 8 },
17256 	{ "PCIE_FID_VFID", 0x52e0, 0 },
17263 		{ "RVF", 0, 8 },
17264 	{ "PCIE_FID_VFID", 0x52e4, 0 },
17271 		{ "RVF", 0, 8 },
17272 	{ "PCIE_FID_VFID", 0x52e8, 0 },
17279 		{ "RVF", 0, 8 },
17280 	{ "PCIE_FID_VFID", 0x52ec, 0 },
17287 		{ "RVF", 0, 8 },
17288 	{ "PCIE_FID_VFID", 0x52f0, 0 },
17295 		{ "RVF", 0, 8 },
17296 	{ "PCIE_FID_VFID", 0x52f4, 0 },
17303 		{ "RVF", 0, 8 },
17304 	{ "PCIE_FID_VFID", 0x52f8, 0 },
17311 		{ "RVF", 0, 8 },
17312 	{ "PCIE_FID_VFID", 0x52fc, 0 },
17319 		{ "RVF", 0, 8 },
17320 	{ "PCIE_FID_VFID", 0x5300, 0 },
17327 		{ "RVF", 0, 8 },
17328 	{ "PCIE_FID_VFID", 0x5304, 0 },
17335 		{ "RVF", 0, 8 },
17336 	{ "PCIE_FID_VFID", 0x5308, 0 },
17343 		{ "RVF", 0, 8 },
17344 	{ "PCIE_FID_VFID", 0x530c, 0 },
17351 		{ "RVF", 0, 8 },
17352 	{ "PCIE_FID_VFID", 0x5310, 0 },
17359 		{ "RVF", 0, 8 },
17360 	{ "PCIE_FID_VFID", 0x5314, 0 },
17367 		{ "RVF", 0, 8 },
17368 	{ "PCIE_FID_VFID", 0x5318, 0 },
17375 		{ "RVF", 0, 8 },
17376 	{ "PCIE_FID_VFID", 0x531c, 0 },
17383 		{ "RVF", 0, 8 },
17384 	{ "PCIE_FID_VFID", 0x5320, 0 },
17391 		{ "RVF", 0, 8 },
17392 	{ "PCIE_FID_VFID", 0x5324, 0 },
17399 		{ "RVF", 0, 8 },
17400 	{ "PCIE_FID_VFID", 0x5328, 0 },
17407 		{ "RVF", 0, 8 },
17408 	{ "PCIE_FID_VFID", 0x532c, 0 },
17415 		{ "RVF", 0, 8 },
17416 	{ "PCIE_FID_VFID", 0x5330, 0 },
17423 		{ "RVF", 0, 8 },
17424 	{ "PCIE_FID_VFID", 0x5334, 0 },
17431 		{ "RVF", 0, 8 },
17432 	{ "PCIE_FID_VFID", 0x5338, 0 },
17439 		{ "RVF", 0, 8 },
17440 	{ "PCIE_FID_VFID", 0x533c, 0 },
17447 		{ "RVF", 0, 8 },
17448 	{ "PCIE_FID_VFID", 0x5340, 0 },
17455 		{ "RVF", 0, 8 },
17456 	{ "PCIE_FID_VFID", 0x5344, 0 },
17463 		{ "RVF", 0, 8 },
17464 	{ "PCIE_FID_VFID", 0x5348, 0 },
17471 		{ "RVF", 0, 8 },
17472 	{ "PCIE_FID_VFID", 0x534c, 0 },
17479 		{ "RVF", 0, 8 },
17480 	{ "PCIE_FID_VFID", 0x5350, 0 },
17487 		{ "RVF", 0, 8 },
17488 	{ "PCIE_FID_VFID", 0x5354, 0 },
17495 		{ "RVF", 0, 8 },
17496 	{ "PCIE_FID_VFID", 0x5358, 0 },
17503 		{ "RVF", 0, 8 },
17504 	{ "PCIE_FID_VFID", 0x535c, 0 },
17511 		{ "RVF", 0, 8 },
17512 	{ "PCIE_FID_VFID", 0x5360, 0 },
17519 		{ "RVF", 0, 8 },
17520 	{ "PCIE_FID_VFID", 0x5364, 0 },
17527 		{ "RVF", 0, 8 },
17528 	{ "PCIE_FID_VFID", 0x5368, 0 },
17535 		{ "RVF", 0, 8 },
17536 	{ "PCIE_FID_VFID", 0x536c, 0 },
17543 		{ "RVF", 0, 8 },
17544 	{ "PCIE_FID_VFID", 0x5370, 0 },
17551 		{ "RVF", 0, 8 },
17552 	{ "PCIE_FID_VFID", 0x5374, 0 },
17559 		{ "RVF", 0, 8 },
17560 	{ "PCIE_FID_VFID", 0x5378, 0 },
17567 		{ "RVF", 0, 8 },
17568 	{ "PCIE_FID_VFID", 0x537c, 0 },
17575 		{ "RVF", 0, 8 },
17576 	{ "PCIE_FID_VFID", 0x5380, 0 },
17583 		{ "RVF", 0, 8 },
17584 	{ "PCIE_FID_VFID", 0x5384, 0 },
17591 		{ "RVF", 0, 8 },
17592 	{ "PCIE_FID_VFID", 0x5388, 0 },
17599 		{ "RVF", 0, 8 },
17600 	{ "PCIE_FID_VFID", 0x538c, 0 },
17607 		{ "RVF", 0, 8 },
17608 	{ "PCIE_FID_VFID", 0x5390, 0 },
17615 		{ "RVF", 0, 8 },
17616 	{ "PCIE_FID_VFID", 0x5394, 0 },
17623 		{ "RVF", 0, 8 },
17624 	{ "PCIE_FID_VFID", 0x5398, 0 },
17631 		{ "RVF", 0, 8 },
17632 	{ "PCIE_FID_VFID", 0x539c, 0 },
17639 		{ "RVF", 0, 8 },
17640 	{ "PCIE_FID_VFID", 0x53a0, 0 },
17647 		{ "RVF", 0, 8 },
17648 	{ "PCIE_FID_VFID", 0x53a4, 0 },
17655 		{ "RVF", 0, 8 },
17656 	{ "PCIE_FID_VFID", 0x53a8, 0 },
17663 		{ "RVF", 0, 8 },
17664 	{ "PCIE_FID_VFID", 0x53ac, 0 },
17671 		{ "RVF", 0, 8 },
17672 	{ "PCIE_FID_VFID", 0x53b0, 0 },
17679 		{ "RVF", 0, 8 },
17680 	{ "PCIE_FID_VFID", 0x53b4, 0 },
17687 		{ "RVF", 0, 8 },
17688 	{ "PCIE_FID_VFID", 0x53b8, 0 },
17695 		{ "RVF", 0, 8 },
17696 	{ "PCIE_FID_VFID", 0x53bc, 0 },
17703 		{ "RVF", 0, 8 },
17704 	{ "PCIE_FID_VFID", 0x53c0, 0 },
17711 		{ "RVF", 0, 8 },
17712 	{ "PCIE_FID_VFID", 0x53c4, 0 },
17719 		{ "RVF", 0, 8 },
17720 	{ "PCIE_FID_VFID", 0x53c8, 0 },
17727 		{ "RVF", 0, 8 },
17728 	{ "PCIE_FID_VFID", 0x53cc, 0 },
17735 		{ "RVF", 0, 8 },
17736 	{ "PCIE_FID_VFID", 0x53d0, 0 },
17743 		{ "RVF", 0, 8 },
17744 	{ "PCIE_FID_VFID", 0x53d4, 0 },
17751 		{ "RVF", 0, 8 },
17752 	{ "PCIE_FID_VFID", 0x53d8, 0 },
17759 		{ "RVF", 0, 8 },
17760 	{ "PCIE_FID_VFID", 0x53dc, 0 },
17767 		{ "RVF", 0, 8 },
17768 	{ "PCIE_FID_VFID", 0x53e0, 0 },
17775 		{ "RVF", 0, 8 },
17776 	{ "PCIE_FID_VFID", 0x53e4, 0 },
17783 		{ "RVF", 0, 8 },
17784 	{ "PCIE_FID_VFID", 0x53e8, 0 },
17791 		{ "RVF", 0, 8 },
17792 	{ "PCIE_FID_VFID", 0x53ec, 0 },
17799 		{ "RVF", 0, 8 },
17800 	{ "PCIE_FID_VFID", 0x53f0, 0 },
17807 		{ "RVF", 0, 8 },
17808 	{ "PCIE_FID_VFID", 0x53f4, 0 },
17815 		{ "RVF", 0, 8 },
17816 	{ "PCIE_FID_VFID", 0x53f8, 0 },
17823 		{ "RVF", 0, 8 },
17824 	{ "PCIE_FID_VFID", 0x53fc, 0 },
17831 		{ "RVF", 0, 8 },
17832 	{ "PCIE_FID_VFID", 0x5400, 0 },
17839 		{ "RVF", 0, 8 },
17840 	{ "PCIE_FID_VFID", 0x5404, 0 },
17847 		{ "RVF", 0, 8 },
17848 	{ "PCIE_FID_VFID", 0x5408, 0 },
17855 		{ "RVF", 0, 8 },
17856 	{ "PCIE_FID_VFID", 0x540c, 0 },
17863 		{ "RVF", 0, 8 },
17864 	{ "PCIE_FID_VFID", 0x5410, 0 },
17871 		{ "RVF", 0, 8 },
17872 	{ "PCIE_FID_VFID", 0x5414, 0 },
17879 		{ "RVF", 0, 8 },
17880 	{ "PCIE_FID_VFID", 0x5418, 0 },
17887 		{ "RVF", 0, 8 },
17888 	{ "PCIE_FID_VFID", 0x541c, 0 },
17895 		{ "RVF", 0, 8 },
17896 	{ "PCIE_FID_VFID", 0x5420, 0 },
17903 		{ "RVF", 0, 8 },
17904 	{ "PCIE_FID_VFID", 0x5424, 0 },
17911 		{ "RVF", 0, 8 },
17912 	{ "PCIE_FID_VFID", 0x5428, 0 },
17919 		{ "RVF", 0, 8 },
17920 	{ "PCIE_FID_VFID", 0x542c, 0 },
17927 		{ "RVF", 0, 8 },
17928 	{ "PCIE_FID_VFID", 0x5430, 0 },
17935 		{ "RVF", 0, 8 },
17936 	{ "PCIE_FID_VFID", 0x5434, 0 },
17943 		{ "RVF", 0, 8 },
17944 	{ "PCIE_FID_VFID", 0x5438, 0 },
17951 		{ "RVF", 0, 8 },
17952 	{ "PCIE_FID_VFID", 0x543c, 0 },
17959 		{ "RVF", 0, 8 },
17960 	{ "PCIE_FID_VFID", 0x5440, 0 },
17967 		{ "RVF", 0, 8 },
17968 	{ "PCIE_FID_VFID", 0x5444, 0 },
17975 		{ "RVF", 0, 8 },
17976 	{ "PCIE_FID_VFID", 0x5448, 0 },
17983 		{ "RVF", 0, 8 },
17984 	{ "PCIE_FID_VFID", 0x544c, 0 },
17991 		{ "RVF", 0, 8 },
17992 	{ "PCIE_FID_VFID", 0x5450, 0 },
17999 		{ "RVF", 0, 8 },
18000 	{ "PCIE_FID_VFID", 0x5454, 0 },
18007 		{ "RVF", 0, 8 },
18008 	{ "PCIE_FID_VFID", 0x5458, 0 },
18015 		{ "RVF", 0, 8 },
18016 	{ "PCIE_FID_VFID", 0x545c, 0 },
18023 		{ "RVF", 0, 8 },
18024 	{ "PCIE_FID_VFID", 0x5460, 0 },
18031 		{ "RVF", 0, 8 },
18032 	{ "PCIE_FID_VFID", 0x5464, 0 },
18039 		{ "RVF", 0, 8 },
18040 	{ "PCIE_FID_VFID", 0x5468, 0 },
18047 		{ "RVF", 0, 8 },
18048 	{ "PCIE_FID_VFID", 0x546c, 0 },
18055 		{ "RVF", 0, 8 },
18056 	{ "PCIE_FID_VFID", 0x5470, 0 },
18063 		{ "RVF", 0, 8 },
18064 	{ "PCIE_FID_VFID", 0x5474, 0 },
18071 		{ "RVF", 0, 8 },
18072 	{ "PCIE_FID_VFID", 0x5478, 0 },
18079 		{ "RVF", 0, 8 },
18080 	{ "PCIE_FID_VFID", 0x547c, 0 },
18087 		{ "RVF", 0, 8 },
18088 	{ "PCIE_FID_VFID", 0x5480, 0 },
18095 		{ "RVF", 0, 8 },
18096 	{ "PCIE_FID_VFID", 0x5484, 0 },
18103 		{ "RVF", 0, 8 },
18104 	{ "PCIE_FID_VFID", 0x5488, 0 },
18111 		{ "RVF", 0, 8 },
18112 	{ "PCIE_FID_VFID", 0x548c, 0 },
18119 		{ "RVF", 0, 8 },
18120 	{ "PCIE_FID_VFID", 0x5490, 0 },
18127 		{ "RVF", 0, 8 },
18128 	{ "PCIE_FID_VFID", 0x5494, 0 },
18135 		{ "RVF", 0, 8 },
18136 	{ "PCIE_FID_VFID", 0x5498, 0 },
18143 		{ "RVF", 0, 8 },
18144 	{ "PCIE_FID_VFID", 0x549c, 0 },
18151 		{ "RVF", 0, 8 },
18152 	{ "PCIE_FID_VFID", 0x54a0, 0 },
18159 		{ "RVF", 0, 8 },
18160 	{ "PCIE_FID_VFID", 0x54a4, 0 },
18167 		{ "RVF", 0, 8 },
18168 	{ "PCIE_FID_VFID", 0x54a8, 0 },
18175 		{ "RVF", 0, 8 },
18176 	{ "PCIE_FID_VFID", 0x54ac, 0 },
18183 		{ "RVF", 0, 8 },
18184 	{ "PCIE_FID_VFID", 0x54b0, 0 },
18191 		{ "RVF", 0, 8 },
18192 	{ "PCIE_FID_VFID", 0x54b4, 0 },
18199 		{ "RVF", 0, 8 },
18200 	{ "PCIE_FID_VFID", 0x54b8, 0 },
18207 		{ "RVF", 0, 8 },
18208 	{ "PCIE_FID_VFID", 0x54bc, 0 },
18215 		{ "RVF", 0, 8 },
18216 	{ "PCIE_FID_VFID", 0x54c0, 0 },
18223 		{ "RVF", 0, 8 },
18224 	{ "PCIE_FID_VFID", 0x54c4, 0 },
18231 		{ "RVF", 0, 8 },
18232 	{ "PCIE_FID_VFID", 0x54c8, 0 },
18239 		{ "RVF", 0, 8 },
18240 	{ "PCIE_FID_VFID", 0x54cc, 0 },
18247 		{ "RVF", 0, 8 },
18248 	{ "PCIE_FID_VFID", 0x54d0, 0 },
18255 		{ "RVF", 0, 8 },
18256 	{ "PCIE_FID_VFID", 0x54d4, 0 },
18263 		{ "RVF", 0, 8 },
18264 	{ "PCIE_FID_VFID", 0x54d8, 0 },
18271 		{ "RVF", 0, 8 },
18272 	{ "PCIE_FID_VFID", 0x54dc, 0 },
18279 		{ "RVF", 0, 8 },
18280 	{ "PCIE_FID_VFID", 0x54e0, 0 },
18287 		{ "RVF", 0, 8 },
18288 	{ "PCIE_FID_VFID", 0x54e4, 0 },
18295 		{ "RVF", 0, 8 },
18296 	{ "PCIE_FID_VFID", 0x54e8, 0 },
18303 		{ "RVF", 0, 8 },
18304 	{ "PCIE_FID_VFID", 0x54ec, 0 },
18311 		{ "RVF", 0, 8 },
18312 	{ "PCIE_FID_VFID", 0x54f0, 0 },
18319 		{ "RVF", 0, 8 },
18320 	{ "PCIE_FID_VFID", 0x54f4, 0 },
18327 		{ "RVF", 0, 8 },
18328 	{ "PCIE_FID_VFID", 0x54f8, 0 },
18335 		{ "RVF", 0, 8 },
18336 	{ "PCIE_FID_VFID", 0x54fc, 0 },
18343 		{ "RVF", 0, 8 },
18344 	{ "PCIE_FID_VFID", 0x5500, 0 },
18351 		{ "RVF", 0, 8 },
18352 	{ "PCIE_FID_VFID", 0x5504, 0 },
18359 		{ "RVF", 0, 8 },
18360 	{ "PCIE_FID_VFID", 0x5508, 0 },
18367 		{ "RVF", 0, 8 },
18368 	{ "PCIE_FID_VFID", 0x550c, 0 },
18375 		{ "RVF", 0, 8 },
18376 	{ "PCIE_FID_VFID", 0x5510, 0 },
18383 		{ "RVF", 0, 8 },
18384 	{ "PCIE_FID_VFID", 0x5514, 0 },
18391 		{ "RVF", 0, 8 },
18392 	{ "PCIE_FID_VFID", 0x5518, 0 },
18399 		{ "RVF", 0, 8 },
18400 	{ "PCIE_FID_VFID", 0x551c, 0 },
18407 		{ "RVF", 0, 8 },
18408 	{ "PCIE_FID_VFID", 0x5520, 0 },
18415 		{ "RVF", 0, 8 },
18416 	{ "PCIE_FID_VFID", 0x5524, 0 },
18423 		{ "RVF", 0, 8 },
18424 	{ "PCIE_FID_VFID", 0x5528, 0 },
18431 		{ "RVF", 0, 8 },
18432 	{ "PCIE_FID_VFID", 0x552c, 0 },
18439 		{ "RVF", 0, 8 },
18440 	{ "PCIE_FID_VFID", 0x5530, 0 },
18447 		{ "RVF", 0, 8 },
18448 	{ "PCIE_FID_VFID", 0x5534, 0 },
18455 		{ "RVF", 0, 8 },
18456 	{ "PCIE_FID_VFID", 0x5538, 0 },
18463 		{ "RVF", 0, 8 },
18464 	{ "PCIE_FID_VFID", 0x553c, 0 },
18471 		{ "RVF", 0, 8 },
18472 	{ "PCIE_FID_VFID", 0x5540, 0 },
18479 		{ "RVF", 0, 8 },
18480 	{ "PCIE_FID_VFID", 0x5544, 0 },
18487 		{ "RVF", 0, 8 },
18488 	{ "PCIE_FID_VFID", 0x5548, 0 },
18495 		{ "RVF", 0, 8 },
18496 	{ "PCIE_FID_VFID", 0x554c, 0 },
18503 		{ "RVF", 0, 8 },
18504 	{ "PCIE_FID_VFID", 0x5550, 0 },
18511 		{ "RVF", 0, 8 },
18512 	{ "PCIE_FID_VFID", 0x5554, 0 },
18519 		{ "RVF", 0, 8 },
18520 	{ "PCIE_FID_VFID", 0x5558, 0 },
18527 		{ "RVF", 0, 8 },
18528 	{ "PCIE_FID_VFID", 0x555c, 0 },
18535 		{ "RVF", 0, 8 },
18536 	{ "PCIE_FID_VFID", 0x5560, 0 },
18543 		{ "RVF", 0, 8 },
18544 	{ "PCIE_FID_VFID", 0x5564, 0 },
18551 		{ "RVF", 0, 8 },
18552 	{ "PCIE_FID_VFID", 0x5568, 0 },
18559 		{ "RVF", 0, 8 },
18560 	{ "PCIE_FID_VFID", 0x556c, 0 },
18567 		{ "RVF", 0, 8 },
18568 	{ "PCIE_FID_VFID", 0x5570, 0 },
18575 		{ "RVF", 0, 8 },
18576 	{ "PCIE_FID_VFID", 0x5574, 0 },
18583 		{ "RVF", 0, 8 },
18584 	{ "PCIE_FID_VFID", 0x5578, 0 },
18591 		{ "RVF", 0, 8 },
18592 	{ "PCIE_FID_VFID", 0x557c, 0 },
18599 		{ "RVF", 0, 8 },
18600 	{ "PCIE_FID_VFID", 0x5580, 0 },
18607 		{ "RVF", 0, 8 },
18608 	{ "PCIE_FID_VFID", 0x5584, 0 },
18615 		{ "RVF", 0, 8 },
18616 	{ "PCIE_FID_VFID", 0x5588, 0 },
18623 		{ "RVF", 0, 8 },
18624 	{ "PCIE_FID_VFID", 0x558c, 0 },
18631 		{ "RVF", 0, 8 },
18632 	{ "PCIE_FID_VFID", 0x5590, 0 },
18639 		{ "RVF", 0, 8 },
18640 	{ "PCIE_FID_VFID", 0x5594, 0 },
18647 		{ "RVF", 0, 8 },
18648 	{ "PCIE_FID_VFID", 0x5598, 0 },
18655 		{ "RVF", 0, 8 },
18656 	{ "PCIE_FID_VFID", 0x559c, 0 },
18663 		{ "RVF", 0, 8 },
18664 	{ "PCIE_FID_VFID", 0x55a0, 0 },
18671 		{ "RVF", 0, 8 },
18672 	{ "PCIE_FID_VFID", 0x55a4, 0 },
18679 		{ "RVF", 0, 8 },
18680 	{ "PCIE_FID_VFID", 0x55a8, 0 },
18687 		{ "RVF", 0, 8 },
18688 	{ "PCIE_FID_VFID", 0x55ac, 0 },
18695 		{ "RVF", 0, 8 },
18696 	{ "PCIE_FID_VFID", 0x55b0, 0 },
18703 		{ "RVF", 0, 8 },
18704 	{ "PCIE_FID_VFID", 0x55b4, 0 },
18711 		{ "RVF", 0, 8 },
18712 	{ "PCIE_FID_VFID", 0x55b8, 0 },
18719 		{ "RVF", 0, 8 },
18720 	{ "PCIE_FID_VFID", 0x55bc, 0 },
18727 		{ "RVF", 0, 8 },
18728 	{ "PCIE_FID_VFID", 0x55c0, 0 },
18735 		{ "RVF", 0, 8 },
18736 	{ "PCIE_FID_VFID", 0x55c4, 0 },
18743 		{ "RVF", 0, 8 },
18744 	{ "PCIE_FID_VFID", 0x55c8, 0 },
18751 		{ "RVF", 0, 8 },
18752 	{ "PCIE_FID_VFID", 0x55cc, 0 },
18759 		{ "RVF", 0, 8 },
18760 	{ "PCIE_FID_VFID", 0x55d0, 0 },
18767 		{ "RVF", 0, 8 },
18768 	{ "PCIE_FID_VFID", 0x55d4, 0 },
18775 		{ "RVF", 0, 8 },
18776 	{ "PCIE_FID_VFID", 0x55d8, 0 },
18783 		{ "RVF", 0, 8 },
18784 	{ "PCIE_FID_VFID", 0x55dc, 0 },
18791 		{ "RVF", 0, 8 },
18792 	{ "PCIE_FID_VFID", 0x55e0, 0 },
18799 		{ "RVF", 0, 8 },
18800 	{ "PCIE_FID_VFID", 0x55e4, 0 },
18807 		{ "RVF", 0, 8 },
18808 	{ "PCIE_FID_VFID", 0x55e8, 0 },
18815 		{ "RVF", 0, 8 },
18816 	{ "PCIE_FID_VFID", 0x55ec, 0 },
18823 		{ "RVF", 0, 8 },
18824 	{ "PCIE_FID_VFID", 0x55f0, 0 },
18831 		{ "RVF", 0, 8 },
18832 	{ "PCIE_FID_VFID", 0x55f4, 0 },
18839 		{ "RVF", 0, 8 },
18840 	{ "PCIE_FID_VFID", 0x55f8, 0 },
18847 		{ "RVF", 0, 8 },
18848 	{ "PCIE_FID_VFID", 0x55fc, 0 },
18855 		{ "RVF", 0, 8 },
18856 	{ "PCIE_COOKIE_STAT", 0x5600, 0 },
18858 		{ "CookieA", 0, 10 },
18859 	{ "PCIE_COOKIE_STAT", 0x5604, 0 },
18861 		{ "CookieA", 0, 10 },
18862 	{ "PCIE_COOKIE_STAT", 0x5608, 0 },
18864 		{ "CookieA", 0, 10 },
18865 	{ "PCIE_COOKIE_STAT", 0x560c, 0 },
18867 		{ "CookieA", 0, 10 },
18868 	{ "PCIE_COOKIE_STAT", 0x5610, 0 },
18870 		{ "CookieA", 0, 10 },
18871 	{ "PCIE_COOKIE_STAT", 0x5614, 0 },
18873 		{ "CookieA", 0, 10 },
18874 	{ "PCIE_COOKIE_STAT", 0x5618, 0 },
18876 		{ "CookieA", 0, 10 },
18877 	{ "PCIE_COOKIE_STAT", 0x561c, 0 },
18879 		{ "CookieA", 0, 10 },
18880 	{ "PCIE_FLR_PIO", 0x5620, 0 },
18884 		{ "ExpdCookie", 0, 8 },
18885 	{ "PCIE_FLR_PIO2", 0x5624, 0 },
18889 		{ "RcvdPIOReqCookie", 0, 8 },
18890 	{ "PCIE_VC0_CDTS0", 0x56cc, 0 },
18893 		{ "PD0", 0, 12 },
18894 	{ "PCIE_VC0_CDTS1", 0x56d0, 0 },
18897 		{ "NPD0", 0, 12 },
18898 	{ "PCIE_VC1_CDTS0", 0x56d4, 0 },
18901 		{ "PD1", 0, 12 },
18902 	{ "PCIE_VC1_CDTS1", 0x56d8, 0 },
18905 		{ "NPD1", 0, 12 },
18906 	{ "PCIE_FLR_PF_STATUS", 0x56dc, 0 },
18907 	{ "PCIE_FLR_VF0_STATUS", 0x56e0, 0 },
18908 	{ "PCIE_FLR_VF1_STATUS", 0x56e4, 0 },
18909 	{ "PCIE_FLR_VF2_STATUS", 0x56e8, 0 },
18910 	{ "PCIE_FLR_VF3_STATUS", 0x56ec, 0 },
18911 	{ "PCIE_STAT", 0x56f4, 0 },
18916 		{ "StateCfgInit", 0, 4 },
18917 	{ "PCIE_CRS", 0x56f8, 0 },
18918 	{ "PCIE_LTSSM", 0x56fc, 0 },
18920 		{ "Enable", 0, 1 },
18921 	{ "PCIE_PF_CFG", 0x1e040, 0 },
18925 		{ "CLIDecEn", 0, 1 },
18926 	{ "PCIE_PF_CLI", 0x1e044, 0 },
18927 	{ "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 },
18929 	{ "PCIE_PF_CFG", 0x1e440, 0 },
18933 		{ "CLIDecEn", 0, 1 },
18934 	{ "PCIE_PF_CLI", 0x1e444, 0 },
18935 	{ "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 },
18937 	{ "PCIE_PF_CFG", 0x1e840, 0 },
18941 		{ "CLIDecEn", 0, 1 },
18942 	{ "PCIE_PF_CLI", 0x1e844, 0 },
18943 	{ "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 },
18945 	{ "PCIE_PF_CFG", 0x1ec40, 0 },
18949 		{ "CLIDecEn", 0, 1 },
18950 	{ "PCIE_PF_CLI", 0x1ec44, 0 },
18951 	{ "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 },
18953 	{ "PCIE_PF_CFG", 0x1f040, 0 },
18957 		{ "CLIDecEn", 0, 1 },
18958 	{ "PCIE_PF_CLI", 0x1f044, 0 },
18959 	{ "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 },
18961 	{ "PCIE_PF_CFG", 0x1f440, 0 },
18965 		{ "CLIDecEn", 0, 1 },
18966 	{ "PCIE_PF_CLI", 0x1f444, 0 },
18967 	{ "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 },
18969 	{ "PCIE_PF_CFG", 0x1f840, 0 },
18973 		{ "CLIDecEn", 0, 1 },
18974 	{ "PCIE_PF_CLI", 0x1f844, 0 },
18975 	{ "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 },
18977 	{ "PCIE_PF_CFG", 0x1fc40, 0 },
18981 		{ "CLIDecEn", 0, 1 },
18982 	{ "PCIE_PF_CLI", 0x1fc44, 0 },
18983 	{ "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
18985 	{ "PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x5700, 0 },
18987 		{ "Ack_Latency_Timer_Limit", 0, 16 },
18988 	{ "PCIE_CORE_VENDOR_SPECIFIC_DLLP", 0x5704, 0 },
18989 	{ "PCIE_CORE_PORT_FORCE_LINK", 0x5708, 0 },
18993 		{ "Link_Number", 0, 8 },
18994 	{ "PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x570c, 0 },
19000 		{ "Ack_Frequency", 0, 8 },
19001 	{ "PCIE_CORE_PORT_LINK_CONTROL", 0x5710, 0 },
19010 		{ "Vendor_Specific_DLLP_Request", 0, 1 },
19011 	{ "PCIE_CORE_LANE_SKEW", 0x5714, 0 },
19015 		{ "Insert_TxSkew", 0, 24 },
19016 	{ "PCIE_CORE_SYMBOL_NUMBER", 0x5718, 0 },
19019 		{ "MaxFunc", 0, 3 },
19020 	{ "PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x571c, 0 },
19023 		{ "SKP_Interval", 0, 11 },
19024 	{ "PCIE_CORE_FILTER_MASK2", 0x5720, 0 },
19025 	{ "PCIE_CORE_DEBUG_0", 0x5728, 0 },
19026 	{ "PCIE_CORE_DEBUG_1", 0x572c, 0 },
19027 	{ "PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x5730, 0 },
19029 		{ "TxPD_FC", 0, 12 },
19030 	{ "PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x5734, 0 },
19032 		{ "TxNPD_FC", 0, 12 },
19033 	{ "PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x5738, 0 },
19035 		{ "TxCPLD_FC", 0, 12 },
19036 	{ "PCIE_CORE_QUEUE_STATUS", 0x573c, 0 },
19039 		{ "RxTLP_FC_Not_Returned", 0, 1 },
19040 	{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_1", 0x5740, 0 },
19044 		{ "VC0_WRR", 0, 8 },
19045 	{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_2", 0x5744, 0 },
19049 		{ "VC4_WRR", 0, 8 },
19050 	{ "PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x5748, 0 },
19055 		{ "VC0_PD_Credits", 0, 12 },
19056 	{ "PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x574c, 0 },
19059 		{ "VC0_NPD_Credits", 0, 12 },
19060 	{ "PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x5750, 0 },
19063 		{ "VC0_CPLD_Credits", 0, 12 },
19064 	{ "PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x5754, 0 },
19068 		{ "VC1_PD_Credits", 0, 12 },
19069 	{ "PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x5758, 0 },
19072 		{ "VC1_NPD_Credits", 0, 12 },
19073 	{ "PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x575c, 0 },
19076 		{ "VC1_CPLD_Credits", 0, 12 },
19077 	{ "PCIE_CORE_LINK_WIDTH_SPEED_CHANGE", 0x580c, 0 },
19084 		{ "NFTS_Gen2_3", 0, 8 },
19085 	{ "PCIE_CORE_PHY_STATUS", 0x5810, 0 },
19086 	{ "PCIE_CORE_PHY_CONTROL", 0x5814, 0 },
19087 	{ "PCIE_CORE_GEN3_CONTROL", 0x5890, 0 },
19095 	{ "PCIE_CORE_GEN3_EQ_FS_LF", 0x5894, 0 },
19097 		{ "Low_Frequency", 0, 6 },
19098 	{ "PCIE_CORE_GEN3_EQ_PRESET_COEFF", 0x5898, 0 },
19101 		{ "PreCursor", 0, 6 },
19102 	{ "PCIE_CORE_GEN3_EQ_PRESET_INDEX", 0x589c, 0 },
19103 	{ "PCIE_CORE_GEN3_EQ_STATUS", 0x58a4, 0 },
19104 	{ "PCIE_CORE_GEN3_EQ_CONTROL", 0x58a8, 0 },
19109 		{ "Feedback_Mode", 0, 4 },
19110 	{ "PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x58ac, 0 },
19114 		{ "EQMasterPhase_MinTime", 0, 5 },
19115 	{ "PCIE_CORE_PIPE_CONTROL", 0x58b8, 0 },
19117 	{ "PCIE_CORE_DBI_RO_WE", 0x58bc, 0 },
19118 	{ "PCIE_DMA_CFG", 0x5940, 0 },
19124 		{ "MinTag", 0, 8 },
19125 	{ "PCIE_DMA_STAT", 0x5944, 0 },
19128 		{ "WrReqCnt", 0, 9 },
19129 	{ "PCIE_DMA_STAT2", 0x5948, 0 },
19135 		{ "RdSOPCnt", 0, 8 },
19136 	{ "PCIE_DMA_STAT3", 0x594c, 0 },
19141 		{ "RspSOPCnt", 0, 8 },
19142 	{ "PCIE_DMA_CFG", 0x5950, 0 },
19148 		{ "MinTag", 0, 8 },
19149 	{ "PCIE_DMA_STAT", 0x5954, 0 },
19152 		{ "WrReqCnt", 0, 9 },
19153 	{ "PCIE_DMA_STAT2", 0x5958, 0 },
19159 		{ "RdSOPCnt", 0, 8 },
19160 	{ "PCIE_DMA_STAT3", 0x595c, 0 },
19165 		{ "RspSOPCnt", 0, 8 },
19166 	{ "PCIE_CMD_CFG", 0x5980, 0 },
19170 		{ "MinTag", 0, 8 },
19171 	{ "PCIE_CMD_STAT", 0x5984, 0 },
19174 	{ "PCIE_CMD_STAT2", 0x5988, 0 },
19175 	{ "PCIE_CMD_STAT3", 0x598c, 0 },
19178 		{ "RspSOPCnt", 0, 8 },
19179 	{ "PCIE_HMA_CFG", 0x59b0, 0 },
19185 		{ "MinTag", 0, 8 },
19186 	{ "PCIE_HMA_STAT", 0x59b4, 0 },
19189 		{ "WrReqCnt", 0, 9 },
19190 	{ "PCIE_HMA_STAT2", 0x59b8, 0 },
19195 		{ "RdSOPCnt", 0, 8 },
19196 	{ "PCIE_HMA_STAT3", 0x59bc, 0 },
19199 		{ "RspSOPCnt", 0, 8 },
19200 	{ "PCIE_CGEN", 0x59c0, 0 },
19219 		{ "STI_SleepReq", 0, 1 },
19220 	{ "PCIE_MA_RSP", 0x59c4, 0 },
19223 		{ "TimerEn", 0, 1 },
19224 	{ "PCIE_HPRD", 0x59c8, 0 },
19233 		{ "EnableVC1", 0, 1 },
19234 	{ "PCIE_PERR_GROUP", 0x59d0, 0 },
19258 		{ "PIOCpl_PLMRspPerr", 0, 1 },
19259 	{ "PCIE_RSP_ERR_INT_LOG_EN", 0x59d4, 0 },
19269 		{ "ReqUnderFLRLogEn", 0, 1 },
19270 	{ "PCIE_RSP_ERR_LOG1", 0x59d8, 0 },
19276 		{ "CplStatus", 0, 3 },
19277 	{ "PCIE_RSP_ERR_LOG2", 0x59dc, 0 },
19280 		{ "VFID", 0, 9 },
19281 	{ "PCIE_REVISION", 0x5a00, 0 },
19282 	{ "PCIE_PDEBUG_INDEX", 0x5a04, 0 },
19284 		{ "PDEBUGSelL", 0, 7 },
19285 	{ "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 },
19286 	{ "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 },
19287 	{ "PCIE_CDEBUG_INDEX", 0x5a10, 0 },
19289 		{ "CDEBUGSelL", 0, 8 },
19290 	{ "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 },
19291 	{ "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 },
19292 	{ "PCIE_BUS_MST_STAT_0", 0x5a60, 0 },
19293 	{ "PCIE_BUS_MST_STAT_1", 0x5a64, 0 },
19294 	{ "PCIE_BUS_MST_STAT_2", 0x5a68, 0 },
19295 	{ "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 },
19296 	{ "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 },
19297 	{ "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 },
19298 	{ "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 },
19299 	{ "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 },
19300 	{ "PCIE_DBI_TIMEOUT_CTL", 0x5a94, 0 },
19301 	{ "PCIE_DBI_TIMEOUT_STATUS0", 0x5a98, 0 },
19302 	{ "PCIE_DBI_TIMEOUT_STATUS1", 0x5a9c, 0 },
19309 		{ "VF", 0, 8 },
19310 	{ "PCIE_PB_CTL", 0x5b94, 0 },
19313 		{ "PB_Func", 0, 3 },
19314 	{ "PCIE_PB_DATA", 0x5b98, 0 },
19315 	{ "PCIE_CHANGESET", 0x59fc, 0 },
19316 	{ "PCIE_CUR_LINK", 0x5b9c, 0 },
19327 		{ "ActiveLanes", 0, 8 },
19328 	{ "PCIE_PHY_REQRXPWR", 0x5ba0, 0 },
19352 		{ "Req_LnA_RxPwrState", 0, 2 },
19353 	{ "PCIE_PHY_CURRXPWR", 0x5ba4, 0 },
19361 		{ "Cur_LnA_RxPwrState", 0, 3 },
19362 	{ "PCIE_PHY_GEN3_AE0", 0x5ba8, 0 },
19370 		{ "LnA_CMD", 0, 3 },
19371 	{ "PCIE_PHY_GEN3_AE1", 0x5bac, 0 },
19379 		{ "LnE_CMD", 0, 3 },
19380 	{ "PCIE_PHY_FS_LF0", 0x5bb0, 0 },
19384 		{ "Lane0FS", 0, 6 },
19385 	{ "PCIE_PHY_FS_LF1", 0x5bb4, 0 },
19389 		{ "Lane2FS", 0, 6 },
19390 	{ "PCIE_PHY_FS_LF2", 0x5bb8, 0 },
19394 		{ "Lane4FS", 0, 6 },
19395 	{ "PCIE_PHY_FS_LF3", 0x5bbc, 0 },
19399 		{ "Lane6FS", 0, 6 },
19400 	{ "PCIE_PHY_PRESET_REQ", 0x5bc0, 0 },
19403 		{ "CoeffStart", 0, 1 },
19404 	{ "PCIE_PHY_PRESET_COEFF", 0x5bc4, 0 },
19405 	{ "PCIE_PHY_PRESET_COEFF", 0x5bc8, 0 },
19406 	{ "PCIE_PHY_PRESET_COEFF", 0x5bcc, 0 },
19407 	{ "PCIE_PHY_PRESET_COEFF", 0x5bd0, 0 },
19408 	{ "PCIE_PHY_PRESET_COEFF", 0x5bd4, 0 },
19409 	{ "PCIE_PHY_PRESET_COEFF", 0x5bd8, 0 },
19410 	{ "PCIE_PHY_PRESET_COEFF", 0x5bdc, 0 },
19411 	{ "PCIE_PHY_PRESET_COEFF", 0x5be0, 0 },
19412 	{ "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 },
19413 	{ "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 },
19414 	{ "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 },
19415 	{ "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 },
19417 		{ "RegAddr", 0, 16 },
19418 	{ "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 },
19419 	{ "PCIE_STATIC_SPARE1", 0x5bf8, 0 },
19420 	{ "PCIE_STATIC_SPARE2", 0x5bfc, 0 },
19421 	{ "PCIE_KDOORBELL_GTS_PF_BASE_LEN", 0x5c10, 0 },
19423 		{ "KDB_PF_BaseAddr", 0, 20 },
19424 	{ "PCIE_KDOORBELL_GTS_VF_BASE_LEN", 0x5c14, 0 },
19426 		{ "KDB_VF_BaseAddr", 0, 20 },
19427 	{ "PCIE_KDOORBELL_GTS_VF_OFFSET", 0x5c18, 0 },
19428 	{ "PCIE_PHY_REQRXPWR1", 0x5c1c, 0 },
19452 		{ "Req_LnI_RxPwrState", 0, 2 },
19453 	{ "PCIE_PHY_CURRXPWR1", 0x5c20, 0 },
19461 		{ "Cur_LnI_RxPwrState", 0, 3 },
19462 	{ "PCIE_PHY_GEN3_AE2", 0x5c24, 0 },
19470 		{ "LnI_CMD", 0, 3 },
19471 	{ "PCIE_PHY_GEN3_AE3", 0x5c28, 0 },
19479 		{ "LnM_CMD", 0, 3 },
19480 	{ "PCIE_PHY_FS_LF4", 0x5c2c, 0 },
19484 		{ "Lane8FS", 0, 6 },
19485 	{ "PCIE_PHY_FS_LF5", 0x5c30, 0 },
19489 		{ "Lane10FS", 0, 6 },
19490 	{ "PCIE_PHY_FS_LF6", 0x5c34, 0 },
19494 		{ "Lane12FS", 0, 6 },
19495 	{ "PCIE_PHY_FS_LF7", 0x5c38, 0 },
19499 		{ "Lane14FS", 0, 6 },
19500 	{ "PCIE_MULTI_PHY_INDIR_REQ", 0x5c3c, 0 },
19503 		{ "Phy_Reg_RegAddr", 0, 16 },
19504 	{ "PCIE_MULTI_PHY_INDIR_DATA", 0x5c40, 0 },
19505 	{ "PCIE_VF_INT_INDIR_REQ", 0x5c44, 0 },
19508 		{ "VFID", 0, 10 },
19509 	{ "PCIE_VF_INT_INDIR_DATA", 0x5c48, 0 },
19511 		{ "VecBase", 0, 11 },
19512 	{ "PCIE_VF_256_INT_CFG2", 0x5c4c, 0 },
19516 	{ "PCIE_VF_256_INT_CFG2", 0x5c50, 0 },
19520 	{ "PCIE_VF_256_INT_CFG2", 0x5c54, 0 },
19524 	{ "PCIE_VF_256_INT_CFG2", 0x5c58, 0 },
19528 	{ "PCIE_VF_256_INT_CFG2", 0x5c5c, 0 },
19532 	{ "PCIE_VF_256_INT_CFG2", 0x5c60, 0 },
19536 	{ "PCIE_VF_256_INT_CFG2", 0x5c64, 0 },
19540 	{ "PCIE_VF_256_INT_CFG2", 0x5c68, 0 },
19544 	{ "PCIE_VF_256_INT_CFG2", 0x5c6c, 0 },
19548 	{ "PCIE_VF_256_INT_CFG2", 0x5c70, 0 },
19552 	{ "PCIE_VF_256_INT_CFG2", 0x5c74, 0 },
19556 	{ "PCIE_VF_256_INT_CFG2", 0x5c78, 0 },
19560 	{ "PCIE_VF_256_INT_CFG2", 0x5c7c, 0 },
19564 	{ "PCIE_VF_256_INT_CFG2", 0x5c80, 0 },
19568 	{ "PCIE_VF_256_INT_CFG2", 0x5c84, 0 },
19572 	{ "PCIE_VF_256_INT_CFG2", 0x5c88, 0 },
19576 	{ "PCIE_VF_256_INT_CFG2", 0x5c8c, 0 },
19580 	{ "PCIE_VF_256_INT_CFG2", 0x5c90, 0 },
19584 	{ "PCIE_VF_256_INT_CFG2", 0x5c94, 0 },
19588 	{ "PCIE_VF_256_INT_CFG2", 0x5c98, 0 },
19592 	{ "PCIE_VF_256_INT_CFG2", 0x5c9c, 0 },
19596 	{ "PCIE_VF_256_INT_CFG2", 0x5ca0, 0 },
19600 	{ "PCIE_VF_256_INT_CFG2", 0x5ca4, 0 },
19604 	{ "PCIE_VF_256_INT_CFG2", 0x5ca8, 0 },
19608 	{ "PCIE_VF_256_INT_CFG2", 0x5cac, 0 },
19612 	{ "PCIE_VF_256_INT_CFG2", 0x5cb0, 0 },
19616 	{ "PCIE_VF_256_INT_CFG2", 0x5cb4, 0 },
19620 	{ "PCIE_VF_256_INT_CFG2", 0x5cb8, 0 },
19624 	{ "PCIE_VF_256_INT_CFG2", 0x5cbc, 0 },
19628 	{ "PCIE_VF_256_INT_CFG2", 0x5cc0, 0 },
19632 	{ "PCIE_VF_256_INT_CFG2", 0x5cc4, 0 },
19636 	{ "PCIE_VF_256_INT_CFG2", 0x5cc8, 0 },
19640 	{ "PCIE_VF_256_INT_CFG2", 0x5ccc, 0 },
19644 	{ "PCIE_VF_256_INT_CFG2", 0x5cd0, 0 },
19648 	{ "PCIE_VF_256_INT_CFG2", 0x5cd4, 0 },
19652 	{ "PCIE_VF_256_INT_CFG2", 0x5cd8, 0 },
19656 	{ "PCIE_VF_256_INT_CFG2", 0x5cdc, 0 },
19660 	{ "PCIE_VF_256_INT_CFG2", 0x5ce0, 0 },
19664 	{ "PCIE_VF_256_INT_CFG2", 0x5ce4, 0 },
19668 	{ "PCIE_VF_256_INT_CFG2", 0x5ce8, 0 },
19672 	{ "PCIE_VF_256_INT_CFG2", 0x5cec, 0 },
19676 	{ "PCIE_VF_256_INT_CFG2", 0x5cf0, 0 },
19680 	{ "PCIE_VF_256_INT_CFG2", 0x5cf4, 0 },
19684 	{ "PCIE_VF_256_INT_CFG2", 0x5cf8, 0 },
19688 	{ "PCIE_VF_256_INT_CFG2", 0x5cfc, 0 },
19692 	{ "PCIE_VF_256_INT_CFG2", 0x5d00, 0 },
19696 	{ "PCIE_VF_256_INT_CFG2", 0x5d04, 0 },
19700 	{ "PCIE_VF_256_INT_CFG2", 0x5d08, 0 },
19704 	{ "PCIE_VF_256_INT_CFG2", 0x5d0c, 0 },
19708 	{ "PCIE_VF_256_INT_CFG2", 0x5d10, 0 },
19712 	{ "PCIE_VF_256_INT_CFG2", 0x5d14, 0 },
19716 	{ "PCIE_VF_256_INT_CFG2", 0x5d18, 0 },
19720 	{ "PCIE_VF_256_INT_CFG2", 0x5d1c, 0 },
19724 	{ "PCIE_VF_256_INT_CFG2", 0x5d20, 0 },
19728 	{ "PCIE_VF_256_INT_CFG2", 0x5d24, 0 },
19732 	{ "PCIE_VF_256_INT_CFG2", 0x5d28, 0 },
19736 	{ "PCIE_VF_256_INT_CFG2", 0x5d2c, 0 },
19740 	{ "PCIE_VF_256_INT_CFG2", 0x5d30, 0 },
19744 	{ "PCIE_VF_256_INT_CFG2", 0x5d34, 0 },
19748 	{ "PCIE_VF_256_INT_CFG2", 0x5d38, 0 },
19752 	{ "PCIE_VF_256_INT_CFG2", 0x5d3c, 0 },
19756 	{ "PCIE_VF_256_INT_CFG2", 0x5d40, 0 },
19760 	{ "PCIE_VF_256_INT_CFG2", 0x5d44, 0 },
19764 	{ "PCIE_VF_256_INT_CFG2", 0x5d48, 0 },
19768 	{ "PCIE_VF_256_INT_CFG2", 0x5d4c, 0 },
19772 	{ "PCIE_VF_256_INT_CFG2", 0x5d50, 0 },
19776 	{ "PCIE_VF_256_INT_CFG2", 0x5d54, 0 },
19780 	{ "PCIE_VF_256_INT_CFG2", 0x5d58, 0 },
19784 	{ "PCIE_VF_256_INT_CFG2", 0x5d5c, 0 },
19788 	{ "PCIE_VF_256_INT_CFG2", 0x5d60, 0 },
19792 	{ "PCIE_VF_256_INT_CFG2", 0x5d64, 0 },
19796 	{ "PCIE_VF_256_INT_CFG2", 0x5d68, 0 },
19800 	{ "PCIE_VF_256_INT_CFG2", 0x5d6c, 0 },
19804 	{ "PCIE_VF_256_INT_CFG2", 0x5d70, 0 },
19808 	{ "PCIE_VF_256_INT_CFG2", 0x5d74, 0 },
19812 	{ "PCIE_VF_256_INT_CFG2", 0x5d78, 0 },
19816 	{ "PCIE_VF_256_INT_CFG2", 0x5d7c, 0 },
19820 	{ "PCIE_VF_256_INT_CFG2", 0x5d80, 0 },
19824 	{ "PCIE_VF_256_INT_CFG2", 0x5d84, 0 },
19828 	{ "PCIE_VF_256_INT_CFG2", 0x5d88, 0 },
19832 	{ "PCIE_VF_256_INT_CFG2", 0x5d8c, 0 },
19836 	{ "PCIE_VF_256_INT_CFG2", 0x5d90, 0 },
19840 	{ "PCIE_VF_256_INT_CFG2", 0x5d94, 0 },
19844 	{ "PCIE_VF_256_INT_CFG2", 0x5d98, 0 },
19848 	{ "PCIE_VF_256_INT_CFG2", 0x5d9c, 0 },
19852 	{ "PCIE_VF_256_INT_CFG2", 0x5da0, 0 },
19856 	{ "PCIE_VF_256_INT_CFG2", 0x5da4, 0 },
19860 	{ "PCIE_VF_256_INT_CFG2", 0x5da8, 0 },
19864 	{ "PCIE_VF_256_INT_CFG2", 0x5dac, 0 },
19868 	{ "PCIE_VF_256_INT_CFG2", 0x5db0, 0 },
19872 	{ "PCIE_VF_256_INT_CFG2", 0x5db4, 0 },
19876 	{ "PCIE_VF_256_INT_CFG2", 0x5db8, 0 },
19880 	{ "PCIE_VF_256_INT_CFG2", 0x5dbc, 0 },
19884 	{ "PCIE_VF_256_INT_CFG2", 0x5dc0, 0 },
19888 	{ "PCIE_VF_256_INT_CFG2", 0x5dc4, 0 },
19892 	{ "PCIE_VF_256_INT_CFG2", 0x5dc8, 0 },
19896 	{ "PCIE_VF_256_INT_CFG2", 0x5dcc, 0 },
19900 	{ "PCIE_VF_256_INT_CFG2", 0x5dd0, 0 },
19904 	{ "PCIE_VF_256_INT_CFG2", 0x5dd4, 0 },
19908 	{ "PCIE_VF_256_INT_CFG2", 0x5dd8, 0 },
19912 	{ "PCIE_VF_256_INT_CFG2", 0x5ddc, 0 },
19916 	{ "PCIE_VF_256_INT_CFG2", 0x5de0, 0 },
19920 	{ "PCIE_VF_256_INT_CFG2", 0x5de4, 0 },
19924 	{ "PCIE_VF_256_INT_CFG2", 0x5de8, 0 },
19928 	{ "PCIE_VF_256_INT_CFG2", 0x5dec, 0 },
19932 	{ "PCIE_VF_256_INT_CFG2", 0x5df0, 0 },
19936 	{ "PCIE_VF_256_INT_CFG2", 0x5df4, 0 },
19940 	{ "PCIE_VF_256_INT_CFG2", 0x5df8, 0 },
19944 	{ "PCIE_VF_256_INT_CFG2", 0x5dfc, 0 },
19948 	{ "PCIE_VF_256_INT_CFG2", 0x5e00, 0 },
19952 	{ "PCIE_VF_256_INT_CFG2", 0x5e04, 0 },
19956 	{ "PCIE_VF_256_INT_CFG2", 0x5e08, 0 },
19960 	{ "PCIE_VF_256_INT_CFG2", 0x5e0c, 0 },
19964 	{ "PCIE_VF_256_INT_CFG2", 0x5e10, 0 },
19968 	{ "PCIE_VF_256_INT_CFG2", 0x5e14, 0 },
19972 	{ "PCIE_VF_256_INT_CFG2", 0x5e18, 0 },
19976 	{ "PCIE_VF_256_INT_CFG2", 0x5e1c, 0 },
19980 	{ "PCIE_VF_256_INT_CFG2", 0x5e20, 0 },
19984 	{ "PCIE_VF_256_INT_CFG2", 0x5e24, 0 },
19988 	{ "PCIE_VF_256_INT_CFG2", 0x5e28, 0 },
19992 	{ "PCIE_VF_256_INT_CFG2", 0x5e2c, 0 },
19996 	{ "PCIE_VF_256_INT_CFG2", 0x5e30, 0 },
20000 	{ "PCIE_VF_256_INT_CFG2", 0x5e34, 0 },
20004 	{ "PCIE_VF_256_INT_CFG2", 0x5e38, 0 },
20008 	{ "PCIE_VF_256_INT_CFG2", 0x5e3c, 0 },
20012 	{ "PCIE_VF_256_INT_CFG2", 0x5e40, 0 },
20016 	{ "PCIE_VF_256_INT_CFG2", 0x5e44, 0 },
20020 	{ "PCIE_VF_256_INT_CFG2", 0x5e48, 0 },
20024 	{ "PCIE_VF_MSI_EN_4", 0x5e50, 0 },
20025 	{ "PCIE_VF_MSI_EN_5", 0x5e54, 0 },
20026 	{ "PCIE_VF_MSI_EN_6", 0x5e58, 0 },
20027 	{ "PCIE_VF_MSI_EN_7", 0x5e5c, 0 },
20028 	{ "PCIE_VF_MSIX_EN_4", 0x5e60, 0 },
20029 	{ "PCIE_VF_MSIX_EN_5", 0x5e64, 0 },
20030 	{ "PCIE_VF_MSIX_EN_6", 0x5e68, 0 },
20031 	{ "PCIE_VF_MSIX_EN_7", 0x5e6c, 0 },
20032 	{ "PCIE_FLR_VF4_STATUS", 0x5e70, 0 },
20033 	{ "PCIE_FLR_VF5_STATUS", 0x5e74, 0 },
20034 	{ "PCIE_FLR_VF6_STATUS", 0x5e78, 0 },
20035 	{ "PCIE_FLR_VF7_STATUS", 0x5e7c, 0 },
20036 	{ "PCIE_BUS_MST_STAT_4", 0x5e80, 0 },
20037 	{ "PCIE_BUS_MST_STAT_5", 0x5e84, 0 },
20038 	{ "PCIE_BUS_MST_STAT_6", 0x5e88, 0 },
20039 	{ "PCIE_BUS_MST_STAT_7", 0x5e8c, 0 },
20040 	{ "PCIE_BUS_MST_STAT_8", 0x5e90, 0 },
20041 	{ "PCIE_TGT_SKID_FIFO", 0x5e94, 0 },
20043 		{ "DataFreeCnt", 0, 12 },
20044 	{ "PCIE_RSP_ERR_STAT_4", 0x5ea0, 0 },
20045 	{ "PCIE_RSP_ERR_STAT_5", 0x5ea4, 0 },
20046 	{ "PCIE_RSP_ERR_STAT_6", 0x5ea8, 0 },
20047 	{ "PCIE_RSP_ERR_STAT_7", 0x5eac, 0 },
20048 	{ "PCIE_RSP_ERR_STAT_8", 0x5eb0, 0 },
20049 	{ "PCIE_PHY_STAT1", 0x5ec0, 0 },
20052 	{ "PCIE_PHY_CTRL1", 0x5ec4, 0 },
20057 		{ "TxDeemph_gen2_6db", 0, 8 },
20058 	{ "PCIE_PCIE_SPARE0", 0x5ec8, 0 },
20059 	{ "PCIE_RESET_STAT", 0x5ecc, 0 },
20068 		{ "LastResetState", 0, 3 },
20069 	{ "PCIE_FUNC_DSTATE", 0x5ed0, 0 },
20077 		{ "PF0_DState", 0, 3 },
20078 	{ "PCIE_DEBUG_ADDR_RANGE1", 0x5ee0, 0 },
20079 	{ "PCIE_DEBUG_ADDR_RANGE2", 0x5ef0, 0 },
20080 	{ "PCIE_DEBUG_ADDR_RANGE_CNT", 0x5f00, 0 },
20085 	{ "DBG_DBG0_CFG", 0x6000, 0 },
20088 		{ "ClkSelect", 0, 4 },
20089 	{ "DBG_DBG0_EN", 0x6004, 0 },
20092 		{ "PortEn", 0, 1 },
20093 	{ "DBG_DBG1_CFG", 0x6008, 0 },
20096 		{ "ClkSelect", 0, 4 },
20097 	{ "DBG_DBG1_EN", 0x600c, 0 },
20101 		{ "PortEn", 0, 1 },
20102 	{ "DBG_GPIO_EN", 0x6010, 0 },
20134 		{ "GPIO0_Out_Val", 0, 1 },
20135 	{ "DBG_GPIO_IN", 0x6014, 0 },
20167 		{ "GPIO0_IN", 0, 1 },
20168 	{ "DBG_GPIO_EN_NEW", 0x6100, 0 },
20176 		{ "GPIO19_Out_Val", 0, 1 },
20177 	{ "DBG_GPIO_IN_NEW", 0x6104, 0 },
20185 		{ "GPIO16_IN", 0, 1 },
20186 	{ "DBG_INT_ENABLE", 0x6018, 0 },
20214 		{ "GPIO0", 0, 1 },
20215 	{ "DBG_INT_CAUSE", 0x601c, 0 },
20243 		{ "GPIO0", 0, 1 },
20244 	{ "DBG_DBG0_RST_VALUE", 0x6020, 0 },
20245 	{ "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 },
20251 		{ "C_OCLK_En", 0, 1 },
20252 	{ "DBG_PLL_LOCK", 0x602c, 0 },
20258 		{ "C_LOCK", 0, 1 },
20259 	{ "DBG_GPIO_ACT_LOW", 0x6030, 0 },
20285 		{ "GPIO0_ACT_LOW", 0, 1 },
20286 	{ "DBG_EFUSE_BYTE0_3", 0x6034, 0 },
20287 	{ "DBG_EFUSE_BYTE4_7", 0x6038, 0 },
20288 	{ "DBG_EFUSE_BYTE8_11", 0x603c, 0 },
20289 	{ "DBG_EFUSE_BYTE12_15", 0x6040, 0 },
20290 	{ "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 },
20309 	{ "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 },
20315 		{ "KR_OCLK_MUXSEL", 0, 3 },
20316 	{ "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 },
20317 	{ "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 },
20318 	{ "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 },
20319 	{ "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 },
20320 	{ "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 },
20321 	{ "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 },
20322 	{ "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 },
20323 	{ "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 },
20324 	{ "DBG_TRACE_COUNTER", 0x6080, 0 },
20326 		{ "Counter0", 0, 16 },
20327 	{ "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 },
20328 	{ "DBG_TRACE_CONF", 0x6088, 0 },
20334 		{ "dbg_operate0_or_1", 0, 1 },
20335 	{ "DBG_TRACE_RDEN", 0x608c, 0 },
20339 		{ "Rd_en0", 0, 1 },
20340 	{ "DBG_TRACE_WRADDR", 0x6090, 0 },
20342 		{ "Wr_pointer_addr0", 0, 9 },
20343 	{ "DBG_TRACE0_DATA_OUT", 0x6094, 0 },
20344 	{ "DBG_TRACE1_DATA_OUT", 0x6098, 0 },
20345 	{ "DBG_FUSE_SENSE_DONE", 0x609c, 0 },
20347 		{ "FUSE_DONE_SENSE", 0, 1 },
20348 	{ "DBG_TVSENSE_EN", 0x60a8, 0 },
20356 		{ "TVSENSE_RATIO", 0, 8 },
20357 	{ "DBG_CUST_EFUSE_OUT_EN", 0x60ac, 0 },
20358 	{ "DBG_CUST_EFUSE_SEL1_EN", 0x60b0, 0 },
20359 	{ "DBG_CUST_EFUSE_SEL2_EN", 0x60b4, 0 },
20367 		{ "DBG_FETIME", 0, 3 },
20368 	{ "DBG_STATIC_M_PLL_CONF1", 0x60b8, 0 },
20370 		{ "STATIC_M_PLL_FFSLEWRATE", 0, 8 },
20371 	{ "DBG_STATIC_M_PLL_CONF2", 0x60bc, 0 },
20380 		{ "STATIC_M_PLL_LOCKTUNE", 0, 5 },
20381 	{ "DBG_STATIC_M_PLL_CONF3", 0x60c0, 0 },
20387 		{ "STATIC_M_PLL_RANGEA", 0, 5 },
20388 	{ "DBG_STATIC_M_PLL_CONF4", 0x60c4, 0 },
20389 	{ "DBG_STATIC_M_PLL_CONF5", 0x60c8, 0 },
20394 		{ "STATIC_M_PLL_MULT", 0, 8 },
20395 	{ "DBG_STATIC_M_PLL_CONF6", 0x60cc, 0 },
20407 		{ "STATIC_SWMC1CfgRst_", 0, 1 },
20408 	{ "DBG_STATIC_C_PLL_CONF1", 0x60d0, 0 },
20410 		{ "STATIC_C_PLL_FFSLEWRATE", 0, 8 },
20411 	{ "DBG_STATIC_C_PLL_CONF2", 0x60d4, 0 },
20421 		{ "STATIC_C_PLL_LOCKTUNE", 0, 5 },
20422 	{ "DBG_STATIC_C_PLL_CONF3", 0x60d8, 0 },
20428 		{ "STATIC_C_PLL_RANGEA", 0, 5 },
20429 	{ "DBG_STATIC_C_PLL_CONF4", 0x60dc, 0 },
20430 	{ "DBG_STATIC_C_PLL_CONF5", 0x60e0, 0 },
20437 		{ "STATIC_C_PLL_MULT", 0, 8 },
20438 	{ "DBG_STATIC_U_PLL_CONF1", 0x60e4, 0 },
20440 		{ "STATIC_U_PLL_FFSLEWRATE", 0, 8 },
20441 	{ "DBG_STATIC_U_PLL_CONF2", 0x60e8, 0 },
20451 		{ "STATIC_U_PLL_LOCKTUNE", 0, 5 },
20452 	{ "DBG_STATIC_U_PLL_CONF3", 0x60ec, 0 },
20458 		{ "STATIC_U_PLL_RANGEA", 0, 5 },
20459 	{ "DBG_STATIC_U_PLL_CONF4", 0x60f0, 0 },
20460 	{ "DBG_STATIC_U_PLL_CONF5", 0x60f4, 0 },
20467 		{ "STATIC_U_PLL_MULT", 0, 8 },
20468 	{ "DBG_STATIC_KR_PLL_CONF1", 0x60f8, 0 },
20481 		{ "STATIC_KR_PLL_N1", 0, 4 },
20482 	{ "DBG_STATIC_KR_PLL_CONF2", 0x60fc, 0 },
20484 		{ "STATIC_KR_PLL_ANALOGTUNE", 0, 11 },
20485 	{ "DBG_STATIC_KX_PLL_CONF1", 0x6108, 0 },
20498 		{ "STATIC_KX_PLL_N1", 0, 4 },
20499 	{ "DBG_STATIC_KX_PLL_CONF2", 0x610c, 0 },
20501 		{ "STATIC_KX_PLL_ANALOGTUNE", 0, 11 },
20502 	{ "DBG_STATIC_C_DFS_CONF", 0x6110, 0 },
20507 		{ "STATIC_C_DFS_ENABLE", 0, 1 },
20508 	{ "DBG_STATIC_U_DFS_CONF", 0x6114, 0 },
20513 		{ "STATIC_U_DFS_ENABLE", 0, 1 },
20514 	{ "DBG_GPIO_PE_EN", 0x6118, 0 },
20534 		{ "GPIO0_PE_En", 0, 1 },
20535 	{ "DBG_GPIO_PS_EN", 0x611c, 0 },
20555 		{ "GPIO0_PS_En", 0, 1 },
20556 	{ "DBG_EFUSE_BYTE16_19", 0x6120, 0 },
20557 	{ "DBG_EFUSE_BYTE20_23", 0x6124, 0 },
20558 	{ "DBG_EFUSE_BYTE24_27", 0x6128, 0 },
20559 	{ "DBG_EFUSE_BYTE28_31", 0x612c, 0 },
20560 	{ "DBG_EFUSE_BYTE32_35", 0x6130, 0 },
20561 	{ "DBG_EFUSE_BYTE36_39", 0x6134, 0 },
20562 	{ "DBG_EFUSE_BYTE40_43", 0x6138, 0 },
20563 	{ "DBG_EFUSE_BYTE44_47", 0x613c, 0 },
20564 	{ "DBG_EFUSE_BYTE48_51", 0x6140, 0 },
20565 	{ "DBG_EFUSE_BYTE52_55", 0x6144, 0 },
20566 	{ "DBG_EFUSE_BYTE56_59", 0x6148, 0 },
20567 	{ "DBG_EFUSE_BYTE60_63", 0x614c, 0 },
20568 	{ "DBG_STATIC_U_PLL_CONF6", 0x6150, 0 },
20569 	{ "DBG_STATIC_C_PLL_CONF6", 0x6154, 0 },
20570 	{ "DBG_CUST_EFUSE_PROGRAM", 0x6158, 0 },
20574 		{ "EFUSE_DIN", 0, 8 },
20575 	{ "DBG_CUST_EFUSE_OUT", 0x615c, 0 },
20577 		{ "EFUSE_DOUT", 0, 8 },
20578 	{ "DBG_CUST_EFUSE_BYTE0_3", 0x6160, 0 },
20579 	{ "DBG_CUST_EFUSE_BYTE4_7", 0x6164, 0 },
20580 	{ "DBG_CUST_EFUSE_BYTE8_11", 0x6168, 0 },
20581 	{ "DBG_CUST_EFUSE_BYTE12_15", 0x616c, 0 },
20582 	{ "DBG_CUST_EFUSE_BYTE16_19", 0x6170, 0 },
20583 	{ "DBG_CUST_EFUSE_BYTE20_23", 0x6174, 0 },
20584 	{ "DBG_CUST_EFUSE_BYTE24_27", 0x6178, 0 },
20585 	{ "DBG_CUST_EFUSE_BYTE28_31", 0x617c, 0 },
20586 	{ "DBG_CUST_EFUSE_BYTE32_35", 0x6180, 0 },
20587 	{ "DBG_CUST_EFUSE_BYTE36_39", 0x6184, 0 },
20588 	{ "DBG_CUST_EFUSE_BYTE40_43", 0x6188, 0 },
20589 	{ "DBG_CUST_EFUSE_BYTE44_47", 0x618c, 0 },
20590 	{ "DBG_CUST_EFUSE_BYTE48_51", 0x6190, 0 },
20591 	{ "DBG_CUST_EFUSE_BYTE52_55", 0x6194, 0 },
20592 	{ "DBG_CUST_EFUSE_BYTE56_59", 0x6198, 0 },
20593 	{ "DBG_CUST_EFUSE_BYTE60_63", 0x619c, 0 },
20598 	{ "MA_CLIENT0_RD_LATENCY_THRESHOLD", 0x7700, 0 },
20602 		{ "THRESHOLD0_EN", 0, 1 },
20603 	{ "MA_CLIENT0_WR_LATENCY_THRESHOLD", 0x7704, 0 },
20607 		{ "THRESHOLD0_EN", 0, 1 },
20608 	{ "MA_CLIENT1_RD_LATENCY_THRESHOLD", 0x7708, 0 },
20612 		{ "THRESHOLD0_EN", 0, 1 },
20613 	{ "MA_CLIENT1_WR_LATENCY_THRESHOLD", 0x770c, 0 },
20617 		{ "THRESHOLD0_EN", 0, 1 },
20618 	{ "MA_CLIENT2_RD_LATENCY_THRESHOLD", 0x7710, 0 },
20622 		{ "THRESHOLD0_EN", 0, 1 },
20623 	{ "MA_CLIENT2_WR_LATENCY_THRESHOLD", 0x7714, 0 },
20627 		{ "THRESHOLD0_EN", 0, 1 },
20628 	{ "MA_CLIENT3_RD_LATENCY_THRESHOLD", 0x7718, 0 },
20632 		{ "THRESHOLD0_EN", 0, 1 },
20633 	{ "MA_CLIENT3_WR_LATENCY_THRESHOLD", 0x771c, 0 },
20637 		{ "THRESHOLD0_EN", 0, 1 },
20638 	{ "MA_CLIENT4_RD_LATENCY_THRESHOLD", 0x7720, 0 },
20642 		{ "THRESHOLD0_EN", 0, 1 },
20643 	{ "MA_CLIENT4_WR_LATENCY_THRESHOLD", 0x7724, 0 },
20647 		{ "THRESHOLD0_EN", 0, 1 },
20648 	{ "MA_CLIENT5_RD_LATENCY_THRESHOLD", 0x7728, 0 },
20652 		{ "THRESHOLD0_EN", 0, 1 },
20653 	{ "MA_CLIENT5_WR_LATENCY_THRESHOLD", 0x772c, 0 },
20657 		{ "THRESHOLD0_EN", 0, 1 },
20658 	{ "MA_CLIENT6_RD_LATENCY_THRESHOLD", 0x7730, 0 },
20662 		{ "THRESHOLD0_EN", 0, 1 },
20663 	{ "MA_CLIENT6_WR_LATENCY_THRESHOLD", 0x7734, 0 },
20667 		{ "THRESHOLD0_EN", 0, 1 },
20668 	{ "MA_CLIENT7_RD_LATENCY_THRESHOLD", 0x7738, 0 },
20672 		{ "THRESHOLD0_EN", 0, 1 },
20673 	{ "MA_CLIENT7_WR_LATENCY_THRESHOLD", 0x773c, 0 },
20677 		{ "THRESHOLD0_EN", 0, 1 },
20678 	{ "MA_CLIENT8_RD_LATENCY_THRESHOLD", 0x7740, 0 },
20682 		{ "THRESHOLD0_EN", 0, 1 },
20683 	{ "MA_CLIENT8_WR_LATENCY_THRESHOLD", 0x7744, 0 },
20687 		{ "THRESHOLD0_EN", 0, 1 },
20688 	{ "MA_CLIENT9_RD_LATENCY_THRESHOLD", 0x7748, 0 },
20692 		{ "THRESHOLD0_EN", 0, 1 },
20693 	{ "MA_CLIENT9_WR_LATENCY_THRESHOLD", 0x774c, 0 },
20697 		{ "THRESHOLD0_EN", 0, 1 },
20698 	{ "MA_CLIENT10_RD_LATENCY_THRESHOLD", 0x7750, 0 },
20702 		{ "THRESHOLD0_EN", 0, 1 },
20703 	{ "MA_CLIENT10_WR_LATENCY_THRESHOLD", 0x7754, 0 },
20707 		{ "THRESHOLD0_EN", 0, 1 },
20708 	{ "MA_CLIENT11_RD_LATENCY_THRESHOLD", 0x7758, 0 },
20712 		{ "THRESHOLD0_EN", 0, 1 },
20713 	{ "MA_CLIENT11_WR_LATENCY_THRESHOLD", 0x775c, 0 },
20717 		{ "THRESHOLD0_EN", 0, 1 },
20718 	{ "MA_CLIENT12_RD_LATENCY_THRESHOLD", 0x7760, 0 },
20722 		{ "THRESHOLD0_EN", 0, 1 },
20723 	{ "MA_CLIENT12_WR_LATENCY_THRESHOLD", 0x7764, 0 },
20727 		{ "THRESHOLD0_EN", 0, 1 },
20728 	{ "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 },
20732 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20733 	{ "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 },
20737 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20738 	{ "MA_ULPTX_DEBUG_CNT", 0x7770, 0 },
20742 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20743 	{ "MA_ULPRX_DEBUG_CNT", 0x7774, 0 },
20747 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20748 	{ "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 },
20752 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20753 	{ "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 },
20757 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20758 	{ "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 },
20762 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20763 	{ "MA_LE_DEBUG_CNT", 0x7784, 0 },
20767 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20768 	{ "MA_CIM_DEBUG_CNT", 0x7788, 0 },
20772 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20773 	{ "MA_PCIE_DEBUG_CNT", 0x778c, 0 },
20777 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20778 	{ "MA_PMTX_DEBUG_CNT", 0x7790, 0 },
20782 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20783 	{ "MA_PMRX_DEBUG_CNT", 0x7794, 0 },
20787 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20788 	{ "MA_HMA_DEBUG_CNT", 0x7798, 0 },
20792 		{ "DBG_WRITE_REQ_CNT", 0, 8 },
20793 	{ "MA_EDRAM0_BAR", 0x77c0, 0 },
20795 		{ "EDRAM0_SIZE", 0, 12 },
20796 	{ "MA_EDRAM1_BAR", 0x77c4, 0 },
20798 		{ "EDRAM1_SIZE", 0, 12 },
20799 	{ "MA_EXT_MEMORY0_BAR", 0x77c8, 0 },
20801 		{ "EXT_MEM0_SIZE", 0, 12 },
20802 	{ "MA_HOST_MEMORY_BAR", 0x77cc, 0 },
20804 		{ "HMA_SIZE", 0, 12 },
20805 	{ "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 },
20808 		{ "EXT_MEM_PAGE_SIZE", 0, 3 },
20809 	{ "MA_ARB_CTRL", 0x77d4, 0 },
20822 		{ "DIS_ADV_ARB", 0, 1 },
20823 	{ "MA_TARGET_MEM_ENABLE", 0x77d8, 0 },
20830 		{ "EDRAM0_ENABLE", 0, 1 },
20831 	{ "MA_INT_ENABLE", 0x77dc, 0 },
20834 		{ "MEM_WRAP_INT_ENABLE", 0, 1 },
20835 	{ "MA_INT_CAUSE", 0x77e0, 0 },
20838 		{ "MEM_WRAP_INT_CAUSE", 0, 1 },
20839 	{ "MA_INT_WRAP_STATUS", 0x77e4, 0 },
20841 		{ "MEM_WRAP_CLIENT_NUM", 0, 4 },
20842 	{ "MA_TP_THREAD1_MAPPER", 0x77e8, 0 },
20843 	{ "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 },
20844 	{ "MA_PARITY_ERROR_ENABLE1", 0x77f0, 0 },
20876 		{ "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 },
20877 	{ "MA_PARITY_ERROR_STATUS1", 0x77f4, 0 },
20909 		{ "CL0_PAR_RDQUEUE_ERROR", 0, 1 },
20910 	{ "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 },
20914 		{ "COHERANCY_ENABLE", 0, 1 },
20915 	{ "MA_ERROR_ENABLE", 0x77fc, 0 },
20917 		{ "UE_ENABLE", 0, 1 },
20918 	{ "MA_PARITY_ERROR_ENABLE2", 0x7800, 0 },
20920 		{ "ARB4_PAR_RDQUEUE_ERROR_EN", 0, 1 },
20921 	{ "MA_PARITY_ERROR_STATUS2", 0x7804, 0 },
20923 		{ "ARB4_PAR_RDQUEUE_ERROR", 0, 1 },
20924 	{ "MA_EXT_MEMORY1_BAR", 0x7808, 0 },
20926 		{ "EXT_MEM1_SIZE", 0, 12 },
20927 	{ "MA_PMTX_THROTTLE", 0x780c, 0 },
20929 		{ "FL_LIMIT", 0, 8 },
20930 	{ "MA_PMRX_THROTTLE", 0x7810, 0 },
20932 		{ "FL_LIMIT", 0, 8 },
20933 	{ "MA_SGE_TH0_WRDATA_CNT", 0x7814, 0 },
20934 	{ "MA_SGE_TH1_WRDATA_CNT", 0x7818, 0 },
20935 	{ "MA_ULPTX_WRDATA_CNT", 0x781c, 0 },
20936 	{ "MA_ULPRX_WRDATA_CNT", 0x7820, 0 },
20937 	{ "MA_ULPTXRX_WRDATA_CNT", 0x7824, 0 },
20938 	{ "MA_TP_TH0_WRDATA_CNT", 0x7828, 0 },
20939 	{ "MA_TP_TH1_WRDATA_CNT", 0x782c, 0 },
20940 	{ "MA_LE_WRDATA_CNT", 0x7830, 0 },
20941 	{ "MA_CIM_WRDATA_CNT", 0x7834, 0 },
20942 	{ "MA_PCIE_WRDATA_CNT", 0x7838, 0 },
20943 	{ "MA_PMTX_WRDATA_CNT", 0x783c, 0 },
20944 	{ "MA_PMRX_WRDATA_CNT", 0x7840, 0 },
20945 	{ "MA_HMA_WRDATA_CNT", 0x7844, 0 },
20946 	{ "MA_SGE_TH0_RDDATA_CNT", 0x7848, 0 },
20947 	{ "MA_SGE_TH1_RDDATA_CNT", 0x784c, 0 },
20948 	{ "MA_ULPTX_RDDATA_CNT", 0x7850, 0 },
20949 	{ "MA_ULPRX_RDDATA_CNT", 0x7854, 0 },
20950 	{ "MA_ULPTXRX_RDDATA_CNT", 0x7858, 0 },
20951 	{ "MA_TP_TH0_RDDATA_CNT", 0x785c, 0 },
20952 	{ "MA_TP_TH1_RDDATA_CNT", 0x7860, 0 },
20953 	{ "MA_LE_RDDATA_CNT", 0x7864, 0 },
20954 	{ "MA_CIM_RDDATA_CNT", 0x7868, 0 },
20955 	{ "MA_PCIE_RDDATA_CNT", 0x786c, 0 },
20956 	{ "MA_PMTX_RDDATA_CNT", 0x7870, 0 },
20957 	{ "MA_PMRX_RDDATA_CNT", 0x7874, 0 },
20958 	{ "MA_HMA_RDDATA_CNT", 0x7878, 0 },
20959 	{ "MA_EXIT_ADDR_FAULT", 0x787c, 0 },
20960 	{ "MA_DDR_DEVICE_CFG", 0x7880, 0 },
20962 		{ "DDR_MODE", 0, 1 },
20963 	{ "MA_TIMEOUT_CFG", 0x78cc, 0 },
20970 		{ "DELAY", 0, 16 },
20971 	{ "MA_TIMEOUT_CNT", 0x78d0, 0 },
20975 		{ "CNT_VAL", 0, 16 },
20976 	{ "MA_WRITE_TIMEOUT_ERROR_ENABLE", 0x78d4, 0 },
21004 		{ "CL0_WR_DATA_TO_EN", 0, 1 },
21005 	{ "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
21033 		{ "CL0_WR_DATA_TO_ERROR", 0, 1 },
21034 	{ "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
21062 		{ "CL0_RD_DATA_TO_EN", 0, 1 },
21063 	{ "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
21091 		{ "CL0_RD_DATA_TO_ERROR", 0, 1 },
21092 	{ "MA_BKP_CNT_SEL", 0x78e4, 0 },
21095 	{ "MA_BKP_CNT", 0x78e8, 0 },
21096 	{ "MA_WRT_ARB", 0x78ec, 0 },
21100 		{ "WR_WIN", 0, 8 },
21101 	{ "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
21115 		{ "CL0_IF_PAR_EN", 0, 1 },
21116 	{ "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
21130 		{ "CL0_IF_PAR_ERROR", 0, 1 },
21131 	{ "MA_LOCAL_DEBUG_CFG", 0x78f8, 0 },
21137 		{ "DEBUGSELL", 0, 5 },
21138 	{ "MA_LOCAL_DEBUG_RPT", 0x78fc, 0 },
21143 	{ "CIM_BOOT_CFG", 0x7b00, 0 },
21147 		{ "uPCRst", 0, 1 },
21148 	{ "CIM_BOOT_LEN", 0x7bf0, 0 },
21150 	{ "CIM_FLASH_BASE_ADDR", 0x7b04, 0 },
21152 	{ "CIM_FLASH_ADDR_SIZE", 0x7b08, 0 },
21154 	{ "CIM_EEPROM_BASE_ADDR", 0x7b0c, 0 },
21156 	{ "CIM_EEPROM_ADDR_SIZE", 0x7b10, 0 },
21158 	{ "CIM_SDRAM_BASE_ADDR", 0x7b14, 0 },
21160 	{ "CIM_SDRAM_ADDR_SIZE", 0x7b18, 0 },
21162 	{ "CIM_EXTMEM2_BASE_ADDR", 0x7b1c, 0 },
21164 	{ "CIM_EXTMEM2_ADDR_SIZE", 0x7b20, 0 },
21166 	{ "CIM_UP_SPARE_INT", 0x7b24, 0 },
21169 		{ "uPSpareInt", 0, 3 },
21170 	{ "CIM_HOST_INT_ENABLE", 0x7b28, 0 },
21199 	{ "CIM_HOST_INT_CAUSE", 0x7b2c, 0 },
21227 		{ "uPAccNonZero", 0, 1 },
21228 	{ "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 },
21259 		{ "RsvdSpaceIntEn", 0, 1 },
21260 	{ "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 },
21291 		{ "RsvdSpaceInt", 0, 1 },
21292 	{ "CIM_UP_INT_ENABLE", 0x7b38, 0 },
21322 	{ "CIM_UP_INT_CAUSE", 0x7b3c, 0 },
21351 		{ "uPAccNonZero", 0, 1 },
21352 	{ "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 },
21383 		{ "RsvdSpaceIntEn", 0, 1 },
21384 	{ "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 },
21415 		{ "RsvdSpaceInt", 0, 1 },
21416 	{ "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 },
21419 		{ "QueNumSelect", 0, 3 },
21420 	{ "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 },
21425 		{ "QueFullThrsh", 0, 9 },
21426 	{ "CIM_HOST_ACC_CTRL", 0x7b50, 0 },
21429 		{ "HostAddr", 0, 16 },
21430 	{ "CIM_HOST_ACC_DATA", 0x7b54, 0 },
21431 	{ "CIM_CDEBUGDATA", 0x7b58, 0 },
21433 		{ "CDebugDataL", 0, 16 },
21434 	{ "CIM_IBQ_DBG_CFG", 0x7b60, 0 },
21438 		{ "IbqDbgEn", 0, 1 },
21439 	{ "CIM_OBQ_DBG_CFG", 0x7b64, 0 },
21443 		{ "ObqDbgEn", 0, 1 },
21444 	{ "CIM_IBQ_DBG_DATA", 0x7b68, 0 },
21445 	{ "CIM_OBQ_DBG_DATA", 0x7b6c, 0 },
21446 	{ "CIM_DEBUGCFG", 0x7b70, 0 },
21454 		{ "DebugSelL", 0, 5 },
21455 	{ "CIM_DEBUGSTS", 0x7b74, 0 },
21458 		{ "PILADbgWrPtr", 0, 9 },
21459 	{ "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 },
21460 	{ "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 },
21461 	{ "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 },
21462 	{ "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 },
21463 	{ "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 },
21464 	{ "CIM_MEM_ZONE0_VA", 0x7b90, 0 },
21466 	{ "CIM_MEM_ZONE0_BA", 0x7b94, 0 },
21469 		{ "ZONE_DST", 0, 2 },
21470 	{ "CIM_MEM_ZONE0_LEN", 0x7b98, 0 },
21472 	{ "CIM_MEM_ZONE1_VA", 0x7b9c, 0 },
21474 	{ "CIM_MEM_ZONE1_BA", 0x7ba0, 0 },
21477 		{ "ZONE_DST", 0, 2 },
21478 	{ "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 },
21480 	{ "CIM_MEM_ZONE2_VA", 0x7ba8, 0 },
21482 	{ "CIM_MEM_ZONE2_BA", 0x7bac, 0 },
21485 		{ "ZONE_DST", 0, 2 },
21486 	{ "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 },
21488 	{ "CIM_MEM_ZONE3_VA", 0x7bb4, 0 },
21490 	{ "CIM_MEM_ZONE3_BA", 0x7bb8, 0 },
21493 		{ "ZONE_DST", 0, 2 },
21494 	{ "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 },
21496 	{ "CIM_MEM_ZONE4_VA", 0x7bc0, 0 },
21498 	{ "CIM_MEM_ZONE4_BA", 0x7bc4, 0 },
21501 		{ "ZONE_DST", 0, 2 },
21502 	{ "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 },
21504 	{ "CIM_MEM_ZONE5_VA", 0x7bcc, 0 },
21506 	{ "CIM_MEM_ZONE5_BA", 0x7bd0, 0 },
21509 		{ "ZONE_DST", 0, 2 },
21510 	{ "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 },
21512 	{ "CIM_MEM_ZONE6_VA", 0x7bd8, 0 },
21514 	{ "CIM_MEM_ZONE6_BA", 0x7bdc, 0 },
21517 		{ "ZONE_DST", 0, 2 },
21518 	{ "CIM_MEM_ZONE6_LEN", 0x7be0, 0 },
21520 	{ "CIM_MEM_ZONE7_VA", 0x7be4, 0 },
21522 	{ "CIM_MEM_ZONE7_BA", 0x7be8, 0 },
21525 		{ "ZONE_DST", 0, 2 },
21526 	{ "CIM_MEM_ZONE7_LEN", 0x7bec, 0 },
21528 	{ "CIM_GLB_TIMER_CTL", 0x7bf4, 0 },
21532 	{ "CIM_GLB_TIMER", 0x7bf8, 0 },
21533 	{ "CIM_GLB_TIMER_TICK", 0x7bfc, 0 },
21534 	{ "CIM_TIMER0", 0x7c00, 0 },
21535 	{ "CIM_TIMER1", 0x7c04, 0 },
21536 	{ "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 },
21538 		{ "DAddrTimeOutType", 0, 2 },
21539 	{ "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 },
21541 		{ "DAddrIllegalType", 0, 2 },
21542 	{ "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 },
21543 	{ "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 },
21544 	{ "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 },
21545 	{ "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 },
21546 	{ "CIM_PERR_INJECT", 0x7c20, 0 },
21548 		{ "InjectDataErr", 0, 1 },
21549 	{ "CIM_PERR_ENABLE", 0x7c24, 0 },
21550 	{ "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 },
21551 	{ "CIM_MA_TIMER_EN", 0x7c2c, 0 },
21553 		{ "ma_timer_enable", 0, 1 },
21554 	{ "CIM_UP_PO_SINGLE_OUTSTANDING", 0x7c30, 0 },
21555 	{ "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 },
21556 	{ "CIM_UP_OPERATION_FREQ", 0x7c38, 0 },
21557 	{ "CIM_CIM_IBQ_ERR_CODE", 0x7c3c, 0 },
21560 		{ "CIM_SGE0_PKT_ERR_CODE", 0, 8 },
21561 	{ "CIM_IBQ_DBG_WAIT_COUNTER", 0x7c40, 0 },
21562 	{ "CIM_PIO_UP_MST_CFG_SEL", 0x7c44, 0 },
21563 	{ "CIM_CGEN", 0x7c48, 0 },
21564 	{ "CIM_QUEUE_FEATURE_DISABLE", 0x7c4c, 0 },
21570 		{ "ibq_skid_fifo_eop_flsh_dsbl", 0, 1 },
21571 	{ "CIM_CGEN_GLOBAL", 0x7c50, 0 },
21572 	{ "CIM_DPSLP_EN", 0x7c54, 0 },
21573 	{ "CIM_PF_MAILBOX_DATA", 0x1e240, 0 },
21574 	{ "CIM_PF_MAILBOX_DATA", 0x1e244, 0 },
21575 	{ "CIM_PF_MAILBOX_DATA", 0x1e248, 0 },
21576 	{ "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 },
21577 	{ "CIM_PF_MAILBOX_DATA", 0x1e250, 0 },
21578 	{ "CIM_PF_MAILBOX_DATA", 0x1e254, 0 },
21579 	{ "CIM_PF_MAILBOX_DATA", 0x1e258, 0 },
21580 	{ "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 },
21581 	{ "CIM_PF_MAILBOX_DATA", 0x1e260, 0 },
21582 	{ "CIM_PF_MAILBOX_DATA", 0x1e264, 0 },
21583 	{ "CIM_PF_MAILBOX_DATA", 0x1e268, 0 },
21584 	{ "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 },
21585 	{ "CIM_PF_MAILBOX_DATA", 0x1e270, 0 },
21586 	{ "CIM_PF_MAILBOX_DATA", 0x1e274, 0 },
21587 	{ "CIM_PF_MAILBOX_DATA", 0x1e278, 0 },
21588 	{ "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 },
21589 	{ "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 },
21593 		{ "MBOwner", 0, 2 },
21594 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 },
21596 	{ "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 },
21598 	{ "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 },
21600 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e290, 0 },
21604 		{ "MBOwner", 0, 2 },
21605 	{ "CIM_PF_MAILBOX_DATA", 0x1e640, 0 },
21606 	{ "CIM_PF_MAILBOX_DATA", 0x1e644, 0 },
21607 	{ "CIM_PF_MAILBOX_DATA", 0x1e648, 0 },
21608 	{ "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 },
21609 	{ "CIM_PF_MAILBOX_DATA", 0x1e650, 0 },
21610 	{ "CIM_PF_MAILBOX_DATA", 0x1e654, 0 },
21611 	{ "CIM_PF_MAILBOX_DATA", 0x1e658, 0 },
21612 	{ "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 },
21613 	{ "CIM_PF_MAILBOX_DATA", 0x1e660, 0 },
21614 	{ "CIM_PF_MAILBOX_DATA", 0x1e664, 0 },
21615 	{ "CIM_PF_MAILBOX_DATA", 0x1e668, 0 },
21616 	{ "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 },
21617 	{ "CIM_PF_MAILBOX_DATA", 0x1e670, 0 },
21618 	{ "CIM_PF_MAILBOX_DATA", 0x1e674, 0 },
21619 	{ "CIM_PF_MAILBOX_DATA", 0x1e678, 0 },
21620 	{ "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 },
21621 	{ "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 },
21625 		{ "MBOwner", 0, 2 },
21626 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 },
21628 	{ "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 },
21630 	{ "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 },
21632 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e690, 0 },
21636 		{ "MBOwner", 0, 2 },
21637 	{ "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 },
21638 	{ "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 },
21639 	{ "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 },
21640 	{ "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 },
21641 	{ "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 },
21642 	{ "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 },
21643 	{ "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 },
21644 	{ "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 },
21645 	{ "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 },
21646 	{ "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 },
21647 	{ "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 },
21648 	{ "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 },
21649 	{ "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 },
21650 	{ "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 },
21651 	{ "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 },
21652 	{ "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 },
21653 	{ "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 },
21657 		{ "MBOwner", 0, 2 },
21658 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 },
21660 	{ "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 },
21662 	{ "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 },
21664 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ea90, 0 },
21668 		{ "MBOwner", 0, 2 },
21669 	{ "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 },
21670 	{ "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 },
21671 	{ "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 },
21672 	{ "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 },
21673 	{ "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 },
21674 	{ "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 },
21675 	{ "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 },
21676 	{ "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 },
21677 	{ "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 },
21678 	{ "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 },
21679 	{ "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 },
21680 	{ "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 },
21681 	{ "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 },
21682 	{ "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 },
21683 	{ "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 },
21684 	{ "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 },
21685 	{ "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 },
21689 		{ "MBOwner", 0, 2 },
21690 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 },
21692 	{ "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 },
21694 	{ "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 },
21696 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ee90, 0 },
21700 		{ "MBOwner", 0, 2 },
21701 	{ "CIM_PF_MAILBOX_DATA", 0x1f240, 0 },
21702 	{ "CIM_PF_MAILBOX_DATA", 0x1f244, 0 },
21703 	{ "CIM_PF_MAILBOX_DATA", 0x1f248, 0 },
21704 	{ "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 },
21705 	{ "CIM_PF_MAILBOX_DATA", 0x1f250, 0 },
21706 	{ "CIM_PF_MAILBOX_DATA", 0x1f254, 0 },
21707 	{ "CIM_PF_MAILBOX_DATA", 0x1f258, 0 },
21708 	{ "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 },
21709 	{ "CIM_PF_MAILBOX_DATA", 0x1f260, 0 },
21710 	{ "CIM_PF_MAILBOX_DATA", 0x1f264, 0 },
21711 	{ "CIM_PF_MAILBOX_DATA", 0x1f268, 0 },
21712 	{ "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 },
21713 	{ "CIM_PF_MAILBOX_DATA", 0x1f270, 0 },
21714 	{ "CIM_PF_MAILBOX_DATA", 0x1f274, 0 },
21715 	{ "CIM_PF_MAILBOX_DATA", 0x1f278, 0 },
21716 	{ "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 },
21717 	{ "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 },
21721 		{ "MBOwner", 0, 2 },
21722 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 },
21724 	{ "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 },
21726 	{ "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 },
21728 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f290, 0 },
21732 		{ "MBOwner", 0, 2 },
21733 	{ "CIM_PF_MAILBOX_DATA", 0x1f640, 0 },
21734 	{ "CIM_PF_MAILBOX_DATA", 0x1f644, 0 },
21735 	{ "CIM_PF_MAILBOX_DATA", 0x1f648, 0 },
21736 	{ "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 },
21737 	{ "CIM_PF_MAILBOX_DATA", 0x1f650, 0 },
21738 	{ "CIM_PF_MAILBOX_DATA", 0x1f654, 0 },
21739 	{ "CIM_PF_MAILBOX_DATA", 0x1f658, 0 },
21740 	{ "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 },
21741 	{ "CIM_PF_MAILBOX_DATA", 0x1f660, 0 },
21742 	{ "CIM_PF_MAILBOX_DATA", 0x1f664, 0 },
21743 	{ "CIM_PF_MAILBOX_DATA", 0x1f668, 0 },
21744 	{ "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 },
21745 	{ "CIM_PF_MAILBOX_DATA", 0x1f670, 0 },
21746 	{ "CIM_PF_MAILBOX_DATA", 0x1f674, 0 },
21747 	{ "CIM_PF_MAILBOX_DATA", 0x1f678, 0 },
21748 	{ "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 },
21749 	{ "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 },
21753 		{ "MBOwner", 0, 2 },
21754 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 },
21756 	{ "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 },
21758 	{ "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 },
21760 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f690, 0 },
21764 		{ "MBOwner", 0, 2 },
21765 	{ "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 },
21766 	{ "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 },
21767 	{ "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 },
21768 	{ "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 },
21769 	{ "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 },
21770 	{ "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 },
21771 	{ "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 },
21772 	{ "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 },
21773 	{ "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 },
21774 	{ "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 },
21775 	{ "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 },
21776 	{ "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 },
21777 	{ "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 },
21778 	{ "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 },
21779 	{ "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 },
21780 	{ "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 },
21781 	{ "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 },
21785 		{ "MBOwner", 0, 2 },
21786 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 },
21788 	{ "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 },
21790 	{ "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 },
21792 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fa90, 0 },
21796 		{ "MBOwner", 0, 2 },
21797 	{ "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 },
21798 	{ "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 },
21799 	{ "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 },
21800 	{ "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 },
21801 	{ "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 },
21802 	{ "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 },
21803 	{ "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 },
21804 	{ "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 },
21805 	{ "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 },
21806 	{ "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 },
21807 	{ "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 },
21808 	{ "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 },
21809 	{ "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 },
21810 	{ "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 },
21811 	{ "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 },
21812 	{ "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 },
21813 	{ "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 },
21817 		{ "MBOwner", 0, 2 },
21818 	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 },
21820 	{ "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 },
21822 	{ "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
21824 	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fe90, 0 },
21828 		{ "MBOwner", 0, 2 },
21833 	{ "TP_IN_CONFIG", 0x7d00, 0 },
21865 		{ "CFastDemuxEn", 0, 1 },
21866 	{ "TP_OUT_CONFIG", 0x7d04, 0 },
21889 		{ "CEthernet", 0, 1 },
21890 	{ "TP_GLOBAL_CONFIG", 0x7d08, 0 },
21904 		{ "IPTTL", 0, 8 },
21905 	{ "TP_DB_CONFIG", 0x7d0c, 0 },
21912 		{ "RxMaxOpCnt", 0, 7 },
21913 	{ "TP_CMM_TCB_BASE", 0x7d10, 0 },
21914 	{ "TP_CMM_MM_BASE", 0x7d14, 0 },
21915 	{ "TP_CMM_TIMER_BASE", 0x7d18, 0 },
21916 	{ "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 },
21918 		{ "TxPoolSize", 0, 16 },
21919 	{ "TP_PMM_TX_BASE", 0x7d20, 0 },
21920 	{ "TP_PMM_DEFRAG_BASE", 0x7d24, 0 },
21921 	{ "TP_PMM_RX_BASE", 0x7d28, 0 },
21922 	{ "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 },
21923 	{ "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 },
21925 		{ "PMRxMaxPage", 0, 21 },
21926 	{ "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 },
21927 	{ "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 },
21929 		{ "PMTxMaxPage", 0, 21 },
21930 	{ "TP_TCP_OPTIONS", 0x7d40, 0 },
21937 		{ "TimestampsMode", 0, 2 },
21938 	{ "TP_DACK_CONFIG", 0x7d44, 0 },
21946 		{ "Mode", 0, 1 },
21947 	{ "TP_PC_CONFIG", 0x7d48, 0 },
21979 		{ "TxDataAckPageEnable", 0, 1 },
21980 	{ "TP_PC_CONFIG2", 0x7d4c, 0 },
22012 		{ "EnableTnlOfdClosed", 0, 1 },
22013 	{ "TP_TCP_BACKOFF_REG0", 0x7d50, 0 },
22017 		{ "TimerBackoffIndex0", 0, 8 },
22018 	{ "TP_TCP_BACKOFF_REG1", 0x7d54, 0 },
22022 		{ "TimerBackoffIndex4", 0, 8 },
22023 	{ "TP_TCP_BACKOFF_REG2", 0x7d58, 0 },
22027 		{ "TimerBackoffIndex8", 0, 8 },
22028 	{ "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 },
22032 		{ "TimerBackoffIndex12", 0, 8 },
22033 	{ "TP_PARA_REG0", 0x7d60, 0 },
22054 		{ "SwsTimer", 0, 1 },
22055 	{ "TP_PARA_REG1", 0x7d64, 0 },
22057 		{ "InitialSSThresh", 0, 16 },
22058 	{ "TP_PARA_REG2", 0x7d68, 0 },
22060 		{ "RxCoalesceSize", 0, 16 },
22061 	{ "TP_PARA_REG3", 0x7d6c, 0 },
22086 		{ "RxCoalescePshEn", 0, 1 },
22087 	{ "TP_PARA_REG4", 0x7d70, 0 },
22103 		{ "ByteCountReno", 0, 1 },
22104 	{ "TP_PARA_REG5", 0x7d74, 0 },
22118 		{ "PushTimerEnable", 0, 1 },
22119 	{ "TP_PARA_REG6", 0x7d78, 0 },
22143 		{ "DisablePDUxmt", 0, 1 },
22144 	{ "TP_PARA_REG7", 0x7d7c, 0 },
22146 		{ "PMMaxXferLen0", 0, 16 },
22147 	{ "TP_ENG_CONFIG", 0x7d80, 0 },
22154 		{ "EngineLatencyBase", 0, 4 },
22155 	{ "TP_PARA_REG8", 0x7d84, 0 },
22158 		{ "EcnSynEct", 0, 1 },
22159 	{ "TP_ERR_CONFIG", 0x7d8c, 0 },
22191 		{ "DropErrorAny", 0, 1 },
22192 	{ "TP_TIMER_RESOLUTION", 0x7d90, 0 },
22195 		{ "DelayedACKResolution", 0, 8 },
22196 	{ "TP_MSL", 0x7d94, 0 },
22197 	{ "TP_RXT_MIN", 0x7d98, 0 },
22198 	{ "TP_RXT_MAX", 0x7d9c, 0 },
22199 	{ "TP_PERS_MIN", 0x7da0, 0 },
22200 	{ "TP_PERS_MAX", 0x7da4, 0 },
22201 	{ "TP_KEEP_IDLE", 0x7da8, 0 },
22202 	{ "TP_KEEP_INTVL", 0x7dac, 0 },
22203 	{ "TP_INIT_SRTT", 0x7db0, 0 },
22205 		{ "InitSrtt", 0, 16 },
22206 	{ "TP_DACK_TIMER", 0x7db4, 0 },
22207 	{ "TP_FINWAIT2_TIMER", 0x7db8, 0 },
22208 	{ "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 },
22209 	{ "TP_SHIFT_CNT", 0x7dc0, 0 },
22216 		{ "KeepaliveMaxR2", 0, 4 },
22217 	{ "TP_TM_CONFIG", 0x7dc4, 0 },
22218 	{ "TP_TIME_LO", 0x7dc8, 0 },
22219 	{ "TP_TIME_HI", 0x7dcc, 0 },
22220 	{ "TP_PORT_MTU_0", 0x7dd0, 0 },
22222 		{ "Port0MTUValue", 0, 16 },
22223 	{ "TP_PORT_MTU_1", 0x7dd4, 0 },
22225 		{ "Port2MTUValue", 0, 16 },
22226 	{ "TP_PACE_TABLE", 0x7dd8, 0 },
22227 	{ "TP_CCTRL_TABLE", 0x7ddc, 0 },
22229 		{ "RowValue", 0, 16 },
22230 	{ "TP_MTU_TABLE", 0x7de4, 0 },
22233 		{ "MTUValue", 0, 14 },
22234 	{ "TP_ULP_TABLE", 0x7de8, 0 },
22250 		{ "ULPType0Offset", 0, 3 },
22251 	{ "TP_RSS_LKP_TABLE", 0x7dec, 0 },
22255 		{ "LkpTblQueue0", 0, 10 },
22256 	{ "TP_RSS_CONFIG", 0x7df0, 0 },
22288 		{ "Disable", 0, 1 },
22289 	{ "TP_RSS_CONFIG_TNL", 0x7df4, 0 },
22294 		{ "UseWireCh", 0, 1 },
22295 	{ "TP_RSS_CONFIG_OFD", 0x7df8, 0 },
22300 	{ "TP_RSS_CONFIG_SYN", 0x7dfc, 0 },
22302 		{ "UseWireCh", 0, 1 },
22303 	{ "TP_RSS_CONFIG_VRT", 0x7e00, 0 },
22317 		{ "KeyWrAddr", 0, 4 },
22318 	{ "TP_RSS_CONFIG_CNG", 0x7e04, 0 },
22341 		{ "Queue", 0, 10 },
22342 	{ "TP_LA_TABLE_0", 0x7e10, 0 },
22344 		{ "VirtPort0Table", 0, 16 },
22345 	{ "TP_LA_TABLE_1", 0x7e14, 0 },
22347 		{ "VirtPort2Table", 0, 16 },
22348 	{ "TP_TM_PIO_ADDR", 0x7e18, 0 },
22349 	{ "TP_TM_PIO_DATA", 0x7e1c, 0 },
22350 	{ "TP_MOD_CONFIG", 0x7e24, 0 },
22354 		{ "TxChannelXoffEn", 0, 4 },
22355 	{ "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 },
22358 		{ "TX_MOD_QUEUE_REQ_MAP", 0, 16 },
22359 	{ "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 },
22363 		{ "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
22364 	{ "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 },
22368 		{ "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
22369 	{ "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 },
22373 		{ "CH0", 0, 8 },
22374 	{ "TP_MOD_RATE_LIMIT", 0x7e38, 0 },
22378 		{ "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
22379 	{ "TP_PIO_ADDR", 0x7e40, 0 },
22380 	{ "TP_PIO_DATA", 0x7e44, 0 },
22381 	{ "TP_RESET", 0x7e4c, 0 },
22383 		{ "TPReset", 0, 1 },
22384 	{ "TP_MIB_INDEX", 0x7e50, 0 },
22385 	{ "TP_MIB_DATA", 0x7e54, 0 },
22386 	{ "TP_SYNC_TIME_HI", 0x7e58, 0 },
22387 	{ "TP_SYNC_TIME_LO", 0x7e5c, 0 },
22388 	{ "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 },
22389 	{ "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 },
22390 	{ "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 },
22391 	{ "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 },
22392 	{ "TP_INT_ENABLE", 0x7e70, 0 },
22423 		{ "DelInvFifoPerr", 0, 1 },
22424 	{ "TP_INT_CAUSE", 0x7e74, 0 },
22455 		{ "DelInvFifoPerr", 0, 1 },
22456 	{ "TP_PER_ENABLE", 0x7e78, 0 },
22487 		{ "DelInvFifoPerr", 0, 1 },
22488 	{ "TP_FLM_FREE_PS_CNT", 0x7e80, 0 },
22489 	{ "TP_FLM_FREE_RX_CNT", 0x7e84, 0 },
22491 		{ "FreeRxPageCount", 0, 21 },
22492 	{ "TP_FLM_FREE_TX_CNT", 0x7e88, 0 },
22494 		{ "FreeTxPageCount", 0, 21 },
22495 	{ "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 },
22496 	{ "TP_TM_HEAP_POP_CNT", 0x7e90, 0 },
22497 	{ "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 },
22498 	{ "TP_TM_DACK_POP_CNT", 0x7e98, 0 },
22499 	{ "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 },
22500 	{ "TP_MOD_POP_CNT", 0x7ea0, 0 },
22501 	{ "TP_TIMER_SEPARATOR", 0x7ea4, 0 },
22503 		{ "DisableTimeFreeze", 0, 1 },
22504 	{ "TP_STAMP_TIME", 0x7ea8, 0 },
22505 	{ "TP_DEBUG_FLAGS", 0x7eac, 0 },
22531 		{ "TxRcvAdvLtMss", 0, 1 },
22532 	{ "TP_RX_SCHED", 0x7eb0, 0 },
22545 	{ "TP_TX_SCHED", 0x7eb4, 0 },
22557 		{ "CommitLimit0", 0, 6 },
22558 	{ "TP_FX_SCHED", 0x7eb8, 0 },
22576 		{ "RxModXoff0", 0, 1 },
22577 	{ "TP_TX_ORATE", 0x7ebc, 0 },
22581 		{ "OfdRate0", 0, 8 },
22582 	{ "TP_IX_SCHED0", 0x7ec0, 0 },
22583 	{ "TP_IX_SCHED1", 0x7ec4, 0 },
22584 	{ "TP_IX_SCHED2", 0x7ec8, 0 },
22585 	{ "TP_IX_SCHED3", 0x7ecc, 0 },
22586 	{ "TP_TX_TRATE", 0x7ed0, 0 },
22590 		{ "TnlRate0", 0, 8 },
22591 	{ "TP_DBG_LA_CONFIG", 0x7ed4, 0 },
22598 		{ "DbgLaRptr", 0, 7 },
22599 	{ "TP_DBG_LA_DATAL", 0x7ed8, 0 },
22600 	{ "TP_DBG_LA_DATAH", 0x7edc, 0 },
22601 	{ "TP_PROTOCOL_CNTRL", 0x7ee8, 0 },
22606 		{ "RequestDone", 0, 1 },
22607 	{ "TP_PROTOCOL_DATA0", 0x7eec, 0 },
22608 	{ "TP_PROTOCOL_DATA1", 0x7ef0, 0 },
22609 	{ "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
22610 	{ "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
22611 	{ "TP_PROTOCOL_DATA4", 0x7efc, 0 },
22616 	{ "ULP_TX_CONFIG", 0x8dc0, 0 },
22633 		{ "extra_tag_insertion_enable", 0, 1 },
22634 	{ "ULP_TX_PERR_INJECT", 0x8dc4, 0 },
22636 		{ "InjectDataErr", 0, 1 },
22637 	{ "ULP_TX_INT_ENABLE", 0x8dc8, 0 },
22666 	{ "ULP_TX_INT_CAUSE", 0x8dcc, 0 },
22695 	{ "ULP_TX_PERR_ENABLE", 0x8dd0, 0 },
22720 	{ "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 },
22721 	{ "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 },
22722 	{ "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 },
22723 	{ "ULP_TX_PBL_ULIMIT", 0x8de0, 0 },
22724 	{ "ULP_TX_TLS_CTL", 0x8de4, 0 },
22729 		{ "TlsDisable", 0, 1 },
22730 	{ "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 },
22734 		{ "Ch0Size1", 0, 8 },
22735 	{ "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 },
22739 		{ "Ch0Size2", 0, 8 },
22740 	{ "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 },
22741 	{ "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 },
22742 	{ "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 },
22743 	{ "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 },
22744 	{ "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 },
22745 	{ "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 },
22746 	{ "ULP_TX_FC_SOF", 0x8e20, 0 },
22750 		{ "SOF_2", 0, 8 },
22751 	{ "ULP_TX_FC_EOF", 0x8e24, 0 },
22755 		{ "EOF_2", 0, 8 },
22756 	{ "ULP_TX_CGEN_GLOBAL", 0x8e28, 0 },
22757 	{ "ULP_TX_CGEN", 0x8e2c, 0 },
22760 		{ "ULP_TX_CGEN_Channel", 0, 4 },
22761 	{ "ULP_TX_MEM_CFG", 0x8e30, 0 },
22762 	{ "ULP_TX_PERR_INJECT_2", 0x8e34, 0 },
22764 		{ "InjectDataErr", 0, 1 },
22765 	{ "ULP_TX_FPGA_CMD_CTRL", 0x8e38, 0 },
22766 	{ "ULP_TX_FPGA_CMD_0", 0x8e3c, 0 },
22767 	{ "ULP_TX_FPGA_CMD_1", 0x8e40, 0 },
22768 	{ "ULP_TX_FPGA_CMD_2", 0x8e44, 0 },
22769 	{ "ULP_TX_FPGA_CMD_3", 0x8e48, 0 },
22770 	{ "ULP_TX_FPGA_CMD_4", 0x8e4c, 0 },
22771 	{ "ULP_TX_FPGA_CMD_5", 0x8e50, 0 },
22772 	{ "ULP_TX_FPGA_CMD_6", 0x8e54, 0 },
22773 	{ "ULP_TX_FPGA_CMD_7", 0x8e58, 0 },
22774 	{ "ULP_TX_FPGA_CMD_8", 0x8e5c, 0 },
22775 	{ "ULP_TX_FPGA_CMD_9", 0x8e60, 0 },
22776 	{ "ULP_TX_FPGA_CMD_10", 0x8e64, 0 },
22777 	{ "ULP_TX_FPGA_CMD_11", 0x8e68, 0 },
22778 	{ "ULP_TX_FPGA_CMD_12", 0x8e6c, 0 },
22779 	{ "ULP_TX_FPGA_CMD_13", 0x8e70, 0 },
22780 	{ "ULP_TX_FPGA_CMD_14", 0x8e74, 0 },
22781 	{ "ULP_TX_FPGA_CMD_15", 0x8e78, 0 },
22782 	{ "ULP_TX_INT_ENABLE_2", 0x8e7c, 0 },
22814 		{ "t10_pi_sram_perr_set0", 0, 1 },
22815 	{ "ULP_TX_INT_CAUSE_2", 0x8e80, 0 },
22847 		{ "t10_pi_sram_perr_set0", 0, 1 },
22848 	{ "ULP_TX_PERR_ENABLE_2", 0x8e84, 0 },
22880 		{ "t10_pi_sram_perr_set0", 0, 1 },
22881 	{ "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 },
22885 		{ "ERR_CH0", 0, 4 },
22886 	{ "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 },
22891 		{ "CLR_CH0", 0, 4 },
22892 	{ "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 },
22900 		{ "EOP_CNT_CIM2ULP", 0, 4 },
22901 	{ "ULP_TX_SE_CNT_CH1", 0x8eac, 0 },
22909 		{ "EOP_CNT_CIM2ULP", 0, 4 },
22910 	{ "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 },
22918 		{ "EOP_CNT_CIM2ULP", 0, 4 },
22919 	{ "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 },
22927 		{ "EOP_CNT_CIM2ULP", 0, 4 },
22928 	{ "ULP_TX_DROP_CNT", 0x8eb8, 0 },
22936 		{ "DROP_CH0", 0, 4 },
22937 	{ "ULP_TX_CSU_REVISION", 0x8ebc, 0 },
22938 	{ "ULP_TX_LA_RDPTR_0", 0x8ec0, 0 },
22939 	{ "ULP_TX_LA_RDDATA_0", 0x8ec4, 0 },
22940 	{ "ULP_TX_LA_WRPTR_0", 0x8ec8, 0 },
22941 	{ "ULP_TX_LA_RESERVED_0", 0x8ecc, 0 },
22942 	{ "ULP_TX_LA_RDPTR_1", 0x8ed0, 0 },
22943 	{ "ULP_TX_LA_RDDATA_1", 0x8ed4, 0 },
22944 	{ "ULP_TX_LA_WRPTR_1", 0x8ed8, 0 },
22945 	{ "ULP_TX_LA_RESERVED_1", 0x8edc, 0 },
22946 	{ "ULP_TX_LA_RDPTR_2", 0x8ee0, 0 },
22947 	{ "ULP_TX_LA_RDDATA_2", 0x8ee4, 0 },
22948 	{ "ULP_TX_LA_WRPTR_2", 0x8ee8, 0 },
22949 	{ "ULP_TX_LA_RESERVED_2", 0x8eec, 0 },
22950 	{ "ULP_TX_LA_RDPTR_3", 0x8ef0, 0 },
22951 	{ "ULP_TX_LA_RDDATA_3", 0x8ef4, 0 },
22952 	{ "ULP_TX_LA_WRPTR_3", 0x8ef8, 0 },
22953 	{ "ULP_TX_LA_RESERVED_3", 0x8efc, 0 },
22954 	{ "ULP_TX_LA_RDPTR_4", 0x8f00, 0 },
22955 	{ "ULP_TX_LA_RDDATA_4", 0x8f04, 0 },
22956 	{ "ULP_TX_LA_WRPTR_4", 0x8f08, 0 },
22957 	{ "ULP_TX_LA_RESERVED_4", 0x8f0c, 0 },
22958 	{ "ULP_TX_LA_RDPTR_5", 0x8f10, 0 },
22959 	{ "ULP_TX_LA_RDDATA_5", 0x8f14, 0 },
22960 	{ "ULP_TX_LA_WRPTR_5", 0x8f18, 0 },
22961 	{ "ULP_TX_LA_RESERVED_5", 0x8f1c, 0 },
22962 	{ "ULP_TX_LA_RDPTR_6", 0x8f20, 0 },
22963 	{ "ULP_TX_LA_RDDATA_6", 0x8f24, 0 },
22964 	{ "ULP_TX_LA_WRPTR_6", 0x8f28, 0 },
22965 	{ "ULP_TX_LA_RESERVED_6", 0x8f2c, 0 },
22966 	{ "ULP_TX_LA_RDPTR_7", 0x8f30, 0 },
22967 	{ "ULP_TX_LA_RDDATA_7", 0x8f34, 0 },
22968 	{ "ULP_TX_LA_WRPTR_7", 0x8f38, 0 },
22969 	{ "ULP_TX_LA_RESERVED_7", 0x8f3c, 0 },
22970 	{ "ULP_TX_LA_RDPTR_8", 0x8f40, 0 },
22971 	{ "ULP_TX_LA_RDDATA_8", 0x8f44, 0 },
22972 	{ "ULP_TX_LA_WRPTR_8", 0x8f48, 0 },
22973 	{ "ULP_TX_LA_RESERVED_8", 0x8f4c, 0 },
22974 	{ "ULP_TX_LA_RDPTR_9", 0x8f50, 0 },
22975 	{ "ULP_TX_LA_RDDATA_9", 0x8f54, 0 },
22976 	{ "ULP_TX_LA_WRPTR_9", 0x8f58, 0 },
22977 	{ "ULP_TX_LA_RESERVED_9", 0x8f5c, 0 },
22978 	{ "ULP_TX_LA_RDPTR_10", 0x8f60, 0 },
22979 	{ "ULP_TX_LA_RDDATA_10", 0x8f64, 0 },
22980 	{ "ULP_TX_LA_WRPTR_10", 0x8f68, 0 },
22981 	{ "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 },
22982 	{ "ULP_TX_ASIC_DEBUG_CTRL", 0x8f70, 0 },
22983 	{ "ULP_TX_CPL_TX_DATA_FLAGS_MASK", 0x8f88, 0 },
23004 		{ "shove_last", 0, 1 },
23005 	{ "ULP_TX_TLS_IND_CMD", 0x8fb8, 0 },
23006 	{ "ULP_TX_TLS_IND_DATA", 0x8fbc, 0 },
23007 	{ "ULP_TX_ASIC_DEBUG_0", 0x8f74, 0 },
23008 	{ "ULP_TX_ASIC_DEBUG_1", 0x8f78, 0 },
23009 	{ "ULP_TX_ASIC_DEBUG_2", 0x8f7c, 0 },
23010 	{ "ULP_TX_ASIC_DEBUG_3", 0x8f80, 0 },
23011 	{ "ULP_TX_ASIC_DEBUG_4", 0x8f84, 0 },
23016 	{ "PM_RX_CFG", 0x8fc0, 0 },
23022 		{ "strobe0", 0, 1 },
23023 	{ "PM_RX_MODE", 0x8fc4, 0 },
23027 		{ "prefetch_enable", 0, 1 },
23028 	{ "PM_RX_STAT_CONFIG", 0x8fc8, 0 },
23029 	{ "PM_RX_STAT_COUNT", 0x8fcc, 0 },
23030 	{ "PM_RX_DBG_CTRL", 0x8fd0, 0 },
23033 		{ "PMDbgAddr", 0, 17 },
23034 	{ "PM_RX_DBG_DATA", 0x8fd4, 0 },
23035 	{ "PM_RX_INT_ENABLE", 0x8fd8, 0 },
23064 		{ "e_pcmd_par_error", 0, 1 },
23065 	{ "PM_RX_INT_CAUSE", 0x8fdc, 0 },
23094 		{ "e_pcmd_par_error", 0, 1 },
23099 	{ "PM_TX_CFG", 0x8fe0, 0 },
23107 		{ "strobe0", 0, 1 },
23108 	{ "PM_TX_MODE", 0x8fe4, 0 },
23115 		{ "prefetch_enable", 0, 1 },
23116 	{ "PM_TX_STAT_CONFIG", 0x8fe8, 0 },
23117 	{ "PM_TX_STAT_COUNT", 0x8fec, 0 },
23118 	{ "PM_TX_DBG_CTRL", 0x8ff0, 0 },
23121 		{ "PMDbgAddr", 0, 17 },
23122 	{ "PM_TX_DBG_DATA", 0x8ff4, 0 },
23123 	{ "PM_TX_INT_ENABLE", 0x8ff8, 0 },
23155 		{ "c_pcmd_par_error", 0, 1 },
23156 	{ "PM_TX_INT_CAUSE", 0x8ffc, 0 },
23188 		{ "c_pcmd_par_error", 0, 1 },
23193 	{ "MPS_CMN_CTL", 0x9000, 0 },
23200 		{ "NumPorts", 0, 2 },
23201 	{ "MPS_INT_ENABLE", 0x9004, 0 },
23207 		{ "PLIntEnb", 0, 1 },
23208 	{ "MPS_INT_CAUSE", 0x9008, 0 },
23214 		{ "PLInt", 0, 1 },
23215 	{ "MPS_CGEN_GLOBAL", 0x900c, 0 },
23216 	{ "MPS_VF_TX_CTL_31_0", 0x9010, 0 },
23217 	{ "MPS_VF_TX_CTL_63_32", 0x9014, 0 },
23218 	{ "MPS_VF_TX_CTL_95_64", 0x9018, 0 },
23219 	{ "MPS_VF_TX_CTL_127_96", 0x901c, 0 },
23220 	{ "MPS_VF_TX_CTL_159_128", 0x9100, 0 },
23221 	{ "MPS_VF_TX_CTL_191_160", 0x9104, 0 },
23222 	{ "MPS_VF_TX_CTL_223_192", 0x9108, 0 },
23223 	{ "MPS_VF_TX_CTL_255_224", 0x910c, 0 },
23224 	{ "MPS_VF_RX_CTL_31_0", 0x9020, 0 },
23225 	{ "MPS_VF_RX_CTL_63_32", 0x9024, 0 },
23226 	{ "MPS_VF_RX_CTL_95_64", 0x9028, 0 },
23227 	{ "MPS_VF_RX_CTL_127_96", 0x902c, 0 },
23228 	{ "MPS_VF_RX_CTL_159_128", 0x9110, 0 },
23229 	{ "MPS_VF_RX_CTL_191_160", 0x9114, 0 },
23230 	{ "MPS_VF_RX_CTL_223_192", 0x9118, 0 },
23231 	{ "MPS_VF_RX_CTL_255_224", 0x911c, 0 },
23232 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 },
23233 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 },
23234 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 },
23235 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 },
23236 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 },
23237 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 },
23238 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 },
23239 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 },
23240 	{ "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 },
23241 	{ "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 },
23242 	{ "MPS_WOL_CTL_MODE", 0x9058, 0 },
23243 	{ "MPS_FPGA_DEBUG", 0x9060, 0 },
23247 		{ "CH_MAP0", 0, 2 },
23248 	{ "MPS_DEBUG_CTL", 0x9068, 0 },
23252 		{ "DbgSel_L", 0, 5 },
23253 	{ "MPS_DEBUG_DATA_REG_L", 0x906c, 0 },
23254 	{ "MPS_DEBUG_DATA_REG_H", 0x9070, 0 },
23255 	{ "MPS_TOP_SPARE", 0x9074, 0 },
23264 		{ "oVlanSelMac0", 0, 1 },
23265 	{ "MPS_BUILD_REVISION", 0x9078, 0 },
23266 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH0", 0x907c, 0 },
23267 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH1", 0x9080, 0 },
23268 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH2", 0x9084, 0 },
23269 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH3", 0x9088, 0 },
23270 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH4", 0x908c, 0 },
23271 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH5", 0x9090, 0 },
23272 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH6", 0x9094, 0 },
23273 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH7", 0x9098, 0 },
23274 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH8", 0x909c, 0 },
23275 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH9", 0x90a0, 0 },
23276 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH10", 0x90a4, 0 },
23277 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH11", 0x90a8, 0 },
23278 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH12", 0x90ac, 0 },
23279 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH13", 0x90b0, 0 },
23280 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH14", 0x90b4, 0 },
23281 	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH15", 0x90b8, 0 },
23282 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0", 0x90bc, 0 },
23283 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1", 0x90c0, 0 },
23284 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2", 0x90c4, 0 },
23285 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3", 0x90c8, 0 },
23286 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4", 0x90cc, 0 },
23287 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5", 0x90d0, 0 },
23288 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6", 0x90d4, 0 },
23289 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7", 0x90d8, 0 },
23290 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8", 0x90dc, 0 },
23291 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9", 0x90e0, 0 },
23292 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10", 0x90e4, 0 },
23293 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11", 0x90e8, 0 },
23294 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12", 0x90ec, 0 },
23295 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13", 0x90f0, 0 },
23296 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14", 0x90f4, 0 },
23297 	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15", 0x90f8, 0 },
23298 	{ "MPS_FPGA_BIST_CFG_P0", 0x9120, 0 },
23300 		{ "BaseAddr", 0, 16 },
23301 	{ "MPS_FPGA_BIST_CFG_P1", 0x9124, 0 },
23303 		{ "BaseAddr", 0, 16 },
23304 	{ "MPS_PORT_CTL", 0x30000, 0 },
23312 	{ "MPS_PORT_PAUSE_CTL", 0x30004, 0 },
23313 	{ "MPS_PORT_TX_PAUSE_CTL", 0x30008, 0 },
23317 		{ "RxSendEn", 0, 8 },
23318 	{ "MPS_PORT_TX_PAUSE_CTL2", 0x3000c, 0 },
23319 	{ "MPS_PORT_RX_PAUSE_CTL", 0x30010, 0 },
23321 		{ "RxHaltEn", 0, 8 },
23322 	{ "MPS_PORT_TX_PAUSE_STATUS", 0x30014, 0 },
23325 		{ "RxSending", 0, 8 },
23326 	{ "MPS_PORT_RX_PAUSE_STATUS", 0x30018, 0 },
23328 		{ "RxHalted", 0, 8 },
23329 	{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3001c, 0 },
23330 	{ "MPS_PORT_TX_PAUSE_DEST_H", 0x30020, 0 },
23331 	{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x30024, 0 },
23332 	{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x30028, 0 },
23333 	{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3002c, 0 },
23341 		{ "Prty0", 0, 2 },
23342 	{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x30030, 0 },
23350 		{ "Prty0", 0, 4 },
23351 	{ "MPS_PORT_CTL", 0x34000, 0 },
23359 	{ "MPS_PORT_PAUSE_CTL", 0x34004, 0 },
23360 	{ "MPS_PORT_TX_PAUSE_CTL", 0x34008, 0 },
23364 		{ "RxSendEn", 0, 8 },
23365 	{ "MPS_PORT_TX_PAUSE_CTL2", 0x3400c, 0 },
23366 	{ "MPS_PORT_RX_PAUSE_CTL", 0x34010, 0 },
23368 		{ "RxHaltEn", 0, 8 },
23369 	{ "MPS_PORT_TX_PAUSE_STATUS", 0x34014, 0 },
23372 		{ "RxSending", 0, 8 },
23373 	{ "MPS_PORT_RX_PAUSE_STATUS", 0x34018, 0 },
23375 		{ "RxHalted", 0, 8 },
23376 	{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3401c, 0 },
23377 	{ "MPS_PORT_TX_PAUSE_DEST_H", 0x34020, 0 },
23378 	{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x34024, 0 },
23379 	{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x34028, 0 },
23380 	{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3402c, 0 },
23388 		{ "Prty0", 0, 2 },
23389 	{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x34030, 0 },
23397 		{ "Prty0", 0, 4 },
23398 	{ "MPS_PF_CTL", 0x1e2c0, 0 },
23400 		{ "RxEn", 0, 1 },
23401 	{ "MPS_PF_CTL", 0x1e6c0, 0 },
23403 		{ "RxEn", 0, 1 },
23404 	{ "MPS_PF_CTL", 0x1eac0, 0 },
23406 		{ "RxEn", 0, 1 },
23407 	{ "MPS_PF_CTL", 0x1eec0, 0 },
23409 		{ "RxEn", 0, 1 },
23410 	{ "MPS_PF_CTL", 0x1f2c0, 0 },
23412 		{ "RxEn", 0, 1 },
23413 	{ "MPS_PF_CTL", 0x1f6c0, 0 },
23415 		{ "RxEn", 0, 1 },
23416 	{ "MPS_PF_CTL", 0x1fac0, 0 },
23418 		{ "RxEn", 0, 1 },
23419 	{ "MPS_PF_CTL", 0x1fec0, 0 },
23421 		{ "RxEn", 0, 1 },
23422 	{ "MPS_RX_CTL", 0x11000, 0 },
23427 		{ "SNF", 0, 8 },
23428 	{ "MPS_RX_PORT_MUX_CTL", 0x11004, 0 },
23430 		{ "CTL_P0", 0, 4 },
23431 	{ "MPS_RX_FIFO_0_CTL", 0x11008, 0 },
23432 	{ "MPS_RX_FIFO_1_CTL", 0x1100c, 0 },
23433 	{ "MPS_RX_FIFO_2_CTL", 0x11010, 0 },
23434 	{ "MPS_RX_FIFO_3_CTL", 0x11014, 0 },
23435 	{ "MPS_RX_PG_HYST_BG0", 0x11048, 0 },
23437 		{ "TH", 0, 11 },
23438 	{ "MPS_RX_PG_HYST_BG1", 0x1104c, 0 },
23440 		{ "TH", 0, 11 },
23441 	{ "MPS_RX_PG_HYST_BG2", 0x11050, 0 },
23443 		{ "TH", 0, 11 },
23444 	{ "MPS_RX_PG_HYST_BG3", 0x11054, 0 },
23446 		{ "TH", 0, 11 },
23447 	{ "MPS_RX_OCH_CTL", 0x11058, 0 },
23452 		{ "STOP", 0, 5 },
23453 	{ "MPS_RX_LPBK_BP0", 0x1105c, 0 },
23454 	{ "MPS_RX_LPBK_BP1", 0x11060, 0 },
23455 	{ "MPS_RX_LPBK_BP2", 0x11064, 0 },
23456 	{ "MPS_RX_LPBK_BP3", 0x11068, 0 },
23457 	{ "MPS_RX_PORT_GAP", 0x1106c, 0 },
23458 	{ "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
23465 	{ "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
23472 	{ "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
23479 	{ "MPS_RX_PERR_INJECT", 0x11080, 0 },
23481 		{ "InjectDataErr", 0, 1 },
23482 	{ "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
23498 		{ "PG_TH_INT0", 0, 1 },
23499 	{ "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
23515 		{ "PG_TH_INT0", 0, 1 },
23516 	{ "MPS_RX_REPL_CTL", 0x11098, 0 },
23517 	{ "MPS_RX_PPP_ATRB", 0x1109c, 0 },
23519 		{ "OPCODE", 0, 16 },
23520 	{ "MPS_RX_QFC0_ATRB", 0x110a0, 0 },
23522 		{ "DA", 0, 16 },
23523 	{ "MPS_RX_QFC1_ATRB", 0x110a4, 0 },
23524 	{ "MPS_RX_PT_ARB0", 0x110a8, 0 },
23526 		{ "MAC_WT", 0, 14 },
23527 	{ "MPS_RX_PT_ARB1", 0x110ac, 0 },
23529 		{ "MAC_WT", 0, 14 },
23530 	{ "MPS_RX_PT_ARB2", 0x110b0, 0 },
23532 		{ "MAC_WT", 0, 14 },
23533 	{ "MPS_PF_OUT_EN", 0x110b4, 0 },
23534 	{ "MPS_BMC_MTU", 0x110b8, 0 },
23535 	{ "MPS_BMC_PKT_CNT", 0x110bc, 0 },
23536 	{ "MPS_BMC_BYTE_CNT", 0x110c0, 0 },
23537 	{ "MPS_PFVF_ATRB_CTL", 0x110c4, 0 },
23539 		{ "PFVF", 0, 9 },
23540 	{ "MPS_PFVF_ATRB", 0x110c8, 0 },
23546 		{ "MTU", 0, 14 },
23547 	{ "MPS_PFVF_ATRB_FLTR0", 0x110cc, 0 },
23549 		{ "VLAN_ID", 0, 12 },
23550 	{ "MPS_PFVF_ATRB_FLTR1", 0x110d0, 0 },
23552 		{ "VLAN_ID", 0, 12 },
23553 	{ "MPS_PFVF_ATRB_FLTR2", 0x110d4, 0 },
23555 		{ "VLAN_ID", 0, 12 },
23556 	{ "MPS_PFVF_ATRB_FLTR3", 0x110d8, 0 },
23558 		{ "VLAN_ID", 0, 12 },
23559 	{ "MPS_PFVF_ATRB_FLTR4", 0x110dc, 0 },
23561 		{ "VLAN_ID", 0, 12 },
23562 	{ "MPS_PFVF_ATRB_FLTR5", 0x110e0, 0 },
23564 		{ "VLAN_ID", 0, 12 },
23565 	{ "MPS_PFVF_ATRB_FLTR6", 0x110e4, 0 },
23567 		{ "VLAN_ID", 0, 12 },
23568 	{ "MPS_PFVF_ATRB_FLTR7", 0x110e8, 0 },
23570 		{ "VLAN_ID", 0, 12 },
23571 	{ "MPS_PFVF_ATRB_FLTR8", 0x110ec, 0 },
23573 		{ "VLAN_ID", 0, 12 },
23574 	{ "MPS_PFVF_ATRB_FLTR9", 0x110f0, 0 },
23576 		{ "VLAN_ID", 0, 12 },
23577 	{ "MPS_PFVF_ATRB_FLTR10", 0x110f4, 0 },
23579 		{ "VLAN_ID", 0, 12 },
23580 	{ "MPS_PFVF_ATRB_FLTR11", 0x110f8, 0 },
23582 		{ "VLAN_ID", 0, 12 },
23583 	{ "MPS_PFVF_ATRB_FLTR12", 0x110fc, 0 },
23585 		{ "VLAN_ID", 0, 12 },
23586 	{ "MPS_PFVF_ATRB_FLTR13", 0x11100, 0 },
23588 		{ "VLAN_ID", 0, 12 },
23589 	{ "MPS_PFVF_ATRB_FLTR14", 0x11104, 0 },
23591 		{ "VLAN_ID", 0, 12 },
23592 	{ "MPS_PFVF_ATRB_FLTR15", 0x11108, 0 },
23594 		{ "VLAN_ID", 0, 12 },
23595 	{ "MPS_RPLC_MAP_CTL", 0x1110c, 0 },
23597 		{ "ADDR", 0, 10 },
23598 	{ "MPS_PF_RPLCT_MAP", 0x11110, 0 },
23599 	{ "MPS_VF_RPLCT_MAP0", 0x11114, 0 },
23600 	{ "MPS_VF_RPLCT_MAP1", 0x11118, 0 },
23601 	{ "MPS_VF_RPLCT_MAP2", 0x1111c, 0 },
23602 	{ "MPS_VF_RPLCT_MAP3", 0x11120, 0 },
23603 	{ "MPS_VF_RPLCT_MAP4", 0x11300, 0 },
23604 	{ "MPS_VF_RPLCT_MAP5", 0x11304, 0 },
23605 	{ "MPS_VF_RPLCT_MAP6", 0x11308, 0 },
23606 	{ "MPS_VF_RPLCT_MAP7", 0x1130c, 0 },
23607 	{ "MPS_MEM_DBG_CTL", 0x1112c, 0 },
23610 		{ "ADDR", 0, 16 },
23611 	{ "MPS_PKD_MEM_DATA0", 0x11130, 0 },
23612 	{ "MPS_PKD_MEM_DATA1", 0x11134, 0 },
23613 	{ "MPS_PKD_MEM_DATA2", 0x11138, 0 },
23614 	{ "MPS_PGD_MEM_DATA", 0x1113c, 0 },
23615 	{ "MPS_RX_SE_CNT_ERR", 0x11140, 0 },
23616 	{ "MPS_RX_SE_CNT_CLR", 0x11144, 0 },
23617 	{ "MPS_RX_SE_CNT_IN0", 0x11148, 0 },
23621 		{ "EOP_CNT_IN", 0, 8 },
23622 	{ "MPS_RX_SE_CNT_IN1", 0x1114c, 0 },
23626 		{ "EOP_CNT_IN", 0, 8 },
23627 	{ "MPS_RX_SE_CNT_IN2", 0x11150, 0 },
23631 		{ "EOP_CNT_IN", 0, 8 },
23632 	{ "MPS_RX_SE_CNT_IN3", 0x11154, 0 },
23636 		{ "EOP_CNT_IN", 0, 8 },
23637 	{ "MPS_RX_SE_CNT_IN4", 0x11158, 0 },
23641 		{ "EOP_CNT_IN", 0, 8 },
23642 	{ "MPS_RX_SE_CNT_IN5", 0x1115c, 0 },
23646 		{ "EOP_CNT_IN", 0, 8 },
23647 	{ "MPS_RX_SE_CNT_IN6", 0x11160, 0 },
23651 		{ "EOP_CNT_IN", 0, 8 },
23652 	{ "MPS_RX_SE_CNT_IN7", 0x11164, 0 },
23656 		{ "EOP_CNT_IN", 0, 8 },
23657 	{ "MPS_RX_SE_CNT_OUT01", 0x11168, 0 },
23661 		{ "EOP_CNT_0", 0, 8 },
23662 	{ "MPS_RX_SE_CNT_OUT23", 0x1116c, 0 },
23666 		{ "EOP_CNT_2", 0, 8 },
23667 	{ "MPS_RX_SPI_ERR", 0x11170, 0 },
23669 		{ "ERR", 0, 21 },
23670 	{ "MPS_RX_IN_BUS_STATE", 0x11174, 0 },
23674 		{ "ST0", 0, 8 },
23675 	{ "MPS_RX_OUT_BUS_STATE", 0x11178, 0 },
23677 		{ "ST_TP", 0, 23 },
23678 	{ "MPS_RX_DBG_CTL", 0x1117c, 0 },
23683 		{ "IN_DBG_CHNL", 0, 3 },
23684 	{ "MPS_RX_SPARE", 0x11190, 0 },
23685 	{ "MPS_RX_PTP_ETYPE", 0x11194, 0 },
23687 		{ "PETYPE1", 0, 16 },
23688 	{ "MPS_RX_PTP_TCP", 0x11198, 0 },
23690 		{ "PTCPORT1", 0, 16 },
23691 	{ "MPS_RX_PTP_UDP", 0x1119c, 0 },
23693 		{ "PUDPORT1", 0, 16 },
23694 	{ "MPS_RX_PTP_CTL", 0x111a0, 0 },
23701 		{ "PETYPE1EN", 0, 4 },
23702 	{ "MPS_RX_PAUSE_GEN_TH_0_0", 0x111a4, 0 },
23704 		{ "TH_LOW", 0, 16 },
23705 	{ "MPS_RX_PAUSE_GEN_TH_0_1", 0x111a8, 0 },
23707 		{ "TH_LOW", 0, 16 },
23708 	{ "MPS_RX_PAUSE_GEN_TH_0_2", 0x111ac, 0 },
23710 		{ "TH_LOW", 0, 16 },
23711 	{ "MPS_RX_PAUSE_GEN_TH_0_3", 0x111b0, 0 },
23713 		{ "TH_LOW", 0, 16 },
23714 	{ "MPS_RX_PAUSE_GEN_TH_1_0", 0x111b4, 0 },
23716 		{ "TH_LOW", 0, 16 },
23717 	{ "MPS_RX_PAUSE_GEN_TH_1_1", 0x111b8, 0 },
23719 		{ "TH_LOW", 0, 16 },
23720 	{ "MPS_RX_PAUSE_GEN_TH_1_2", 0x111bc, 0 },
23722 		{ "TH_LOW", 0, 16 },
23723 	{ "MPS_RX_PAUSE_GEN_TH_1_3", 0x111c0, 0 },
23725 		{ "TH_LOW", 0, 16 },
23726 	{ "MPS_RX_PAUSE_GEN_TH_2_0", 0x111c4, 0 },
23728 		{ "TH_LOW", 0, 16 },
23729 	{ "MPS_RX_PAUSE_GEN_TH_2_1", 0x111c8, 0 },
23731 		{ "TH_LOW", 0, 16 },
23732 	{ "MPS_RX_PAUSE_GEN_TH_2_2", 0x111cc, 0 },
23734 		{ "TH_LOW", 0, 16 },
23735 	{ "MPS_RX_PAUSE_GEN_TH_2_3", 0x111d0, 0 },
23737 		{ "TH_LOW", 0, 16 },
23738 	{ "MPS_RX_PAUSE_GEN_TH_3_0", 0x111d4, 0 },
23740 		{ "TH_LOW", 0, 16 },
23741 	{ "MPS_RX_PAUSE_GEN_TH_3_1", 0x111d8, 0 },
23743 		{ "TH_LOW", 0, 16 },
23744 	{ "MPS_RX_PAUSE_GEN_TH_3_2", 0x111dc, 0 },
23746 		{ "TH_LOW", 0, 16 },
23747 	{ "MPS_RX_PAUSE_GEN_TH_3_3", 0x111e0, 0 },
23749 		{ "TH_LOW", 0, 16 },
23750 	{ "MPS_RX_MAC_CLS_DROP_CNT0", 0x111e4, 0 },
23751 	{ "MPS_RX_MAC_CLS_DROP_CNT1", 0x111e8, 0 },
23752 	{ "MPS_RX_MAC_CLS_DROP_CNT2", 0x111ec, 0 },
23753 	{ "MPS_RX_MAC_CLS_DROP_CNT3", 0x111f0, 0 },
23754 	{ "MPS_RX_LPBK_CLS_DROP_CNT0", 0x111f4, 0 },
23755 	{ "MPS_RX_LPBK_CLS_DROP_CNT1", 0x111f8, 0 },
23756 	{ "MPS_RX_LPBK_CLS_DROP_CNT2", 0x111fc, 0 },
23757 	{ "MPS_RX_LPBK_CLS_DROP_CNT3", 0x11200, 0 },
23758 	{ "MPS_RX_CGEN", 0x11204, 0 },
23762 		{ "MPS_RX_CGEN_MAC_IN", 0, 4 },
23763 	{ "MPS_RX_MAC_BG_PG_CNT0", 0x11208, 0 },
23765 		{ "MAC_ALLOC", 0, 11 },
23766 	{ "MPS_RX_MAC_BG_PG_CNT1", 0x1120c, 0 },
23768 		{ "MAC_ALLOC", 0, 11 },
23769 	{ "MPS_RX_MAC_BG_PG_CNT2", 0x11210, 0 },
23771 		{ "MAC_ALLOC", 0, 11 },
23772 	{ "MPS_RX_MAC_BG_PG_CNT3", 0x11214, 0 },
23774 		{ "MAC_ALLOC", 0, 11 },
23775 	{ "MPS_RX_LPBK_BG_PG_CNT0", 0x11218, 0 },
23777 		{ "LPBK_ALLOC", 0, 11 },
23778 	{ "MPS_RX_LPBK_BG_PG_CNT1", 0x1121c, 0 },
23780 		{ "LPBK_ALLOC", 0, 11 },
23781 	{ "MPS_RX_CONGESTION_THRESHOLD_BG0", 0x11220, 0 },
23783 		{ "CONG_TH", 0, 20 },
23784 	{ "MPS_RX_CONGESTION_THRESHOLD_BG1", 0x11224, 0 },
23786 		{ "CONG_TH", 0, 20 },
23787 	{ "MPS_RX_CONGESTION_THRESHOLD_BG2", 0x11228, 0 },
23789 		{ "CONG_TH", 0, 20 },
23790 	{ "MPS_RX_CONGESTION_THRESHOLD_BG3", 0x1122c, 0 },
23792 		{ "CONG_TH", 0, 20 },
23793 	{ "MPS_RX_GRE_PROT_TYPE", 0x11230, 0 },
23796 		{ "GRE", 0, 8 },
23797 	{ "MPS_RX_VXLAN_TYPE", 0x11234, 0 },
23799 		{ "VXLAN", 0, 16 },
23800 	{ "MPS_RX_GENEVE_TYPE", 0x11238, 0 },
23802 		{ "GENEVE", 0, 16 },
23803 	{ "MPS_RX_INNER_HDR_IVLAN", 0x1123c, 0 },
23805 		{ "IVLAN_ETYPE", 0, 16 },
23806 	{ "MPS_RX_ENCAP_NVGRE", 0x11240, 0 },
23808 		{ "ETYPE", 0, 16 },
23809 	{ "MPS_RX_ENCAP_GENEVE", 0x11244, 0 },
23811 		{ "ETYPE", 0, 16 },
23812 	{ "MPS_RX_TCP", 0x11248, 0 },
23814 		{ "PROT_TYPE", 0, 8 },
23815 	{ "MPS_RX_UDP", 0x1124c, 0 },
23817 		{ "PROT_TYPE", 0, 8 },
23818 	{ "MPS_RX_PAUSE", 0x11250, 0 },
23819 	{ "MPS_RX_LENGTH", 0x11254, 0 },
23821 		{ "LENGTH_ETYPE", 0, 16 },
23822 	{ "MPS_RX_CTL_ORG", 0x11258, 0 },
23824 		{ "ORG_VALUE", 0, 24 },
23825 	{ "MPS_RX_IPV4", 0x1125c, 0 },
23826 	{ "MPS_RX_IPV6", 0x11260, 0 },
23827 	{ "MPS_RX_TTL", 0x11264, 0 },
23831 		{ "TTL_CHK_EN_IPV6", 0, 1 },
23832 	{ "MPS_RX_DEFAULT_VNI", 0x11268, 0 },
23833 	{ "MPS_RX_PRS_CTL", 0x1126c, 0 },
23845 	{ "MPS_RX_PRS_CTL_2", 0x11270, 0 },
23850 		{ "IPV6_UDP_CSUM_COMPAT", 0, 1 },
23851 	{ "MPS_RX_MPS2NCSI_CNT", 0x11274, 0 },
23852 	{ "MPS_RX_MAX_TNL_HDR_LEN", 0x11278, 0 },
23853 	{ "MPS_RX_PAUSE_DA_H", 0x1127c, 0 },
23854 	{ "MPS_RX_PAUSE_DA_L", 0x11280, 0 },
23855 	{ "MPS_RX_CNT_NVGRE_PKT_MAC0", 0x11284, 0 },
23856 	{ "MPS_RX_CNT_VXLAN_PKT_MAC0", 0x11288, 0 },
23857 	{ "MPS_RX_CNT_GENEVE_PKT_MAC0", 0x1128c, 0 },
23858 	{ "MPS_RX_CNT_TNL_ERR_PKT_MAC0", 0x11290, 0 },
23859 	{ "MPS_RX_CNT_NVGRE_PKT_MAC1", 0x11294, 0 },
23860 	{ "MPS_RX_CNT_VXLAN_PKT_MAC1", 0x11298, 0 },
23861 	{ "MPS_RX_CNT_GENEVE_PKT_MAC1", 0x1129c, 0 },
23862 	{ "MPS_RX_CNT_TNL_ERR_PKT_MAC1", 0x112a0, 0 },
23863 	{ "MPS_RX_CNT_NVGRE_PKT_LPBK0", 0x112a4, 0 },
23864 	{ "MPS_RX_CNT_VXLAN_PKT_LPBK0", 0x112a8, 0 },
23865 	{ "MPS_RX_CNT_GENEVE_PKT_LPBK0", 0x112ac, 0 },
23866 	{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK0", 0x112b0, 0 },
23867 	{ "MPS_RX_CNT_NVGRE_PKT_LPBK1", 0x112b4, 0 },
23868 	{ "MPS_RX_CNT_VXLAN_PKT_LPBK1", 0x112b8, 0 },
23869 	{ "MPS_RX_CNT_GENEVE_PKT_LPBK1", 0x112bc, 0 },
23870 	{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK1", 0x112c0, 0 },
23871 	{ "MPS_RX_CNT_NVGRE_PKT_TO_TP0", 0x112c4, 0 },
23872 	{ "MPS_RX_CNT_VXLAN_PKT_TO_TP0", 0x112c8, 0 },
23873 	{ "MPS_RX_CNT_GENEVE_PKT_TO_TP0", 0x112cc, 0 },
23874 	{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP0", 0x112d0, 0 },
23875 	{ "MPS_RX_CNT_NVGRE_PKT_TO_TP1", 0x112d4, 0 },
23876 	{ "MPS_RX_CNT_VXLAN_PKT_TO_TP1", 0x112d8, 0 },
23877 	{ "MPS_RX_CNT_GENEVE_PKT_TO_TP1", 0x112dc, 0 },
23878 	{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP1", 0x112e0, 0 },
23879 	{ "MPS_PORT_RX_CTL", 0x30100, 0 },
23904 		{ "OVLAN_EN0", 0, 1 },
23905 	{ "MPS_PORT_RX_MTU", 0x30104, 0 },
23906 	{ "MPS_PORT_RX_PF_MAP", 0x30108, 0 },
23907 	{ "MPS_PORT_RX_VF_MAP0", 0x3010c, 0 },
23908 	{ "MPS_PORT_RX_VF_MAP1", 0x30110, 0 },
23909 	{ "MPS_PORT_RX_VF_MAP2", 0x30114, 0 },
23910 	{ "MPS_PORT_RX_VF_MAP3", 0x30118, 0 },
23911 	{ "MPS_PORT_RX_VF_MAP4", 0x30150, 0 },
23912 	{ "MPS_PORT_RX_VF_MAP5", 0x30154, 0 },
23913 	{ "MPS_PORT_RX_VF_MAP6", 0x30158, 0 },
23914 	{ "MPS_PORT_RX_VF_MAP7", 0x3015c, 0 },
23915 	{ "MPS_PORT_RX_IVLAN", 0x3011c, 0 },
23916 	{ "MPS_PORT_RX_OVLAN0", 0x30120, 0 },
23918 		{ "OVLAN_ETYPE", 0, 16 },
23919 	{ "MPS_PORT_RX_OVLAN1", 0x30124, 0 },
23921 		{ "OVLAN_ETYPE", 0, 16 },
23922 	{ "MPS_PORT_RX_OVLAN2", 0x30128, 0 },
23924 		{ "OVLAN_ETYPE", 0, 16 },
23925 	{ "MPS_PORT_RX_OVLAN3", 0x3012c, 0 },
23927 		{ "OVLAN_ETYPE", 0, 16 },
23928 	{ "MPS_PORT_RX_RSS_HASH", 0x30130, 0 },
23929 	{ "MPS_PORT_RX_RSS_CONTROL", 0x30134, 0 },
23931 		{ "QUE_NUM", 0, 16 },
23932 	{ "MPS_PORT_RX_CTL1", 0x30138, 0 },
23938 		{ "FIXED_VF", 0, 8 },
23939 	{ "MPS_PORT_RX_SPARE", 0x3013c, 0 },
23940 	{ "MPS_PORT_RX_PTP_RSS_HASH", 0x30140, 0 },
23941 	{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x30144, 0 },
23943 		{ "QUE_NUM", 0, 16 },
23944 	{ "MPS_PORT_RX_TS_VLD", 0x30148, 0 },
23945 	{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3014c, 0 },
23946 	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x30160, 0 },
23972 	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x30164, 0 },
23997 	{ "MPS_PORT_RX_REPL_VECT_SEL", 0x30168, 0 },
23999 		{ "REPL_VECT_SEL", 0, 4 },
24000 	{ "MPS_PORT_RX_CTL", 0x34100, 0 },
24025 		{ "OVLAN_EN0", 0, 1 },
24026 	{ "MPS_PORT_RX_MTU", 0x34104, 0 },
24027 	{ "MPS_PORT_RX_PF_MAP", 0x34108, 0 },
24028 	{ "MPS_PORT_RX_VF_MAP0", 0x3410c, 0 },
24029 	{ "MPS_PORT_RX_VF_MAP1", 0x34110, 0 },
24030 	{ "MPS_PORT_RX_VF_MAP2", 0x34114, 0 },
24031 	{ "MPS_PORT_RX_VF_MAP3", 0x34118, 0 },
24032 	{ "MPS_PORT_RX_VF_MAP4", 0x34150, 0 },
24033 	{ "MPS_PORT_RX_VF_MAP5", 0x34154, 0 },
24034 	{ "MPS_PORT_RX_VF_MAP6", 0x34158, 0 },
24035 	{ "MPS_PORT_RX_VF_MAP7", 0x3415c, 0 },
24036 	{ "MPS_PORT_RX_IVLAN", 0x3411c, 0 },
24037 	{ "MPS_PORT_RX_OVLAN0", 0x34120, 0 },
24039 		{ "OVLAN_ETYPE", 0, 16 },
24040 	{ "MPS_PORT_RX_OVLAN1", 0x34124, 0 },
24042 		{ "OVLAN_ETYPE", 0, 16 },
24043 	{ "MPS_PORT_RX_OVLAN2", 0x34128, 0 },
24045 		{ "OVLAN_ETYPE", 0, 16 },
24046 	{ "MPS_PORT_RX_OVLAN3", 0x3412c, 0 },
24048 		{ "OVLAN_ETYPE", 0, 16 },
24049 	{ "MPS_PORT_RX_RSS_HASH", 0x34130, 0 },
24050 	{ "MPS_PORT_RX_RSS_CONTROL", 0x34134, 0 },
24052 		{ "QUE_NUM", 0, 16 },
24053 	{ "MPS_PORT_RX_CTL1", 0x34138, 0 },
24059 		{ "FIXED_VF", 0, 8 },
24060 	{ "MPS_PORT_RX_SPARE", 0x3413c, 0 },
24061 	{ "MPS_PORT_RX_PTP_RSS_HASH", 0x34140, 0 },
24062 	{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x34144, 0 },
24064 		{ "QUE_NUM", 0, 16 },
24065 	{ "MPS_PORT_RX_TS_VLD", 0x34148, 0 },
24066 	{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3414c, 0 },
24067 	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x34160, 0 },
24093 	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x34164, 0 },
24118 	{ "MPS_PORT_RX_REPL_VECT_SEL", 0x34168, 0 },
24120 		{ "REPL_VECT_SEL", 0, 4 },
24121 	{ "MPS_TX_PRTY_SEL", 0x9400, 0 },
24126 		{ "NCSI_Source", 0, 2 },
24127 	{ "MPS_TX_INT_ENABLE", 0x9404, 0 },
24135 		{ "TP", 0, 4 },
24136 	{ "MPS_TX_INT_CAUSE", 0x9408, 0 },
24144 		{ "TP", 0, 4 },
24145 	{ "MPS_TX_NCSI2MPS_CNT", 0x940c, 0 },
24146 	{ "MPS_TX_PERR_ENABLE", 0x9410, 0 },
24150 		{ "TP", 0, 4 },
24151 	{ "MPS_TX_PERR_INJECT", 0x9414, 0 },
24153 		{ "InjectDataErr", 0, 1 },
24154 	{ "MPS_TX_SE_CNT_TP01", 0x9418, 0 },
24158 		{ "EOP_CNT_0", 0, 8 },
24159 	{ "MPS_TX_SE_CNT_TP23", 0x941c, 0 },
24163 		{ "EOP_CNT_2", 0, 8 },
24164 	{ "MPS_TX_SE_CNT_MAC01", 0x9420, 0 },
24168 		{ "EOP_CNT_0", 0, 8 },
24169 	{ "MPS_TX_SE_CNT_MAC23", 0x9424, 0 },
24173 		{ "EOP_CNT_2", 0, 8 },
24174 	{ "MPS_TX_SECNT_SPI_BUBBLE_ERR", 0x9428, 0 },
24177 		{ "SeCnt", 0, 8 },
24178 	{ "MPS_TX_SECNT_BUBBLE_CLR", 0x942c, 0 },
24182 		{ "SeCnt", 0, 8 },
24183 	{ "MPS_TX_PORT_ERR", 0x9430, 0 },
24191 		{ "pt0", 0, 1 },
24192 	{ "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 },
24194 		{ "DropEn", 0, 1 },
24195 	{ "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 },
24197 		{ "DropEn", 0, 1 },
24198 	{ "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 },
24200 		{ "DropEn", 0, 1 },
24201 	{ "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 },
24203 		{ "DropEn", 0, 1 },
24204 	{ "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 },
24218 		{ "DataCh0", 0, 8 },
24219 	{ "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 },
24233 		{ "DataCh2", 0, 8 },
24234 	{ "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 },
24248 		{ "DataPt0", 0, 8 },
24249 	{ "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 },
24263 		{ "DataPt2", 0, 8 },
24264 	{ "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
24265 	{ "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 },
24269 		{ "PortL", 0, 3 },
24270 	{ "MPS_TX_PAD_CTL", 0x945c, 0 },
24278 		{ "MacPadEnPt0", 0, 1 },
24279 	{ "MPS_TX_PFVF_PORT_DROP_TP", 0x9460, 0 },
24281 		{ "TP2MPS_Ch0", 0, 8 },
24282 	{ "MPS_TX_PFVF_PORT_DROP_NCSI", 0x9464, 0 },
24283 	{ "MPS_TX_PFVF_PORT_DROP_CTL", 0x9468, 0 },
24287 		{ "TP2MPS_Ch0_CLR", 0, 1 },
24288 	{ "MPS_TX_CGEN", 0x946c, 0 },
24310 	{ "MPS_TX_CGEN_DYNAMIC", 0x9470, 0 },
24332 	{ "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 },
24336 		{ "Tag", 0, 12 },
24337 	{ "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 },
24341 		{ "Tag", 0, 12 },
24342 	{ "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 },
24346 		{ "Tag", 0, 12 },
24347 	{ "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 },
24351 		{ "Tag", 0, 12 },
24352 	{ "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 },
24356 		{ "Tag", 0, 12 },
24357 	{ "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 },
24361 		{ "Tag", 0, 12 },
24362 	{ "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 },
24366 		{ "Tag", 0, 12 },
24367 	{ "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 },
24371 		{ "Tag", 0, 12 },
24372 	{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x30190, 0 },
24373 	{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x30194, 0 },
24374 	{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x30198, 0 },
24375 	{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3019c, 0 },
24376 	{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x301a0, 0 },
24377 	{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x301a8, 0 },
24378 	{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x301ac, 0 },
24379 	{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x301b0, 0 },
24380 	{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x301b4, 0 },
24381 	{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x301b8, 0 },
24382 	{ "MPS_PORT_TX_FIFO_CTL", 0x301c4, 0 },
24387 		{ "MaxPktCnt", 0, 4 },
24388 	{ "MPS_PORT_FPGA_PAUSE_CTL", 0x301c8, 0 },
24389 	{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x301d0, 0 },
24391 		{ "on_pending", 0, 8 },
24392 	{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x34190, 0 },
24393 	{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x34194, 0 },
24394 	{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x34198, 0 },
24395 	{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3419c, 0 },
24396 	{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x341a0, 0 },
24397 	{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x341a8, 0 },
24398 	{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x341ac, 0 },
24399 	{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x341b0, 0 },
24400 	{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x341b4, 0 },
24401 	{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x341b8, 0 },
24402 	{ "MPS_PORT_TX_FIFO_CTL", 0x341c4, 0 },
24407 		{ "MaxPktCnt", 0, 4 },
24408 	{ "MPS_PORT_FPGA_PAUSE_CTL", 0x341c8, 0 },
24409 	{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x341d0, 0 },
24411 		{ "on_pending", 0, 8 },
24412 	{ "MPS_TRC_CFG", 0x9800, 0 },
24418 		{ "TrcMultiFilter", 0, 1 },
24419 	{ "MPS_TRC_FILTER0_RSS_HASH", 0x9804, 0 },
24420 	{ "MPS_TRC_FILTER0_RSS_CONTROL", 0x9808, 0 },
24422 		{ "QueueNumber", 0, 16 },
24423 	{ "MPS_TRC_FILTER1_RSS_HASH", 0x9ff0, 0 },
24424 	{ "MPS_TRC_FILTER1_RSS_CONTROL", 0x9ff4, 0 },
24426 		{ "QueueNumber", 0, 16 },
24427 	{ "MPS_TRC_FILTER2_RSS_HASH", 0x9ff8, 0 },
24428 	{ "MPS_TRC_FILTER2_RSS_CONTROL", 0x9ffc, 0 },
24430 		{ "QueueNumber", 0, 16 },
24431 	{ "MPS_TRC_FILTER3_RSS_HASH", 0xa000, 0 },
24432 	{ "MPS_TRC_FILTER3_RSS_CONTROL", 0xa004, 0 },
24434 		{ "QueueNumber", 0, 16 },
24435 	{ "MPS_TRC_RSS_HASH", 0xa008, 0 },
24436 	{ "MPS_TRC_RSS_CONTROL", 0xa00c, 0 },
24438 		{ "QueueNumber", 0, 16 },
24439 	{ "MPS_TRC_VF_OFF_FILTER_0", 0xa010, 0 },
24448 		{ "VfFiltData", 0, 8 },
24449 	{ "MPS_TRC_VF_OFF_FILTER_1", 0xa014, 0 },
24458 		{ "VfFiltData", 0, 8 },
24459 	{ "MPS_TRC_VF_OFF_FILTER_2", 0xa018, 0 },
24468 		{ "VfFiltData", 0, 8 },
24469 	{ "MPS_TRC_VF_OFF_FILTER_3", 0xa01c, 0 },
24478 		{ "VfFiltData", 0, 8 },
24479 	{ "MPS_TRC_CGEN", 0xa020, 0 },
24480 	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9810, 0 },
24490 		{ "TfOffset", 0, 5 },
24491 	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9814, 0 },
24501 		{ "TfOffset", 0, 5 },
24502 	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9818, 0 },
24512 		{ "TfOffset", 0, 5 },
24513 	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x981c, 0 },
24523 		{ "TfOffset", 0, 5 },
24524 	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9820, 0 },
24526 		{ "TfCaptureMax", 0, 14 },
24527 	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9824, 0 },
24529 		{ "TfCaptureMax", 0, 14 },
24530 	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9828, 0 },
24532 		{ "TfCaptureMax", 0, 14 },
24533 	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x982c, 0 },
24535 		{ "TfCaptureMax", 0, 14 },
24536 	{ "MPS_TRC_FILTER_RUNT_CTL", 0x9830, 0 },
24537 	{ "MPS_TRC_FILTER_RUNT_CTL", 0x9834, 0 },
24538 	{ "MPS_TRC_FILTER_RUNT_CTL", 0x9838, 0 },
24539 	{ "MPS_TRC_FILTER_RUNT_CTL", 0x983c, 0 },
24540 	{ "MPS_TRC_FILTER_DROP", 0x9840, 0 },
24542 		{ "TfDropBufferCount", 0, 16 },
24543 	{ "MPS_TRC_FILTER_DROP", 0x9844, 0 },
24545 		{ "TfDropBufferCount", 0, 16 },
24546 	{ "MPS_TRC_FILTER_DROP", 0x9848, 0 },
24548 		{ "TfDropBufferCount", 0, 16 },
24549 	{ "MPS_TRC_FILTER_DROP", 0x984c, 0 },
24551 		{ "TfDropBufferCount", 0, 16 },
24552 	{ "MPS_TRC_PERR_INJECT", 0x9850, 0 },
24554 		{ "InjectDataErr", 0, 1 },
24555 	{ "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
24558 		{ "FiltMem", 0, 4 },
24559 	{ "MPS_TRC_INT_ENABLE", 0x9858, 0 },
24563 		{ "FiltMem", 0, 4 },
24564 	{ "MPS_TRC_INT_CAUSE", 0x985c, 0 },
24568 		{ "FiltMem", 0, 4 },
24569 	{ "MPS_TRC_TIMESTAMP_L", 0x9860, 0 },
24570 	{ "MPS_TRC_TIMESTAMP_H", 0x9864, 0 },
24571 	{ "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
24572 	{ "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 },
24573 	{ "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 },
24574 	{ "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 },
24575 	{ "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 },
24576 	{ "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 },
24577 	{ "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 },
24578 	{ "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 },
24579 	{ "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 },
24580 	{ "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 },
24581 	{ "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 },
24582 	{ "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 },
24583 	{ "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 },
24584 	{ "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 },
24585 	{ "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 },
24586 	{ "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 },
24587 	{ "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 },
24588 	{ "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 },
24589 	{ "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 },
24590 	{ "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 },
24591 	{ "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 },
24592 	{ "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 },
24593 	{ "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 },
24594 	{ "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 },
24595 	{ "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 },
24596 	{ "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 },
24597 	{ "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 },
24598 	{ "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 },
24599 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 },
24600 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 },
24601 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 },
24602 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 },
24603 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 },
24604 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 },
24605 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 },
24606 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 },
24607 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 },
24608 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 },
24609 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 },
24610 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 },
24611 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 },
24612 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 },
24613 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 },
24614 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 },
24615 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 },
24616 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 },
24617 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 },
24618 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 },
24619 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 },
24620 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 },
24621 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 },
24622 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 },
24623 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 },
24624 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 },
24625 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 },
24626 	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 },
24627 	{ "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 },
24628 	{ "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 },
24629 	{ "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 },
24630 	{ "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 },
24631 	{ "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 },
24632 	{ "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 },
24633 	{ "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 },
24634 	{ "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 },
24635 	{ "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 },
24636 	{ "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 },
24637 	{ "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 },
24638 	{ "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 },
24639 	{ "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 },
24640 	{ "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 },
24641 	{ "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 },
24642 	{ "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 },
24643 	{ "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 },
24644 	{ "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 },
24645 	{ "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 },
24646 	{ "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 },
24647 	{ "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 },
24648 	{ "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 },
24649 	{ "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 },
24650 	{ "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 },
24651 	{ "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 },
24652 	{ "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 },
24653 	{ "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 },
24654 	{ "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 },
24655 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 },
24656 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 },
24657 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 },
24658 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 },
24659 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 },
24660 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 },
24661 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 },
24662 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 },
24663 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 },
24664 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 },
24665 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 },
24666 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 },
24667 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 },
24668 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 },
24669 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 },
24670 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 },
24671 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 },
24672 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 },
24673 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 },
24674 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 },
24675 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 },
24676 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 },
24677 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 },
24678 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 },
24679 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 },
24680 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 },
24681 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 },
24682 	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 },
24683 	{ "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 },
24684 	{ "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 },
24685 	{ "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 },
24686 	{ "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 },
24687 	{ "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 },
24688 	{ "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 },
24689 	{ "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 },
24690 	{ "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 },
24691 	{ "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 },
24692 	{ "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 },
24693 	{ "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 },
24694 	{ "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 },
24695 	{ "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 },
24696 	{ "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 },
24697 	{ "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 },
24698 	{ "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 },
24699 	{ "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 },
24700 	{ "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 },
24701 	{ "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 },
24702 	{ "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 },
24703 	{ "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 },
24704 	{ "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 },
24705 	{ "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 },
24706 	{ "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 },
24707 	{ "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 },
24708 	{ "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 },
24709 	{ "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 },
24710 	{ "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 },
24711 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 },
24712 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 },
24713 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 },
24714 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 },
24715 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 },
24716 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 },
24717 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 },
24718 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 },
24719 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 },
24720 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 },
24721 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 },
24722 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 },
24723 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 },
24724 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 },
24725 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 },
24726 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 },
24727 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 },
24728 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 },
24729 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 },
24730 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 },
24731 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 },
24732 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 },
24733 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 },
24734 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 },
24735 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 },
24736 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 },
24737 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 },
24738 	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 },
24739 	{ "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 },
24740 	{ "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 },
24741 	{ "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 },
24742 	{ "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 },
24743 	{ "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 },
24744 	{ "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 },
24745 	{ "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 },
24746 	{ "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 },
24747 	{ "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 },
24748 	{ "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 },
24749 	{ "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 },
24750 	{ "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 },
24751 	{ "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 },
24752 	{ "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 },
24753 	{ "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 },
24754 	{ "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 },
24755 	{ "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 },
24756 	{ "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 },
24757 	{ "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 },
24758 	{ "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 },
24759 	{ "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 },
24760 	{ "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 },
24761 	{ "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 },
24762 	{ "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 },
24763 	{ "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 },
24764 	{ "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 },
24765 	{ "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 },
24766 	{ "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 },
24767 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 },
24768 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 },
24769 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 },
24770 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 },
24771 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 },
24772 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 },
24773 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 },
24774 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 },
24775 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 },
24776 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 },
24777 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 },
24778 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 },
24779 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 },
24780 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 },
24781 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 },
24782 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 },
24783 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 },
24784 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 },
24785 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 },
24786 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 },
24787 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 },
24788 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 },
24789 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 },
24790 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 },
24791 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 },
24792 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 },
24793 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 },
24794 	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 },
24795 	{ "MPS_STAT_CTL", 0x9600, 0 },
24806 		{ "LpbkErrStat", 0, 1 },
24807 	{ "MPS_STAT_INT_ENABLE", 0x9608, 0 },
24808 	{ "MPS_STAT_INT_CAUSE", 0x960c, 0 },
24809 	{ "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 },
24815 		{ "Txport", 0, 6 },
24816 	{ "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
24822 		{ "Txport", 0, 6 },
24823 	{ "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
24829 		{ "Txport", 0, 6 },
24830 	{ "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 },
24834 		{ "Drop", 0, 8 },
24835 	{ "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 },
24839 		{ "Drop", 0, 8 },
24840 	{ "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 },
24844 		{ "Drop", 0, 8 },
24845 	{ "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 },
24850 		{ "Mac", 0, 4 },
24851 	{ "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 },
24856 		{ "Mac", 0, 4 },
24857 	{ "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 },
24862 		{ "Mac", 0, 4 },
24863 	{ "MPS_STAT_PERR_INJECT", 0x9634, 0 },
24865 		{ "InjectDataErr", 0, 1 },
24866 	{ "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 },
24868 		{ "SubPrtL", 0, 5 },
24869 	{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 },
24870 	{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 },
24871 	{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 },
24872 	{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 },
24873 	{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 },
24874 	{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 },
24875 	{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 },
24876 	{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 },
24877 	{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 },
24878 	{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 },
24879 	{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 },
24880 	{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 },
24881 	{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 },
24882 	{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 },
24883 	{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 },
24884 	{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 },
24885 	{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 },
24886 	{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 },
24887 	{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 },
24888 	{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 },
24889 	{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 },
24890 	{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 },
24891 	{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 },
24892 	{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 },
24893 	{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 },
24894 	{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 },
24895 	{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 },
24896 	{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 },
24897 	{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 },
24898 	{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 },
24899 	{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
24900 	{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
24901 	{ "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
24903 		{ "Txvf", 0, 5 },
24904 	{ "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
24906 		{ "Txvf", 0, 5 },
24907 	{ "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
24909 		{ "Txvf", 0, 5 },
24910 	{ "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
24911 	{ "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
24914 		{ "PtRx", 0, 4 },
24915 	{ "MPS_STAT_STOP_UPD_PF", 0x96d4, 0 },
24917 		{ "PFRx", 0, 8 },
24918 	{ "MPS_STAT_STOP_UPD_TX_VF_0_31", 0x96d8, 0 },
24919 	{ "MPS_STAT_STOP_UPD_TX_VF_32_63", 0x96dc, 0 },
24920 	{ "MPS_STAT_STOP_UPD_TX_VF_64_95", 0x96e0, 0 },
24921 	{ "MPS_STAT_STOP_UPD_TX_VF_96_127", 0x96e4, 0 },
24922 	{ "MPS_STAT_STOP_UPD_TX_VF_128_159", 0x9710, 0 },
24923 	{ "MPS_STAT_STOP_UPD_TX_VF_160_191", 0x9714, 0 },
24924 	{ "MPS_STAT_STOP_UPD_TX_VF_192_223", 0x9718, 0 },
24925 	{ "MPS_STAT_STOP_UPD_TX_VF_224_255", 0x971c, 0 },
24926 	{ "MPS_STAT_STOP_UPD_RX_VF_0_31", 0x96e8, 0 },
24927 	{ "MPS_STAT_STOP_UPD_RX_VF_32_63", 0x96ec, 0 },
24928 	{ "MPS_STAT_STOP_UPD_RX_VF_64_95", 0x96f0, 0 },
24929 	{ "MPS_STAT_STOP_UPD_RX_VF_96_127", 0x96f4, 0 },
24930 	{ "MPS_STAT_STOP_UPD_RX_VF_128_159", 0x96f8, 0 },
24931 	{ "MPS_STAT_STOP_UPD_RX_VF_160_191", 0x96fc, 0 },
24932 	{ "MPS_STAT_STOP_UPD_RX_VF_192_223", 0x9700, 0 },
24933 	{ "MPS_STAT_STOP_UPD_RX_VF_224_255", 0x9704, 0 },
24934 	{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x30400, 0 },
24935 	{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x30404, 0 },
24936 	{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x30408, 0 },
24937 	{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3040c, 0 },
24938 	{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x30410, 0 },
24939 	{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x30414, 0 },
24940 	{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x30418, 0 },
24941 	{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3041c, 0 },
24942 	{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x30420, 0 },
24943 	{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x30424, 0 },
24944 	{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x30428, 0 },
24945 	{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3042c, 0 },
24946 	{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x30430, 0 },
24947 	{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x30434, 0 },
24948 	{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x30438, 0 },
24949 	{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3043c, 0 },
24950 	{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x30440, 0 },
24951 	{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x30444, 0 },
24952 	{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x30448, 0 },
24953 	{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3044c, 0 },
24954 	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x30450, 0 },
24955 	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x30454, 0 },
24956 	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x30458, 0 },
24957 	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3045c, 0 },
24958 	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x30460, 0 },
24959 	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x30464, 0 },
24960 	{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x30468, 0 },
24961 	{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3046c, 0 },
24962 	{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x30470, 0 },
24963 	{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x30474, 0 },
24964 	{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x30478, 0 },
24965 	{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3047c, 0 },
24966 	{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x30480, 0 },
24967 	{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x30484, 0 },
24968 	{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x30488, 0 },
24969 	{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3048c, 0 },
24970 	{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x30490, 0 },
24971 	{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x30494, 0 },
24972 	{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x30498, 0 },
24973 	{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3049c, 0 },
24974 	{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x304a0, 0 },
24975 	{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x304a4, 0 },
24976 	{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x304a8, 0 },
24977 	{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x304ac, 0 },
24978 	{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x304b0, 0 },
24979 	{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x304b4, 0 },
24980 	{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x304c0, 0 },
24981 	{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x304c4, 0 },
24982 	{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x304c8, 0 },
24983 	{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x304cc, 0 },
24984 	{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x304d0, 0 },
24985 	{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x304d4, 0 },
24986 	{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x304d8, 0 },
24987 	{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x304dc, 0 },
24988 	{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x304e0, 0 },
24989 	{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x304e4, 0 },
24990 	{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x304e8, 0 },
24991 	{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x304ec, 0 },
24992 	{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x304f0, 0 },
24993 	{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x304f4, 0 },
24994 	{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x304f8, 0 },
24995 	{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x304fc, 0 },
24996 	{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x30500, 0 },
24997 	{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x30504, 0 },
24998 	{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x30508, 0 },
24999 	{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3050c, 0 },
25000 	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x30510, 0 },
25001 	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x30514, 0 },
25002 	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x30518, 0 },
25003 	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3051c, 0 },
25004 	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x30520, 0 },
25005 	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x30524, 0 },
25006 	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x30528, 0 },
25007 	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3052c, 0 },
25008 	{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x30540, 0 },
25009 	{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x30544, 0 },
25010 	{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x30548, 0 },
25011 	{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3054c, 0 },
25012 	{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x30550, 0 },
25013 	{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x30554, 0 },
25014 	{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x30558, 0 },
25015 	{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3055c, 0 },
25016 	{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x30560, 0 },
25017 	{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x30564, 0 },
25018 	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x30568, 0 },
25019 	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3056c, 0 },
25020 	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x30570, 0 },
25021 	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x30574, 0 },
25022 	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x30578, 0 },
25023 	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3057c, 0 },
25024 	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x30580, 0 },
25025 	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x30584, 0 },
25026 	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x30588, 0 },
25027 	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3058c, 0 },
25028 	{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x30590, 0 },
25029 	{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x30594, 0 },
25030 	{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x30598, 0 },
25031 	{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3059c, 0 },
25032 	{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x305a0, 0 },
25033 	{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x305a4, 0 },
25034 	{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x305a8, 0 },
25035 	{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x305ac, 0 },
25036 	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x305b0, 0 },
25037 	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x305b4, 0 },
25038 	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x305b8, 0 },
25039 	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x305bc, 0 },
25040 	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x305c0, 0 },
25041 	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x305c4, 0 },
25042 	{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x305c8, 0 },
25043 	{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x305cc, 0 },
25044 	{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x305d0, 0 },
25045 	{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x305d4, 0 },
25046 	{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x305d8, 0 },
25047 	{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x305dc, 0 },
25048 	{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x305e0, 0 },
25049 	{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x305e4, 0 },
25050 	{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x305e8, 0 },
25051 	{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x305ec, 0 },
25052 	{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x305f0, 0 },
25053 	{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x305f4, 0 },
25054 	{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x305f8, 0 },
25055 	{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x305fc, 0 },
25056 	{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x30600, 0 },
25057 	{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x30604, 0 },
25058 	{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x30608, 0 },
25059 	{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3060c, 0 },
25060 	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x30610, 0 },
25061 	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x30614, 0 },
25062 	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x30618, 0 },
25063 	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3061c, 0 },
25064 	{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x34400, 0 },
25065 	{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x34404, 0 },
25066 	{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x34408, 0 },
25067 	{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3440c, 0 },
25068 	{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x34410, 0 },
25069 	{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x34414, 0 },
25070 	{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x34418, 0 },
25071 	{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3441c, 0 },
25072 	{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x34420, 0 },
25073 	{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x34424, 0 },
25074 	{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x34428, 0 },
25075 	{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3442c, 0 },
25076 	{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x34430, 0 },
25077 	{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x34434, 0 },
25078 	{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x34438, 0 },
25079 	{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3443c, 0 },
25080 	{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x34440, 0 },
25081 	{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x34444, 0 },
25082 	{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x34448, 0 },
25083 	{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3444c, 0 },
25084 	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x34450, 0 },
25085 	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x34454, 0 },
25086 	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x34458, 0 },
25087 	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3445c, 0 },
25088 	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x34460, 0 },
25089 	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x34464, 0 },
25090 	{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x34468, 0 },
25091 	{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3446c, 0 },
25092 	{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x34470, 0 },
25093 	{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x34474, 0 },
25094 	{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x34478, 0 },
25095 	{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3447c, 0 },
25096 	{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x34480, 0 },
25097 	{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x34484, 0 },
25098 	{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x34488, 0 },
25099 	{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3448c, 0 },
25100 	{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x34490, 0 },
25101 	{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x34494, 0 },
25102 	{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x34498, 0 },
25103 	{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3449c, 0 },
25104 	{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x344a0, 0 },
25105 	{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x344a4, 0 },
25106 	{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x344a8, 0 },
25107 	{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x344ac, 0 },
25108 	{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x344b0, 0 },
25109 	{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x344b4, 0 },
25110 	{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x344c0, 0 },
25111 	{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x344c4, 0 },
25112 	{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x344c8, 0 },
25113 	{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x344cc, 0 },
25114 	{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x344d0, 0 },
25115 	{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x344d4, 0 },
25116 	{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x344d8, 0 },
25117 	{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x344dc, 0 },
25118 	{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x344e0, 0 },
25119 	{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x344e4, 0 },
25120 	{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x344e8, 0 },
25121 	{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x344ec, 0 },
25122 	{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x344f0, 0 },
25123 	{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x344f4, 0 },
25124 	{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x344f8, 0 },
25125 	{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x344fc, 0 },
25126 	{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x34500, 0 },
25127 	{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x34504, 0 },
25128 	{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x34508, 0 },
25129 	{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3450c, 0 },
25130 	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x34510, 0 },
25131 	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x34514, 0 },
25132 	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x34518, 0 },
25133 	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3451c, 0 },
25134 	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x34520, 0 },
25135 	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x34524, 0 },
25136 	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x34528, 0 },
25137 	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3452c, 0 },
25138 	{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x34540, 0 },
25139 	{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x34544, 0 },
25140 	{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x34548, 0 },
25141 	{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3454c, 0 },
25142 	{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x34550, 0 },
25143 	{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x34554, 0 },
25144 	{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x34558, 0 },
25145 	{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3455c, 0 },
25146 	{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x34560, 0 },
25147 	{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x34564, 0 },
25148 	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x34568, 0 },
25149 	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3456c, 0 },
25150 	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x34570, 0 },
25151 	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x34574, 0 },
25152 	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x34578, 0 },
25153 	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3457c, 0 },
25154 	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x34580, 0 },
25155 	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x34584, 0 },
25156 	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x34588, 0 },
25157 	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3458c, 0 },
25158 	{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x34590, 0 },
25159 	{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x34594, 0 },
25160 	{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x34598, 0 },
25161 	{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3459c, 0 },
25162 	{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x345a0, 0 },
25163 	{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x345a4, 0 },
25164 	{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x345a8, 0 },
25165 	{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x345ac, 0 },
25166 	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x345b0, 0 },
25167 	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x345b4, 0 },
25168 	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x345b8, 0 },
25169 	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x345bc, 0 },
25170 	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x345c0, 0 },
25171 	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x345c4, 0 },
25172 	{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x345c8, 0 },
25173 	{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x345cc, 0 },
25174 	{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x345d0, 0 },
25175 	{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x345d4, 0 },
25176 	{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x345d8, 0 },
25177 	{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x345dc, 0 },
25178 	{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x345e0, 0 },
25179 	{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x345e4, 0 },
25180 	{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x345e8, 0 },
25181 	{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x345ec, 0 },
25182 	{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x345f0, 0 },
25183 	{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x345f4, 0 },
25184 	{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x345f8, 0 },
25185 	{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x345fc, 0 },
25186 	{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x34600, 0 },
25187 	{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x34604, 0 },
25188 	{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x34608, 0 },
25189 	{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3460c, 0 },
25190 	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x34610, 0 },
25191 	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x34614, 0 },
25192 	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x34618, 0 },
25193 	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3461c, 0 },
25194 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 },
25195 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 },
25196 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 },
25197 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 },
25198 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 },
25199 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 },
25200 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 },
25201 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 },
25202 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 },
25203 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 },
25204 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 },
25205 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 },
25206 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 },
25207 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 },
25208 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 },
25209 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 },
25210 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 },
25211 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 },
25212 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 },
25213 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 },
25214 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 },
25215 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 },
25216 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 },
25217 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 },
25218 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 },
25219 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 },
25220 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 },
25221 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 },
25222 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 },
25223 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 },
25224 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 },
25225 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 },
25226 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e380, 0 },
25227 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e384, 0 },
25228 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 },
25229 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 },
25230 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 },
25231 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 },
25232 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 },
25233 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 },
25234 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 },
25235 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 },
25236 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 },
25237 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 },
25238 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 },
25239 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 },
25240 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 },
25241 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 },
25242 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 },
25243 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 },
25244 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 },
25245 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 },
25246 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 },
25247 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 },
25248 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 },
25249 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 },
25250 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 },
25251 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 },
25252 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 },
25253 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 },
25254 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 },
25255 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 },
25256 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 },
25257 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 },
25258 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 },
25259 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 },
25260 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e780, 0 },
25261 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e784, 0 },
25262 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 },
25263 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 },
25264 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 },
25265 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 },
25266 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 },
25267 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 },
25268 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 },
25269 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 },
25270 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 },
25271 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 },
25272 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 },
25273 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 },
25274 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 },
25275 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 },
25276 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 },
25277 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 },
25278 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 },
25279 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 },
25280 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 },
25281 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 },
25282 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 },
25283 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 },
25284 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 },
25285 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 },
25286 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 },
25287 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 },
25288 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 },
25289 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 },
25290 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 },
25291 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 },
25292 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 },
25293 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 },
25294 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1eb80, 0 },
25295 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1eb84, 0 },
25296 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 },
25297 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 },
25298 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 },
25299 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 },
25300 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 },
25301 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 },
25302 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 },
25303 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 },
25304 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 },
25305 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 },
25306 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 },
25307 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 },
25308 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 },
25309 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 },
25310 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 },
25311 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 },
25312 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 },
25313 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 },
25314 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 },
25315 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 },
25316 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 },
25317 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 },
25318 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 },
25319 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 },
25320 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 },
25321 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 },
25322 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 },
25323 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 },
25324 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 },
25325 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 },
25326 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 },
25327 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 },
25328 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ef80, 0 },
25329 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ef84, 0 },
25330 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 },
25331 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 },
25332 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 },
25333 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 },
25334 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 },
25335 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 },
25336 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 },
25337 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 },
25338 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 },
25339 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 },
25340 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 },
25341 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 },
25342 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 },
25343 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 },
25344 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 },
25345 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 },
25346 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 },
25347 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 },
25348 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 },
25349 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 },
25350 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 },
25351 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 },
25352 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 },
25353 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 },
25354 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 },
25355 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 },
25356 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 },
25357 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 },
25358 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 },
25359 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 },
25360 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 },
25361 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 },
25362 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f380, 0 },
25363 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f384, 0 },
25364 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 },
25365 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 },
25366 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 },
25367 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 },
25368 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 },
25369 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 },
25370 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 },
25371 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 },
25372 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 },
25373 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 },
25374 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 },
25375 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 },
25376 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 },
25377 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 },
25378 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 },
25379 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 },
25380 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 },
25381 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 },
25382 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 },
25383 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 },
25384 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 },
25385 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 },
25386 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 },
25387 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 },
25388 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 },
25389 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 },
25390 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 },
25391 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 },
25392 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 },
25393 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 },
25394 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 },
25395 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 },
25396 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f780, 0 },
25397 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f784, 0 },
25398 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 },
25399 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 },
25400 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 },
25401 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 },
25402 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 },
25403 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 },
25404 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 },
25405 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 },
25406 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 },
25407 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 },
25408 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 },
25409 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 },
25410 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 },
25411 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 },
25412 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 },
25413 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 },
25414 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 },
25415 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 },
25416 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 },
25417 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 },
25418 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 },
25419 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 },
25420 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 },
25421 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 },
25422 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 },
25423 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 },
25424 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 },
25425 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 },
25426 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 },
25427 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 },
25428 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 },
25429 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 },
25430 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1fb80, 0 },
25431 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1fb84, 0 },
25432 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 },
25433 	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 },
25434 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 },
25435 	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 },
25436 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 },
25437 	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 },
25438 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 },
25439 	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 },
25440 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 },
25441 	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 },
25442 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 },
25443 	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 },
25444 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 },
25445 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 },
25446 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 },
25447 	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 },
25448 	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 },
25449 	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 },
25450 	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 },
25451 	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 },
25452 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 },
25453 	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 },
25454 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 },
25455 	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 },
25456 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 },
25457 	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 },
25458 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 },
25459 	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 },
25460 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 },
25461 	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 },
25462 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 },
25463 	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 },
25464 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ff80, 0 },
25465 	{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ff84, 0 },
25466 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30200, 0 },
25476 		{ "VF", 0, 8 },
25477 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30204, 0 },
25487 		{ "VF", 0, 8 },
25488 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30208, 0 },
25498 		{ "VF", 0, 8 },
25499 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3020c, 0 },
25509 		{ "VF", 0, 8 },
25510 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30210, 0 },
25520 		{ "VF", 0, 8 },
25521 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30214, 0 },
25531 		{ "VF", 0, 8 },
25532 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30218, 0 },
25542 		{ "VF", 0, 8 },
25543 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3021c, 0 },
25553 		{ "VF", 0, 8 },
25554 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30220, 0 },
25564 		{ "VF", 0, 8 },
25565 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30224, 0 },
25575 		{ "VF", 0, 8 },
25576 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30228, 0 },
25586 		{ "VF", 0, 8 },
25587 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3022c, 0 },
25597 		{ "VF", 0, 8 },
25598 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30230, 0 },
25608 		{ "VF", 0, 8 },
25609 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30234, 0 },
25619 		{ "VF", 0, 8 },
25620 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30238, 0 },
25630 		{ "VF", 0, 8 },
25631 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3023c, 0 },
25641 		{ "VF", 0, 8 },
25642 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30240, 0 },
25652 		{ "VF", 0, 8 },
25653 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30244, 0 },
25663 		{ "VF", 0, 8 },
25664 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30248, 0 },
25674 		{ "VF", 0, 8 },
25675 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3024c, 0 },
25685 		{ "VF", 0, 8 },
25686 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30250, 0 },
25696 		{ "VF", 0, 8 },
25697 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30254, 0 },
25707 		{ "VF", 0, 8 },
25708 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30258, 0 },
25718 		{ "VF", 0, 8 },
25719 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3025c, 0 },
25729 		{ "VF", 0, 8 },
25730 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30260, 0 },
25740 		{ "VF", 0, 8 },
25741 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30264, 0 },
25751 		{ "VF", 0, 8 },
25752 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30268, 0 },
25762 		{ "VF", 0, 8 },
25763 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3026c, 0 },
25773 		{ "VF", 0, 8 },
25774 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30270, 0 },
25784 		{ "VF", 0, 8 },
25785 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30274, 0 },
25795 		{ "VF", 0, 8 },
25796 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30278, 0 },
25806 		{ "VF", 0, 8 },
25807 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3027c, 0 },
25817 		{ "VF", 0, 8 },
25818 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30280, 0 },
25828 		{ "VF", 0, 8 },
25829 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30284, 0 },
25839 		{ "VF", 0, 8 },
25840 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30288, 0 },
25850 		{ "VF", 0, 8 },
25851 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3028c, 0 },
25861 		{ "VF", 0, 8 },
25862 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30290, 0 },
25872 		{ "VF", 0, 8 },
25873 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30294, 0 },
25883 		{ "VF", 0, 8 },
25884 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30298, 0 },
25894 		{ "VF", 0, 8 },
25895 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3029c, 0 },
25905 		{ "VF", 0, 8 },
25906 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302a0, 0 },
25916 		{ "VF", 0, 8 },
25917 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302a4, 0 },
25927 		{ "VF", 0, 8 },
25928 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302a8, 0 },
25938 		{ "VF", 0, 8 },
25939 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302ac, 0 },
25949 		{ "VF", 0, 8 },
25950 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302b0, 0 },
25960 		{ "VF", 0, 8 },
25961 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302b4, 0 },
25971 		{ "VF", 0, 8 },
25972 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302b8, 0 },
25982 		{ "VF", 0, 8 },
25983 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302bc, 0 },
25993 		{ "VF", 0, 8 },
25994 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302c0, 0 },
26004 		{ "VF", 0, 8 },
26005 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302c4, 0 },
26015 		{ "VF", 0, 8 },
26016 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302c8, 0 },
26026 		{ "VF", 0, 8 },
26027 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302cc, 0 },
26037 		{ "VF", 0, 8 },
26038 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302d0, 0 },
26048 		{ "VF", 0, 8 },
26049 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302d4, 0 },
26059 		{ "VF", 0, 8 },
26060 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302d8, 0 },
26070 		{ "VF", 0, 8 },
26071 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302dc, 0 },
26081 		{ "VF", 0, 8 },
26082 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302e0, 0 },
26092 		{ "VF", 0, 8 },
26093 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302e4, 0 },
26103 		{ "VF", 0, 8 },
26104 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302e8, 0 },
26114 		{ "VF", 0, 8 },
26115 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302ec, 0 },
26125 		{ "VF", 0, 8 },
26126 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302f0, 0 },
26136 		{ "VF", 0, 8 },
26137 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302f4, 0 },
26147 		{ "VF", 0, 8 },
26148 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302f8, 0 },
26158 		{ "VF", 0, 8 },
26159 	{ "MPS_PORT_CLS_HASH_SRAM", 0x302fc, 0 },
26169 		{ "VF", 0, 8 },
26170 	{ "MPS_PORT_CLS_HASH_SRAM", 0x30300, 0 },
26180 		{ "VF", 0, 8 },
26181 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34200, 0 },
26191 		{ "VF", 0, 8 },
26192 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34204, 0 },
26202 		{ "VF", 0, 8 },
26203 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34208, 0 },
26213 		{ "VF", 0, 8 },
26214 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3420c, 0 },
26224 		{ "VF", 0, 8 },
26225 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34210, 0 },
26235 		{ "VF", 0, 8 },
26236 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34214, 0 },
26246 		{ "VF", 0, 8 },
26247 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34218, 0 },
26257 		{ "VF", 0, 8 },
26258 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3421c, 0 },
26268 		{ "VF", 0, 8 },
26269 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34220, 0 },
26279 		{ "VF", 0, 8 },
26280 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34224, 0 },
26290 		{ "VF", 0, 8 },
26291 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34228, 0 },
26301 		{ "VF", 0, 8 },
26302 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3422c, 0 },
26312 		{ "VF", 0, 8 },
26313 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34230, 0 },
26323 		{ "VF", 0, 8 },
26324 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34234, 0 },
26334 		{ "VF", 0, 8 },
26335 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34238, 0 },
26345 		{ "VF", 0, 8 },
26346 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3423c, 0 },
26356 		{ "VF", 0, 8 },
26357 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34240, 0 },
26367 		{ "VF", 0, 8 },
26368 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34244, 0 },
26378 		{ "VF", 0, 8 },
26379 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34248, 0 },
26389 		{ "VF", 0, 8 },
26390 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3424c, 0 },
26400 		{ "VF", 0, 8 },
26401 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34250, 0 },
26411 		{ "VF", 0, 8 },
26412 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34254, 0 },
26422 		{ "VF", 0, 8 },
26423 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34258, 0 },
26433 		{ "VF", 0, 8 },
26434 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3425c, 0 },
26444 		{ "VF", 0, 8 },
26445 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34260, 0 },
26455 		{ "VF", 0, 8 },
26456 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34264, 0 },
26466 		{ "VF", 0, 8 },
26467 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34268, 0 },
26477 		{ "VF", 0, 8 },
26478 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3426c, 0 },
26488 		{ "VF", 0, 8 },
26489 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34270, 0 },
26499 		{ "VF", 0, 8 },
26500 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34274, 0 },
26510 		{ "VF", 0, 8 },
26511 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34278, 0 },
26521 		{ "VF", 0, 8 },
26522 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3427c, 0 },
26532 		{ "VF", 0, 8 },
26533 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34280, 0 },
26543 		{ "VF", 0, 8 },
26544 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34284, 0 },
26554 		{ "VF", 0, 8 },
26555 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34288, 0 },
26565 		{ "VF", 0, 8 },
26566 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3428c, 0 },
26576 		{ "VF", 0, 8 },
26577 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34290, 0 },
26587 		{ "VF", 0, 8 },
26588 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34294, 0 },
26598 		{ "VF", 0, 8 },
26599 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34298, 0 },
26609 		{ "VF", 0, 8 },
26610 	{ "MPS_PORT_CLS_HASH_SRAM", 0x3429c, 0 },
26620 		{ "VF", 0, 8 },
26621 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342a0, 0 },
26631 		{ "VF", 0, 8 },
26632 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342a4, 0 },
26642 		{ "VF", 0, 8 },
26643 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342a8, 0 },
26653 		{ "VF", 0, 8 },
26654 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342ac, 0 },
26664 		{ "VF", 0, 8 },
26665 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342b0, 0 },
26675 		{ "VF", 0, 8 },
26676 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342b4, 0 },
26686 		{ "VF", 0, 8 },
26687 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342b8, 0 },
26697 		{ "VF", 0, 8 },
26698 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342bc, 0 },
26708 		{ "VF", 0, 8 },
26709 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342c0, 0 },
26719 		{ "VF", 0, 8 },
26720 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342c4, 0 },
26730 		{ "VF", 0, 8 },
26731 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342c8, 0 },
26741 		{ "VF", 0, 8 },
26742 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342cc, 0 },
26752 		{ "VF", 0, 8 },
26753 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342d0, 0 },
26763 		{ "VF", 0, 8 },
26764 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342d4, 0 },
26774 		{ "VF", 0, 8 },
26775 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342d8, 0 },
26785 		{ "VF", 0, 8 },
26786 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342dc, 0 },
26796 		{ "VF", 0, 8 },
26797 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342e0, 0 },
26807 		{ "VF", 0, 8 },
26808 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342e4, 0 },
26818 		{ "VF", 0, 8 },
26819 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342e8, 0 },
26829 		{ "VF", 0, 8 },
26830 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342ec, 0 },
26840 		{ "VF", 0, 8 },
26841 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342f0, 0 },
26851 		{ "VF", 0, 8 },
26852 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342f4, 0 },
26862 		{ "VF", 0, 8 },
26863 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342f8, 0 },
26873 		{ "VF", 0, 8 },
26874 	{ "MPS_PORT_CLS_HASH_SRAM", 0x342fc, 0 },
26884 		{ "VF", 0, 8 },
26885 	{ "MPS_PORT_CLS_HASH_SRAM", 0x34300, 0 },
26895 		{ "VF", 0, 8 },
26896 	{ "MPS_PORT_CLS_HASH_CTL", 0x30304, 0 },
26898 	{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x30308, 0 },
26905 		{ "VF", 0, 8 },
26906 	{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3030c, 0 },
26907 	{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x30310, 0 },
26911 		{ "DA", 0, 16 },
26912 	{ "MPS_PORT_CLS_BMC_VLAN", 0x30314, 0 },
26915 		{ "VLAN_ID", 0, 12 },
26916 	{ "MPS_PORT_CLS_CTL", 0x30318, 0 },
26927 		{ "PF_VLAN_SEL", 0, 1 },
26928 	{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3031c, 0 },
26930 		{ "EthType2", 0, 16 },
26931 	{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x30320, 0 },
26933 		{ "EN2", 0, 1 },
26934 	{ "MPS_PORT_CLS_HASH_CTL", 0x34304, 0 },
26936 	{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x34308, 0 },
26943 		{ "VF", 0, 8 },
26944 	{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3430c, 0 },
26945 	{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x34310, 0 },
26949 		{ "DA", 0, 16 },
26950 	{ "MPS_PORT_CLS_BMC_VLAN", 0x34314, 0 },
26953 		{ "VLAN_ID", 0, 12 },
26954 	{ "MPS_PORT_CLS_CTL", 0x34318, 0 },
26965 		{ "PF_VLAN_SEL", 0, 1 },
26966 	{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3431c, 0 },
26968 		{ "EthType2", 0, 16 },
26969 	{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x34320, 0 },
26971 		{ "EN2", 0, 1 },
26972 	{ "MPS_CLS_CTL", 0xd000, 0 },
26980 		{ "VlanClsEn", 0, 1 },
26981 	{ "MPS_CLS_ARB_WEIGHT", 0xd004, 0 },
26984 		{ "LpbkWeight", 0, 5 },
26985 	{ "MPS_CLS_NCSI_ETH_TYPE", 0xd008, 0 },
26987 		{ "EthType2", 0, 16 },
26988 	{ "MPS_CLS_NCSI_ETH_TYPE_EN", 0xd00c, 0 },
26990 		{ "EN2", 0, 1 },
26991 	{ "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 },
26992 	{ "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 },
26996 		{ "DA", 0, 16 },
26997 	{ "MPS_CLS_BMC_VLAN", 0xd018, 0 },
26999 		{ "VLAN_ID", 0, 12 },
27000 	{ "MPS_CLS_PERR_INJECT", 0xd01c, 0 },
27002 		{ "InjectDataErr", 0, 1 },
27003 	{ "MPS_CLS_PERR_ENABLE", 0xd020, 0 },
27006 		{ "MatchSRAM", 0, 1 },
27007 	{ "MPS_CLS_INT_ENABLE", 0xd024, 0 },
27011 		{ "MatchSRAM", 0, 1 },
27012 	{ "MPS_CLS_INT_CAUSE", 0xd028, 0 },
27016 		{ "MatchSRAM", 0, 1 },
27017 	{ "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 },
27018 	{ "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 },
27019 	{ "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 },
27027 		{ "Cls_Match", 0, 3 },
27028 	{ "MPS_CLS_PL_TEST_CTL", 0xd038, 0 },
27029 	{ "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 },
27030 	{ "MPS_CLS_MATCH_CNT_TCAM", 0xd100, 0 },
27031 	{ "MPS_CLS_MATCH_CNT_HASH", 0xd104, 0 },
27032 	{ "MPS_CLS_MATCH_CNT_BCAST", 0xd108, 0 },
27033 	{ "MPS_CLS_MATCH_CNT_BMC", 0xd10c, 0 },
27034 	{ "MPS_CLS_MATCH_CNT_PROM", 0xd110, 0 },
27035 	{ "MPS_CLS_MATCH_CNT_HPROM", 0xd114, 0 },
27036 	{ "MPS_CLS_MISS_CNT", 0xd118, 0 },
27037 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd200, 0 },
27038 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd220, 0 },
27039 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd240, 0 },
27040 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd260, 0 },
27041 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd280, 0 },
27042 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2a0, 0 },
27043 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2c0, 0 },
27044 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2e0, 0 },
27045 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd204, 0 },
27046 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd224, 0 },
27047 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd244, 0 },
27048 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd264, 0 },
27049 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd284, 0 },
27050 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2a4, 0 },
27051 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2c4, 0 },
27052 	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2e4, 0 },
27053 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd208, 0 },
27054 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd228, 0 },
27055 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd248, 0 },
27056 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd268, 0 },
27057 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd288, 0 },
27058 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2a8, 0 },
27059 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2c8, 0 },
27060 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2e8, 0 },
27061 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd20c, 0 },
27062 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd22c, 0 },
27063 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd24c, 0 },
27064 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd26c, 0 },
27065 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd28c, 0 },
27066 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ac, 0 },
27067 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2cc, 0 },
27068 	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ec, 0 },
27069 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd210, 0 },
27072 		{ "ClsTrcReqPort", 0, 4 },
27073 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd230, 0 },
27076 		{ "ClsTrcReqPort", 0, 4 },
27077 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd250, 0 },
27080 		{ "ClsTrcReqPort", 0, 4 },
27081 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd270, 0 },
27084 		{ "ClsTrcReqPort", 0, 4 },
27085 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd290, 0 },
27088 		{ "ClsTrcReqPort", 0, 4 },
27089 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2b0, 0 },
27092 		{ "ClsTrcReqPort", 0, 4 },
27093 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2d0, 0 },
27096 		{ "ClsTrcReqPort", 0, 4 },
27097 	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2f0, 0 },
27100 		{ "ClsTrcReqPort", 0, 4 },
27101 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd214, 0 },
27104 		{ "ClsTrcVNI", 0, 24 },
27105 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd234, 0 },
27108 		{ "ClsTrcVNI", 0, 24 },
27109 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd254, 0 },
27112 		{ "ClsTrcVNI", 0, 24 },
27113 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd274, 0 },
27116 		{ "ClsTrcVNI", 0, 24 },
27117 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd294, 0 },
27120 		{ "ClsTrcVNI", 0, 24 },
27121 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2b4, 0 },
27124 		{ "ClsTrcVNI", 0, 24 },
27125 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2d4, 0 },
27128 		{ "ClsTrcVNI", 0, 24 },
27129 	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2f4, 0 },
27132 		{ "ClsTrcVNI", 0, 24 },
27133 	{ "MPS_CLS_RESULT_TRACE", 0xd300, 0 },
27143 		{ "ClsTrcVF", 0, 3 },
27144 	{ "MPS_CLS_RESULT_TRACE", 0xd304, 0 },
27154 		{ "ClsTrcVF", 0, 3 },
27155 	{ "MPS_CLS_RESULT_TRACE", 0xd308, 0 },
27165 		{ "ClsTrcVF", 0, 3 },
27166 	{ "MPS_CLS_RESULT_TRACE", 0xd30c, 0 },
27176 		{ "ClsTrcVF", 0, 3 },
27177 	{ "MPS_CLS_RESULT_TRACE", 0xd310, 0 },
27187 		{ "ClsTrcVF", 0, 3 },
27188 	{ "MPS_CLS_RESULT_TRACE", 0xd314, 0 },
27198 		{ "ClsTrcVF", 0, 3 },
27199 	{ "MPS_CLS_RESULT_TRACE", 0xd318, 0 },
27209 		{ "ClsTrcVF", 0, 3 },
27210 	{ "MPS_CLS_RESULT_TRACE", 0xd31c, 0 },
27220 		{ "ClsTrcVF", 0, 3 },
27221 	{ "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 },
27225 		{ "VLAN_ID", 0, 12 },
27226 	{ "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 },
27230 		{ "VLAN_ID", 0, 12 },
27231 	{ "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 },
27235 		{ "VLAN_ID", 0, 12 },
27236 	{ "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 },
27240 		{ "VLAN_ID", 0, 12 },
27241 	{ "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 },
27245 		{ "VLAN_ID", 0, 12 },
27246 	{ "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 },
27250 		{ "VLAN_ID", 0, 12 },
27251 	{ "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 },
27255 		{ "VLAN_ID", 0, 12 },
27256 	{ "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 },
27260 		{ "VLAN_ID", 0, 12 },
27261 	{ "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 },
27265 		{ "VLAN_ID", 0, 12 },
27266 	{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12000, 0 },
27267 	{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12008, 0 },
27268 	{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12010, 0 },
27269 	{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12018, 0 },
27270 	{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x12004, 0 },
27271 	{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x1200c, 0 },
27272 	{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x12014, 0 },
27273 	{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x1201c, 0 },
27274 	{ "MPS_CLS_DIPIPV6ID_0_TABLE", 0x12020, 0 },
27275 	{ "MPS_CLS_DIPIPV6ID_0_TABLE", 0x12040, 0 },
27276 	{ "MPS_CLS_DIPIPV6ID_1_TABLE", 0x12024, 0 },
27277 	{ "MPS_CLS_DIPIPV6ID_1_TABLE", 0x12044, 0 },
27278 	{ "MPS_CLS_DIPIPV6ID_2_TABLE", 0x12028, 0 },
27279 	{ "MPS_CLS_DIPIPV6ID_2_TABLE", 0x12048, 0 },
27280 	{ "MPS_CLS_DIPIPV6ID_3_TABLE", 0x1202c, 0 },
27281 	{ "MPS_CLS_DIPIPV6ID_3_TABLE", 0x1204c, 0 },
27282 	{ "MPS_CLS_DIPIPV6MASK_0_TABLE", 0x12030, 0 },
27283 	{ "MPS_CLS_DIPIPV6MASK_0_TABLE", 0x12050, 0 },
27284 	{ "MPS_CLS_DIPIPV6MASK_1_TABLE", 0x12034, 0 },
27285 	{ "MPS_CLS_DIPIPV6MASK_1_TABLE", 0x12054, 0 },
27286 	{ "MPS_CLS_DIPIPV6MASK_2_TABLE", 0x12038, 0 },
27287 	{ "MPS_CLS_DIPIPV6MASK_2_TABLE", 0x12058, 0 },
27288 	{ "MPS_CLS_DIPIPV6MASK_3_TABLE", 0x1203c, 0 },
27289 	{ "MPS_CLS_DIPIPV6MASK_3_TABLE", 0x1205c, 0 },
27290 	{ "MPS_RX_HASH_LKP_TABLE", 0x12060, 0 },
27291 	{ "MPS_RX_HASH_LKP_TABLE", 0x12064, 0 },
27292 	{ "MPS_RX_HASH_LKP_TABLE", 0x12068, 0 },
27293 	{ "MPS_RX_HASH_LKP_TABLE", 0x1206c, 0 },
27294 	{ "MPS_CLS_SRAM_L", 0xe000, 0 },
27309 		{ "VF", 0, 8 },
27310 	{ "MPS_CLS_SRAM_L", 0xe008, 0 },
27325 		{ "VF", 0, 8 },
27326 	{ "MPS_CLS_SRAM_L", 0xe010, 0 },
27341 		{ "VF", 0, 8 },
27342 	{ "MPS_CLS_SRAM_L", 0xe018, 0 },
27357 		{ "VF", 0, 8 },
27358 	{ "MPS_CLS_SRAM_L", 0xe020, 0 },
27373 		{ "VF", 0, 8 },
27374 	{ "MPS_CLS_SRAM_L", 0xe028, 0 },
27389 		{ "VF", 0, 8 },
27390 	{ "MPS_CLS_SRAM_L", 0xe030, 0 },
27405 		{ "VF", 0, 8 },
27406 	{ "MPS_CLS_SRAM_L", 0xe038, 0 },
27421 		{ "VF", 0, 8 },
27422 	{ "MPS_CLS_SRAM_L", 0xe040, 0 },
27437 		{ "VF", 0, 8 },
27438 	{ "MPS_CLS_SRAM_L", 0xe048, 0 },
27453 		{ "VF", 0, 8 },
27454 	{ "MPS_CLS_SRAM_L", 0xe050, 0 },
27469 		{ "VF", 0, 8 },
27470 	{ "MPS_CLS_SRAM_L", 0xe058, 0 },
27485 		{ "VF", 0, 8 },
27486 	{ "MPS_CLS_SRAM_L", 0xe060, 0 },
27501 		{ "VF", 0, 8 },
27502 	{ "MPS_CLS_SRAM_L", 0xe068, 0 },
27517 		{ "VF", 0, 8 },
27518 	{ "MPS_CLS_SRAM_L", 0xe070, 0 },
27533 		{ "VF", 0, 8 },
27534 	{ "MPS_CLS_SRAM_L", 0xe078, 0 },
27549 		{ "VF", 0, 8 },
27550 	{ "MPS_CLS_SRAM_L", 0xe080, 0 },
27565 		{ "VF", 0, 8 },
27566 	{ "MPS_CLS_SRAM_L", 0xe088, 0 },
27581 		{ "VF", 0, 8 },
27582 	{ "MPS_CLS_SRAM_L", 0xe090, 0 },
27597 		{ "VF", 0, 8 },
27598 	{ "MPS_CLS_SRAM_L", 0xe098, 0 },
27613 		{ "VF", 0, 8 },
27614 	{ "MPS_CLS_SRAM_L", 0xe0a0, 0 },
27629 		{ "VF", 0, 8 },
27630 	{ "MPS_CLS_SRAM_L", 0xe0a8, 0 },
27645 		{ "VF", 0, 8 },
27646 	{ "MPS_CLS_SRAM_L", 0xe0b0, 0 },
27661 		{ "VF", 0, 8 },
27662 	{ "MPS_CLS_SRAM_L", 0xe0b8, 0 },
27677 		{ "VF", 0, 8 },
27678 	{ "MPS_CLS_SRAM_L", 0xe0c0, 0 },
27693 		{ "VF", 0, 8 },
27694 	{ "MPS_CLS_SRAM_L", 0xe0c8, 0 },
27709 		{ "VF", 0, 8 },
27710 	{ "MPS_CLS_SRAM_L", 0xe0d0, 0 },
27725 		{ "VF", 0, 8 },
27726 	{ "MPS_CLS_SRAM_L", 0xe0d8, 0 },
27741 		{ "VF", 0, 8 },
27742 	{ "MPS_CLS_SRAM_L", 0xe0e0, 0 },
27757 		{ "VF", 0, 8 },
27758 	{ "MPS_CLS_SRAM_L", 0xe0e8, 0 },
27773 		{ "VF", 0, 8 },
27774 	{ "MPS_CLS_SRAM_L", 0xe0f0, 0 },
27789 		{ "VF", 0, 8 },
27790 	{ "MPS_CLS_SRAM_L", 0xe0f8, 0 },
27805 		{ "VF", 0, 8 },
27806 	{ "MPS_CLS_SRAM_L", 0xe100, 0 },
27821 		{ "VF", 0, 8 },
27822 	{ "MPS_CLS_SRAM_L", 0xe108, 0 },
27837 		{ "VF", 0, 8 },
27838 	{ "MPS_CLS_SRAM_L", 0xe110, 0 },
27853 		{ "VF", 0, 8 },
27854 	{ "MPS_CLS_SRAM_L", 0xe118, 0 },
27869 		{ "VF", 0, 8 },
27870 	{ "MPS_CLS_SRAM_L", 0xe120, 0 },
27885 		{ "VF", 0, 8 },
27886 	{ "MPS_CLS_SRAM_L", 0xe128, 0 },
27901 		{ "VF", 0, 8 },
27902 	{ "MPS_CLS_SRAM_L", 0xe130, 0 },
27917 		{ "VF", 0, 8 },
27918 	{ "MPS_CLS_SRAM_L", 0xe138, 0 },
27933 		{ "VF", 0, 8 },
27934 	{ "MPS_CLS_SRAM_L", 0xe140, 0 },
27949 		{ "VF", 0, 8 },
27950 	{ "MPS_CLS_SRAM_L", 0xe148, 0 },
27965 		{ "VF", 0, 8 },
27966 	{ "MPS_CLS_SRAM_L", 0xe150, 0 },
27981 		{ "VF", 0, 8 },
27982 	{ "MPS_CLS_SRAM_L", 0xe158, 0 },
27997 		{ "VF", 0, 8 },
27998 	{ "MPS_CLS_SRAM_L", 0xe160, 0 },
28013 		{ "VF", 0, 8 },
28014 	{ "MPS_CLS_SRAM_L", 0xe168, 0 },
28029 		{ "VF", 0, 8 },
28030 	{ "MPS_CLS_SRAM_L", 0xe170, 0 },
28045 		{ "VF", 0, 8 },
28046 	{ "MPS_CLS_SRAM_L", 0xe178, 0 },
28061 		{ "VF", 0, 8 },
28062 	{ "MPS_CLS_SRAM_L", 0xe180, 0 },
28077 		{ "VF", 0, 8 },
28078 	{ "MPS_CLS_SRAM_L", 0xe188, 0 },
28093 		{ "VF", 0, 8 },
28094 	{ "MPS_CLS_SRAM_L", 0xe190, 0 },
28109 		{ "VF", 0, 8 },
28110 	{ "MPS_CLS_SRAM_L", 0xe198, 0 },
28125 		{ "VF", 0, 8 },
28126 	{ "MPS_CLS_SRAM_L", 0xe1a0, 0 },
28141 		{ "VF", 0, 8 },
28142 	{ "MPS_CLS_SRAM_L", 0xe1a8, 0 },
28157 		{ "VF", 0, 8 },
28158 	{ "MPS_CLS_SRAM_L", 0xe1b0, 0 },
28173 		{ "VF", 0, 8 },
28174 	{ "MPS_CLS_SRAM_L", 0xe1b8, 0 },
28189 		{ "VF", 0, 8 },
28190 	{ "MPS_CLS_SRAM_L", 0xe1c0, 0 },
28205 		{ "VF", 0, 8 },
28206 	{ "MPS_CLS_SRAM_L", 0xe1c8, 0 },
28221 		{ "VF", 0, 8 },
28222 	{ "MPS_CLS_SRAM_L", 0xe1d0, 0 },
28237 		{ "VF", 0, 8 },
28238 	{ "MPS_CLS_SRAM_L", 0xe1d8, 0 },
28253 		{ "VF", 0, 8 },
28254 	{ "MPS_CLS_SRAM_L", 0xe1e0, 0 },
28269 		{ "VF", 0, 8 },
28270 	{ "MPS_CLS_SRAM_L", 0xe1e8, 0 },
28285 		{ "VF", 0, 8 },
28286 	{ "MPS_CLS_SRAM_L", 0xe1f0, 0 },
28301 		{ "VF", 0, 8 },
28302 	{ "MPS_CLS_SRAM_L", 0xe1f8, 0 },
28317 		{ "VF", 0, 8 },
28318 	{ "MPS_CLS_SRAM_L", 0xe200, 0 },
28333 		{ "VF", 0, 8 },
28334 	{ "MPS_CLS_SRAM_L", 0xe208, 0 },
28349 		{ "VF", 0, 8 },
28350 	{ "MPS_CLS_SRAM_L", 0xe210, 0 },
28365 		{ "VF", 0, 8 },
28366 	{ "MPS_CLS_SRAM_L", 0xe218, 0 },
28381 		{ "VF", 0, 8 },
28382 	{ "MPS_CLS_SRAM_L", 0xe220, 0 },
28397 		{ "VF", 0, 8 },
28398 	{ "MPS_CLS_SRAM_L", 0xe228, 0 },
28413 		{ "VF", 0, 8 },
28414 	{ "MPS_CLS_SRAM_L", 0xe230, 0 },
28429 		{ "VF", 0, 8 },
28430 	{ "MPS_CLS_SRAM_L", 0xe238, 0 },
28445 		{ "VF", 0, 8 },
28446 	{ "MPS_CLS_SRAM_L", 0xe240, 0 },
28461 		{ "VF", 0, 8 },
28462 	{ "MPS_CLS_SRAM_L", 0xe248, 0 },
28477 		{ "VF", 0, 8 },
28478 	{ "MPS_CLS_SRAM_L", 0xe250, 0 },
28493 		{ "VF", 0, 8 },
28494 	{ "MPS_CLS_SRAM_L", 0xe258, 0 },
28509 		{ "VF", 0, 8 },
28510 	{ "MPS_CLS_SRAM_L", 0xe260, 0 },
28525 		{ "VF", 0, 8 },
28526 	{ "MPS_CLS_SRAM_L", 0xe268, 0 },
28541 		{ "VF", 0, 8 },
28542 	{ "MPS_CLS_SRAM_L", 0xe270, 0 },
28557 		{ "VF", 0, 8 },
28558 	{ "MPS_CLS_SRAM_L", 0xe278, 0 },
28573 		{ "VF", 0, 8 },
28574 	{ "MPS_CLS_SRAM_L", 0xe280, 0 },
28589 		{ "VF", 0, 8 },
28590 	{ "MPS_CLS_SRAM_L", 0xe288, 0 },
28605 		{ "VF", 0, 8 },
28606 	{ "MPS_CLS_SRAM_L", 0xe290, 0 },
28621 		{ "VF", 0, 8 },
28622 	{ "MPS_CLS_SRAM_L", 0xe298, 0 },
28637 		{ "VF", 0, 8 },
28638 	{ "MPS_CLS_SRAM_L", 0xe2a0, 0 },
28653 		{ "VF", 0, 8 },
28654 	{ "MPS_CLS_SRAM_L", 0xe2a8, 0 },
28669 		{ "VF", 0, 8 },
28670 	{ "MPS_CLS_SRAM_L", 0xe2b0, 0 },
28685 		{ "VF", 0, 8 },
28686 	{ "MPS_CLS_SRAM_L", 0xe2b8, 0 },
28701 		{ "VF", 0, 8 },
28702 	{ "MPS_CLS_SRAM_L", 0xe2c0, 0 },
28717 		{ "VF", 0, 8 },
28718 	{ "MPS_CLS_SRAM_L", 0xe2c8, 0 },
28733 		{ "VF", 0, 8 },
28734 	{ "MPS_CLS_SRAM_L", 0xe2d0, 0 },
28749 		{ "VF", 0, 8 },
28750 	{ "MPS_CLS_SRAM_L", 0xe2d8, 0 },
28765 		{ "VF", 0, 8 },
28766 	{ "MPS_CLS_SRAM_L", 0xe2e0, 0 },
28781 		{ "VF", 0, 8 },
28782 	{ "MPS_CLS_SRAM_L", 0xe2e8, 0 },
28797 		{ "VF", 0, 8 },
28798 	{ "MPS_CLS_SRAM_L", 0xe2f0, 0 },
28813 		{ "VF", 0, 8 },
28814 	{ "MPS_CLS_SRAM_L", 0xe2f8, 0 },
28829 		{ "VF", 0, 8 },
28830 	{ "MPS_CLS_SRAM_L", 0xe300, 0 },
28845 		{ "VF", 0, 8 },
28846 	{ "MPS_CLS_SRAM_L", 0xe308, 0 },
28861 		{ "VF", 0, 8 },
28862 	{ "MPS_CLS_SRAM_L", 0xe310, 0 },
28877 		{ "VF", 0, 8 },
28878 	{ "MPS_CLS_SRAM_L", 0xe318, 0 },
28893 		{ "VF", 0, 8 },
28894 	{ "MPS_CLS_SRAM_L", 0xe320, 0 },
28909 		{ "VF", 0, 8 },
28910 	{ "MPS_CLS_SRAM_L", 0xe328, 0 },
28925 		{ "VF", 0, 8 },
28926 	{ "MPS_CLS_SRAM_L", 0xe330, 0 },
28941 		{ "VF", 0, 8 },
28942 	{ "MPS_CLS_SRAM_L", 0xe338, 0 },
28957 		{ "VF", 0, 8 },
28958 	{ "MPS_CLS_SRAM_L", 0xe340, 0 },
28973 		{ "VF", 0, 8 },
28974 	{ "MPS_CLS_SRAM_L", 0xe348, 0 },
28989 		{ "VF", 0, 8 },
28990 	{ "MPS_CLS_SRAM_L", 0xe350, 0 },
29005 		{ "VF", 0, 8 },
29006 	{ "MPS_CLS_SRAM_L", 0xe358, 0 },
29021 		{ "VF", 0, 8 },
29022 	{ "MPS_CLS_SRAM_L", 0xe360, 0 },
29037 		{ "VF", 0, 8 },
29038 	{ "MPS_CLS_SRAM_L", 0xe368, 0 },
29053 		{ "VF", 0, 8 },
29054 	{ "MPS_CLS_SRAM_L", 0xe370, 0 },
29069 		{ "VF", 0, 8 },
29070 	{ "MPS_CLS_SRAM_L", 0xe378, 0 },
29085 		{ "VF", 0, 8 },
29086 	{ "MPS_CLS_SRAM_L", 0xe380, 0 },
29101 		{ "VF", 0, 8 },
29102 	{ "MPS_CLS_SRAM_L", 0xe388, 0 },
29117 		{ "VF", 0, 8 },
29118 	{ "MPS_CLS_SRAM_L", 0xe390, 0 },
29133 		{ "VF", 0, 8 },
29134 	{ "MPS_CLS_SRAM_L", 0xe398, 0 },
29149 		{ "VF", 0, 8 },
29150 	{ "MPS_CLS_SRAM_L", 0xe3a0, 0 },
29165 		{ "VF", 0, 8 },
29166 	{ "MPS_CLS_SRAM_L", 0xe3a8, 0 },
29181 		{ "VF", 0, 8 },
29182 	{ "MPS_CLS_SRAM_L", 0xe3b0, 0 },
29197 		{ "VF", 0, 8 },
29198 	{ "MPS_CLS_SRAM_L", 0xe3b8, 0 },
29213 		{ "VF", 0, 8 },
29214 	{ "MPS_CLS_SRAM_L", 0xe3c0, 0 },
29229 		{ "VF", 0, 8 },
29230 	{ "MPS_CLS_SRAM_L", 0xe3c8, 0 },
29245 		{ "VF", 0, 8 },
29246 	{ "MPS_CLS_SRAM_L", 0xe3d0, 0 },
29261 		{ "VF", 0, 8 },
29262 	{ "MPS_CLS_SRAM_L", 0xe3d8, 0 },
29277 		{ "VF", 0, 8 },
29278 	{ "MPS_CLS_SRAM_L", 0xe3e0, 0 },
29293 		{ "VF", 0, 8 },
29294 	{ "MPS_CLS_SRAM_L", 0xe3e8, 0 },
29309 		{ "VF", 0, 8 },
29310 	{ "MPS_CLS_SRAM_L", 0xe3f0, 0 },
29325 		{ "VF", 0, 8 },
29326 	{ "MPS_CLS_SRAM_L", 0xe3f8, 0 },
29341 		{ "VF", 0, 8 },
29342 	{ "MPS_CLS_SRAM_L", 0xe400, 0 },
29357 		{ "VF", 0, 8 },
29358 	{ "MPS_CLS_SRAM_L", 0xe408, 0 },
29373 		{ "VF", 0, 8 },
29374 	{ "MPS_CLS_SRAM_L", 0xe410, 0 },
29389 		{ "VF", 0, 8 },
29390 	{ "MPS_CLS_SRAM_L", 0xe418, 0 },
29405 		{ "VF", 0, 8 },
29406 	{ "MPS_CLS_SRAM_L", 0xe420, 0 },
29421 		{ "VF", 0, 8 },
29422 	{ "MPS_CLS_SRAM_L", 0xe428, 0 },
29437 		{ "VF", 0, 8 },
29438 	{ "MPS_CLS_SRAM_L", 0xe430, 0 },
29453 		{ "VF", 0, 8 },
29454 	{ "MPS_CLS_SRAM_L", 0xe438, 0 },
29469 		{ "VF", 0, 8 },
29470 	{ "MPS_CLS_SRAM_L", 0xe440, 0 },
29485 		{ "VF", 0, 8 },
29486 	{ "MPS_CLS_SRAM_L", 0xe448, 0 },
29501 		{ "VF", 0, 8 },
29502 	{ "MPS_CLS_SRAM_L", 0xe450, 0 },
29517 		{ "VF", 0, 8 },
29518 	{ "MPS_CLS_SRAM_L", 0xe458, 0 },
29533 		{ "VF", 0, 8 },
29534 	{ "MPS_CLS_SRAM_L", 0xe460, 0 },
29549 		{ "VF", 0, 8 },
29550 	{ "MPS_CLS_SRAM_L", 0xe468, 0 },
29565 		{ "VF", 0, 8 },
29566 	{ "MPS_CLS_SRAM_L", 0xe470, 0 },
29581 		{ "VF", 0, 8 },
29582 	{ "MPS_CLS_SRAM_L", 0xe478, 0 },
29597 		{ "VF", 0, 8 },
29598 	{ "MPS_CLS_SRAM_L", 0xe480, 0 },
29613 		{ "VF", 0, 8 },
29614 	{ "MPS_CLS_SRAM_L", 0xe488, 0 },
29629 		{ "VF", 0, 8 },
29630 	{ "MPS_CLS_SRAM_L", 0xe490, 0 },
29645 		{ "VF", 0, 8 },
29646 	{ "MPS_CLS_SRAM_L", 0xe498, 0 },
29661 		{ "VF", 0, 8 },
29662 	{ "MPS_CLS_SRAM_L", 0xe4a0, 0 },
29677 		{ "VF", 0, 8 },
29678 	{ "MPS_CLS_SRAM_L", 0xe4a8, 0 },
29693 		{ "VF", 0, 8 },
29694 	{ "MPS_CLS_SRAM_L", 0xe4b0, 0 },
29709 		{ "VF", 0, 8 },
29710 	{ "MPS_CLS_SRAM_L", 0xe4b8, 0 },
29725 		{ "VF", 0, 8 },
29726 	{ "MPS_CLS_SRAM_L", 0xe4c0, 0 },
29741 		{ "VF", 0, 8 },
29742 	{ "MPS_CLS_SRAM_L", 0xe4c8, 0 },
29757 		{ "VF", 0, 8 },
29758 	{ "MPS_CLS_SRAM_L", 0xe4d0, 0 },
29773 		{ "VF", 0, 8 },
29774 	{ "MPS_CLS_SRAM_L", 0xe4d8, 0 },
29789 		{ "VF", 0, 8 },
29790 	{ "MPS_CLS_SRAM_L", 0xe4e0, 0 },
29805 		{ "VF", 0, 8 },
29806 	{ "MPS_CLS_SRAM_L", 0xe4e8, 0 },
29821 		{ "VF", 0, 8 },
29822 	{ "MPS_CLS_SRAM_L", 0xe4f0, 0 },
29837 		{ "VF", 0, 8 },
29838 	{ "MPS_CLS_SRAM_L", 0xe4f8, 0 },
29853 		{ "VF", 0, 8 },
29854 	{ "MPS_CLS_SRAM_L", 0xe500, 0 },
29869 		{ "VF", 0, 8 },
29870 	{ "MPS_CLS_SRAM_L", 0xe508, 0 },
29885 		{ "VF", 0, 8 },
29886 	{ "MPS_CLS_SRAM_L", 0xe510, 0 },
29901 		{ "VF", 0, 8 },
29902 	{ "MPS_CLS_SRAM_L", 0xe518, 0 },
29917 		{ "VF", 0, 8 },
29918 	{ "MPS_CLS_SRAM_L", 0xe520, 0 },
29933 		{ "VF", 0, 8 },
29934 	{ "MPS_CLS_SRAM_L", 0xe528, 0 },
29949 		{ "VF", 0, 8 },
29950 	{ "MPS_CLS_SRAM_L", 0xe530, 0 },
29965 		{ "VF", 0, 8 },
29966 	{ "MPS_CLS_SRAM_L", 0xe538, 0 },
29981 		{ "VF", 0, 8 },
29982 	{ "MPS_CLS_SRAM_L", 0xe540, 0 },
29997 		{ "VF", 0, 8 },
29998 	{ "MPS_CLS_SRAM_L", 0xe548, 0 },
30013 		{ "VF", 0, 8 },
30014 	{ "MPS_CLS_SRAM_L", 0xe550, 0 },
30029 		{ "VF", 0, 8 },
30030 	{ "MPS_CLS_SRAM_L", 0xe558, 0 },
30045 		{ "VF", 0, 8 },
30046 	{ "MPS_CLS_SRAM_L", 0xe560, 0 },
30061 		{ "VF", 0, 8 },
30062 	{ "MPS_CLS_SRAM_L", 0xe568, 0 },
30077 		{ "VF", 0, 8 },
30078 	{ "MPS_CLS_SRAM_L", 0xe570, 0 },
30093 		{ "VF", 0, 8 },
30094 	{ "MPS_CLS_SRAM_L", 0xe578, 0 },
30109 		{ "VF", 0, 8 },
30110 	{ "MPS_CLS_SRAM_L", 0xe580, 0 },
30125 		{ "VF", 0, 8 },
30126 	{ "MPS_CLS_SRAM_L", 0xe588, 0 },
30141 		{ "VF", 0, 8 },
30142 	{ "MPS_CLS_SRAM_L", 0xe590, 0 },
30157 		{ "VF", 0, 8 },
30158 	{ "MPS_CLS_SRAM_L", 0xe598, 0 },
30173 		{ "VF", 0, 8 },
30174 	{ "MPS_CLS_SRAM_L", 0xe5a0, 0 },
30189 		{ "VF", 0, 8 },
30190 	{ "MPS_CLS_SRAM_L", 0xe5a8, 0 },
30205 		{ "VF", 0, 8 },
30206 	{ "MPS_CLS_SRAM_L", 0xe5b0, 0 },
30221 		{ "VF", 0, 8 },
30222 	{ "MPS_CLS_SRAM_L", 0xe5b8, 0 },
30237 		{ "VF", 0, 8 },
30238 	{ "MPS_CLS_SRAM_L", 0xe5c0, 0 },
30253 		{ "VF", 0, 8 },
30254 	{ "MPS_CLS_SRAM_L", 0xe5c8, 0 },
30269 		{ "VF", 0, 8 },
30270 	{ "MPS_CLS_SRAM_L", 0xe5d0, 0 },
30285 		{ "VF", 0, 8 },
30286 	{ "MPS_CLS_SRAM_L", 0xe5d8, 0 },
30301 		{ "VF", 0, 8 },
30302 	{ "MPS_CLS_SRAM_L", 0xe5e0, 0 },
30317 		{ "VF", 0, 8 },
30318 	{ "MPS_CLS_SRAM_L", 0xe5e8, 0 },
30333 		{ "VF", 0, 8 },
30334 	{ "MPS_CLS_SRAM_L", 0xe5f0, 0 },
30349 		{ "VF", 0, 8 },
30350 	{ "MPS_CLS_SRAM_L", 0xe5f8, 0 },
30365 		{ "VF", 0, 8 },
30366 	{ "MPS_CLS_SRAM_L", 0xe600, 0 },
30381 		{ "VF", 0, 8 },
30382 	{ "MPS_CLS_SRAM_L", 0xe608, 0 },
30397 		{ "VF", 0, 8 },
30398 	{ "MPS_CLS_SRAM_L", 0xe610, 0 },
30413 		{ "VF", 0, 8 },
30414 	{ "MPS_CLS_SRAM_L", 0xe618, 0 },
30429 		{ "VF", 0, 8 },
30430 	{ "MPS_CLS_SRAM_L", 0xe620, 0 },
30445 		{ "VF", 0, 8 },
30446 	{ "MPS_CLS_SRAM_L", 0xe628, 0 },
30461 		{ "VF", 0, 8 },
30462 	{ "MPS_CLS_SRAM_L", 0xe630, 0 },
30477 		{ "VF", 0, 8 },
30478 	{ "MPS_CLS_SRAM_L", 0xe638, 0 },
30493 		{ "VF", 0, 8 },
30494 	{ "MPS_CLS_SRAM_L", 0xe640, 0 },
30509 		{ "VF", 0, 8 },
30510 	{ "MPS_CLS_SRAM_L", 0xe648, 0 },
30525 		{ "VF", 0, 8 },
30526 	{ "MPS_CLS_SRAM_L", 0xe650, 0 },
30541 		{ "VF", 0, 8 },
30542 	{ "MPS_CLS_SRAM_L", 0xe658, 0 },
30557 		{ "VF", 0, 8 },
30558 	{ "MPS_CLS_SRAM_L", 0xe660, 0 },
30573 		{ "VF", 0, 8 },
30574 	{ "MPS_CLS_SRAM_L", 0xe668, 0 },
30589 		{ "VF", 0, 8 },
30590 	{ "MPS_CLS_SRAM_L", 0xe670, 0 },
30605 		{ "VF", 0, 8 },
30606 	{ "MPS_CLS_SRAM_L", 0xe678, 0 },
30621 		{ "VF", 0, 8 },
30622 	{ "MPS_CLS_SRAM_L", 0xe680, 0 },
30637 		{ "VF", 0, 8 },
30638 	{ "MPS_CLS_SRAM_L", 0xe688, 0 },
30653 		{ "VF", 0, 8 },
30654 	{ "MPS_CLS_SRAM_L", 0xe690, 0 },
30669 		{ "VF", 0, 8 },
30670 	{ "MPS_CLS_SRAM_L", 0xe698, 0 },
30685 		{ "VF", 0, 8 },
30686 	{ "MPS_CLS_SRAM_L", 0xe6a0, 0 },
30701 		{ "VF", 0, 8 },
30702 	{ "MPS_CLS_SRAM_L", 0xe6a8, 0 },
30717 		{ "VF", 0, 8 },
30718 	{ "MPS_CLS_SRAM_L", 0xe6b0, 0 },
30733 		{ "VF", 0, 8 },
30734 	{ "MPS_CLS_SRAM_L", 0xe6b8, 0 },
30749 		{ "VF", 0, 8 },
30750 	{ "MPS_CLS_SRAM_L", 0xe6c0, 0 },
30765 		{ "VF", 0, 8 },
30766 	{ "MPS_CLS_SRAM_L", 0xe6c8, 0 },
30781 		{ "VF", 0, 8 },
30782 	{ "MPS_CLS_SRAM_L", 0xe6d0, 0 },
30797 		{ "VF", 0, 8 },
30798 	{ "MPS_CLS_SRAM_L", 0xe6d8, 0 },
30813 		{ "VF", 0, 8 },
30814 	{ "MPS_CLS_SRAM_L", 0xe6e0, 0 },
30829 		{ "VF", 0, 8 },
30830 	{ "MPS_CLS_SRAM_L", 0xe6e8, 0 },
30845 		{ "VF", 0, 8 },
30846 	{ "MPS_CLS_SRAM_L", 0xe6f0, 0 },
30861 		{ "VF", 0, 8 },
30862 	{ "MPS_CLS_SRAM_L", 0xe6f8, 0 },
30877 		{ "VF", 0, 8 },
30878 	{ "MPS_CLS_SRAM_L", 0xe700, 0 },
30893 		{ "VF", 0, 8 },
30894 	{ "MPS_CLS_SRAM_L", 0xe708, 0 },
30909 		{ "VF", 0, 8 },
30910 	{ "MPS_CLS_SRAM_L", 0xe710, 0 },
30925 		{ "VF", 0, 8 },
30926 	{ "MPS_CLS_SRAM_L", 0xe718, 0 },
30941 		{ "VF", 0, 8 },
30942 	{ "MPS_CLS_SRAM_L", 0xe720, 0 },
30957 		{ "VF", 0, 8 },
30958 	{ "MPS_CLS_SRAM_L", 0xe728, 0 },
30973 		{ "VF", 0, 8 },
30974 	{ "MPS_CLS_SRAM_L", 0xe730, 0 },
30989 		{ "VF", 0, 8 },
30990 	{ "MPS_CLS_SRAM_L", 0xe738, 0 },
31005 		{ "VF", 0, 8 },
31006 	{ "MPS_CLS_SRAM_L", 0xe740, 0 },
31021 		{ "VF", 0, 8 },
31022 	{ "MPS_CLS_SRAM_L", 0xe748, 0 },
31037 		{ "VF", 0, 8 },
31038 	{ "MPS_CLS_SRAM_L", 0xe750, 0 },
31053 		{ "VF", 0, 8 },
31054 	{ "MPS_CLS_SRAM_L", 0xe758, 0 },
31069 		{ "VF", 0, 8 },
31070 	{ "MPS_CLS_SRAM_L", 0xe760, 0 },
31085 		{ "VF", 0, 8 },
31086 	{ "MPS_CLS_SRAM_L", 0xe768, 0 },
31101 		{ "VF", 0, 8 },
31102 	{ "MPS_CLS_SRAM_L", 0xe770, 0 },
31117 		{ "VF", 0, 8 },
31118 	{ "MPS_CLS_SRAM_L", 0xe778, 0 },
31133 		{ "VF", 0, 8 },
31134 	{ "MPS_CLS_SRAM_L", 0xe780, 0 },
31149 		{ "VF", 0, 8 },
31150 	{ "MPS_CLS_SRAM_L", 0xe788, 0 },
31165 		{ "VF", 0, 8 },
31166 	{ "MPS_CLS_SRAM_L", 0xe790, 0 },
31181 		{ "VF", 0, 8 },
31182 	{ "MPS_CLS_SRAM_L", 0xe798, 0 },
31197 		{ "VF", 0, 8 },
31198 	{ "MPS_CLS_SRAM_L", 0xe7a0, 0 },
31213 		{ "VF", 0, 8 },
31214 	{ "MPS_CLS_SRAM_L", 0xe7a8, 0 },
31229 		{ "VF", 0, 8 },
31230 	{ "MPS_CLS_SRAM_L", 0xe7b0, 0 },
31245 		{ "VF", 0, 8 },
31246 	{ "MPS_CLS_SRAM_L", 0xe7b8, 0 },
31261 		{ "VF", 0, 8 },
31262 	{ "MPS_CLS_SRAM_L", 0xe7c0, 0 },
31277 		{ "VF", 0, 8 },
31278 	{ "MPS_CLS_SRAM_L", 0xe7c8, 0 },
31293 		{ "VF", 0, 8 },
31294 	{ "MPS_CLS_SRAM_L", 0xe7d0, 0 },
31309 		{ "VF", 0, 8 },
31310 	{ "MPS_CLS_SRAM_L", 0xe7d8, 0 },
31325 		{ "VF", 0, 8 },
31326 	{ "MPS_CLS_SRAM_L", 0xe7e0, 0 },
31341 		{ "VF", 0, 8 },
31342 	{ "MPS_CLS_SRAM_L", 0xe7e8, 0 },
31357 		{ "VF", 0, 8 },
31358 	{ "MPS_CLS_SRAM_L", 0xe7f0, 0 },
31373 		{ "VF", 0, 8 },
31374 	{ "MPS_CLS_SRAM_L", 0xe7f8, 0 },
31389 		{ "VF", 0, 8 },
31390 	{ "MPS_CLS_SRAM_L", 0xe800, 0 },
31405 		{ "VF", 0, 8 },
31406 	{ "MPS_CLS_SRAM_L", 0xe808, 0 },
31421 		{ "VF", 0, 8 },
31422 	{ "MPS_CLS_SRAM_L", 0xe810, 0 },
31437 		{ "VF", 0, 8 },
31438 	{ "MPS_CLS_SRAM_L", 0xe818, 0 },
31453 		{ "VF", 0, 8 },
31454 	{ "MPS_CLS_SRAM_L", 0xe820, 0 },
31469 		{ "VF", 0, 8 },
31470 	{ "MPS_CLS_SRAM_L", 0xe828, 0 },
31485 		{ "VF", 0, 8 },
31486 	{ "MPS_CLS_SRAM_L", 0xe830, 0 },
31501 		{ "VF", 0, 8 },
31502 	{ "MPS_CLS_SRAM_L", 0xe838, 0 },
31517 		{ "VF", 0, 8 },
31518 	{ "MPS_CLS_SRAM_L", 0xe840, 0 },
31533 		{ "VF", 0, 8 },
31534 	{ "MPS_CLS_SRAM_L", 0xe848, 0 },
31549 		{ "VF", 0, 8 },
31550 	{ "MPS_CLS_SRAM_L", 0xe850, 0 },
31565 		{ "VF", 0, 8 },
31566 	{ "MPS_CLS_SRAM_L", 0xe858, 0 },
31581 		{ "VF", 0, 8 },
31582 	{ "MPS_CLS_SRAM_L", 0xe860, 0 },
31597 		{ "VF", 0, 8 },
31598 	{ "MPS_CLS_SRAM_L", 0xe868, 0 },
31613 		{ "VF", 0, 8 },
31614 	{ "MPS_CLS_SRAM_L", 0xe870, 0 },
31629 		{ "VF", 0, 8 },
31630 	{ "MPS_CLS_SRAM_L", 0xe878, 0 },
31645 		{ "VF", 0, 8 },
31646 	{ "MPS_CLS_SRAM_L", 0xe880, 0 },
31661 		{ "VF", 0, 8 },
31662 	{ "MPS_CLS_SRAM_L", 0xe888, 0 },
31677 		{ "VF", 0, 8 },
31678 	{ "MPS_CLS_SRAM_L", 0xe890, 0 },
31693 		{ "VF", 0, 8 },
31694 	{ "MPS_CLS_SRAM_L", 0xe898, 0 },
31709 		{ "VF", 0, 8 },
31710 	{ "MPS_CLS_SRAM_L", 0xe8a0, 0 },
31725 		{ "VF", 0, 8 },
31726 	{ "MPS_CLS_SRAM_L", 0xe8a8, 0 },
31741 		{ "VF", 0, 8 },
31742 	{ "MPS_CLS_SRAM_L", 0xe8b0, 0 },
31757 		{ "VF", 0, 8 },
31758 	{ "MPS_CLS_SRAM_L", 0xe8b8, 0 },
31773 		{ "VF", 0, 8 },
31774 	{ "MPS_CLS_SRAM_L", 0xe8c0, 0 },
31789 		{ "VF", 0, 8 },
31790 	{ "MPS_CLS_SRAM_L", 0xe8c8, 0 },
31805 		{ "VF", 0, 8 },
31806 	{ "MPS_CLS_SRAM_L", 0xe8d0, 0 },
31821 		{ "VF", 0, 8 },
31822 	{ "MPS_CLS_SRAM_L", 0xe8d8, 0 },
31837 		{ "VF", 0, 8 },
31838 	{ "MPS_CLS_SRAM_L", 0xe8e0, 0 },
31853 		{ "VF", 0, 8 },
31854 	{ "MPS_CLS_SRAM_L", 0xe8e8, 0 },
31869 		{ "VF", 0, 8 },
31870 	{ "MPS_CLS_SRAM_L", 0xe8f0, 0 },
31885 		{ "VF", 0, 8 },
31886 	{ "MPS_CLS_SRAM_L", 0xe8f8, 0 },
31901 		{ "VF", 0, 8 },
31902 	{ "MPS_CLS_SRAM_L", 0xe900, 0 },
31917 		{ "VF", 0, 8 },
31918 	{ "MPS_CLS_SRAM_L", 0xe908, 0 },
31933 		{ "VF", 0, 8 },
31934 	{ "MPS_CLS_SRAM_L", 0xe910, 0 },
31949 		{ "VF", 0, 8 },
31950 	{ "MPS_CLS_SRAM_L", 0xe918, 0 },
31965 		{ "VF", 0, 8 },
31966 	{ "MPS_CLS_SRAM_L", 0xe920, 0 },
31981 		{ "VF", 0, 8 },
31982 	{ "MPS_CLS_SRAM_L", 0xe928, 0 },
31997 		{ "VF", 0, 8 },
31998 	{ "MPS_CLS_SRAM_L", 0xe930, 0 },
32013 		{ "VF", 0, 8 },
32014 	{ "MPS_CLS_SRAM_L", 0xe938, 0 },
32029 		{ "VF", 0, 8 },
32030 	{ "MPS_CLS_SRAM_L", 0xe940, 0 },
32045 		{ "VF", 0, 8 },
32046 	{ "MPS_CLS_SRAM_L", 0xe948, 0 },
32061 		{ "VF", 0, 8 },
32062 	{ "MPS_CLS_SRAM_L", 0xe950, 0 },
32077 		{ "VF", 0, 8 },
32078 	{ "MPS_CLS_SRAM_L", 0xe958, 0 },
32093 		{ "VF", 0, 8 },
32094 	{ "MPS_CLS_SRAM_L", 0xe960, 0 },
32109 		{ "VF", 0, 8 },
32110 	{ "MPS_CLS_SRAM_L", 0xe968, 0 },
32125 		{ "VF", 0, 8 },
32126 	{ "MPS_CLS_SRAM_L", 0xe970, 0 },
32141 		{ "VF", 0, 8 },
32142 	{ "MPS_CLS_SRAM_L", 0xe978, 0 },
32157 		{ "VF", 0, 8 },
32158 	{ "MPS_CLS_SRAM_L", 0xe980, 0 },
32173 		{ "VF", 0, 8 },
32174 	{ "MPS_CLS_SRAM_L", 0xe988, 0 },
32189 		{ "VF", 0, 8 },
32190 	{ "MPS_CLS_SRAM_L", 0xe990, 0 },
32205 		{ "VF", 0, 8 },
32206 	{ "MPS_CLS_SRAM_L", 0xe998, 0 },
32221 		{ "VF", 0, 8 },
32222 	{ "MPS_CLS_SRAM_L", 0xe9a0, 0 },
32237 		{ "VF", 0, 8 },
32238 	{ "MPS_CLS_SRAM_L", 0xe9a8, 0 },
32253 		{ "VF", 0, 8 },
32254 	{ "MPS_CLS_SRAM_L", 0xe9b0, 0 },
32269 		{ "VF", 0, 8 },
32270 	{ "MPS_CLS_SRAM_L", 0xe9b8, 0 },
32285 		{ "VF", 0, 8 },
32286 	{ "MPS_CLS_SRAM_L", 0xe9c0, 0 },
32301 		{ "VF", 0, 8 },
32302 	{ "MPS_CLS_SRAM_L", 0xe9c8, 0 },
32317 		{ "VF", 0, 8 },
32318 	{ "MPS_CLS_SRAM_L", 0xe9d0, 0 },
32333 		{ "VF", 0, 8 },
32334 	{ "MPS_CLS_SRAM_L", 0xe9d8, 0 },
32349 		{ "VF", 0, 8 },
32350 	{ "MPS_CLS_SRAM_L", 0xe9e0, 0 },
32365 		{ "VF", 0, 8 },
32366 	{ "MPS_CLS_SRAM_L", 0xe9e8, 0 },
32381 		{ "VF", 0, 8 },
32382 	{ "MPS_CLS_SRAM_L", 0xe9f0, 0 },
32397 		{ "VF", 0, 8 },
32398 	{ "MPS_CLS_SRAM_L", 0xe9f8, 0 },
32413 		{ "VF", 0, 8 },
32414 	{ "MPS_CLS_SRAM_L", 0xea00, 0 },
32429 		{ "VF", 0, 8 },
32430 	{ "MPS_CLS_SRAM_L", 0xea08, 0 },
32445 		{ "VF", 0, 8 },
32446 	{ "MPS_CLS_SRAM_L", 0xea10, 0 },
32461 		{ "VF", 0, 8 },
32462 	{ "MPS_CLS_SRAM_L", 0xea18, 0 },
32477 		{ "VF", 0, 8 },
32478 	{ "MPS_CLS_SRAM_L", 0xea20, 0 },
32493 		{ "VF", 0, 8 },
32494 	{ "MPS_CLS_SRAM_L", 0xea28, 0 },
32509 		{ "VF", 0, 8 },
32510 	{ "MPS_CLS_SRAM_L", 0xea30, 0 },
32525 		{ "VF", 0, 8 },
32526 	{ "MPS_CLS_SRAM_L", 0xea38, 0 },
32541 		{ "VF", 0, 8 },
32542 	{ "MPS_CLS_SRAM_L", 0xea40, 0 },
32557 		{ "VF", 0, 8 },
32558 	{ "MPS_CLS_SRAM_L", 0xea48, 0 },
32573 		{ "VF", 0, 8 },
32574 	{ "MPS_CLS_SRAM_L", 0xea50, 0 },
32589 		{ "VF", 0, 8 },
32590 	{ "MPS_CLS_SRAM_L", 0xea58, 0 },
32605 		{ "VF", 0, 8 },
32606 	{ "MPS_CLS_SRAM_L", 0xea60, 0 },
32621 		{ "VF", 0, 8 },
32622 	{ "MPS_CLS_SRAM_L", 0xea68, 0 },
32637 		{ "VF", 0, 8 },
32638 	{ "MPS_CLS_SRAM_L", 0xea70, 0 },
32653 		{ "VF", 0, 8 },
32654 	{ "MPS_CLS_SRAM_L", 0xea78, 0 },
32669 		{ "VF", 0, 8 },
32670 	{ "MPS_CLS_SRAM_L", 0xea80, 0 },
32685 		{ "VF", 0, 8 },
32686 	{ "MPS_CLS_SRAM_L", 0xea88, 0 },
32701 		{ "VF", 0, 8 },
32702 	{ "MPS_CLS_SRAM_L", 0xea90, 0 },
32717 		{ "VF", 0, 8 },
32718 	{ "MPS_CLS_SRAM_L", 0xea98, 0 },
32733 		{ "VF", 0, 8 },
32734 	{ "MPS_CLS_SRAM_L", 0xeaa0, 0 },
32749 		{ "VF", 0, 8 },
32750 	{ "MPS_CLS_SRAM_L", 0xeaa8, 0 },
32765 		{ "VF", 0, 8 },
32766 	{ "MPS_CLS_SRAM_L", 0xeab0, 0 },
32781 		{ "VF", 0, 8 },
32782 	{ "MPS_CLS_SRAM_L", 0xeab8, 0 },
32797 		{ "VF", 0, 8 },
32798 	{ "MPS_CLS_SRAM_L", 0xeac0, 0 },
32813 		{ "VF", 0, 8 },
32814 	{ "MPS_CLS_SRAM_L", 0xeac8, 0 },
32829 		{ "VF", 0, 8 },
32830 	{ "MPS_CLS_SRAM_L", 0xead0, 0 },
32845 		{ "VF", 0, 8 },
32846 	{ "MPS_CLS_SRAM_L", 0xead8, 0 },
32861 		{ "VF", 0, 8 },
32862 	{ "MPS_CLS_SRAM_L", 0xeae0, 0 },
32877 		{ "VF", 0, 8 },
32878 	{ "MPS_CLS_SRAM_L", 0xeae8, 0 },
32893 		{ "VF", 0, 8 },
32894 	{ "MPS_CLS_SRAM_L", 0xeaf0, 0 },
32909 		{ "VF", 0, 8 },
32910 	{ "MPS_CLS_SRAM_L", 0xeaf8, 0 },
32925 		{ "VF", 0, 8 },
32926 	{ "MPS_CLS_SRAM_L", 0xeb00, 0 },
32941 		{ "VF", 0, 8 },
32942 	{ "MPS_CLS_SRAM_L", 0xeb08, 0 },
32957 		{ "VF", 0, 8 },
32958 	{ "MPS_CLS_SRAM_L", 0xeb10, 0 },
32973 		{ "VF", 0, 8 },
32974 	{ "MPS_CLS_SRAM_L", 0xeb18, 0 },
32989 		{ "VF", 0, 8 },
32990 	{ "MPS_CLS_SRAM_L", 0xeb20, 0 },
33005 		{ "VF", 0, 8 },
33006 	{ "MPS_CLS_SRAM_L", 0xeb28, 0 },
33021 		{ "VF", 0, 8 },
33022 	{ "MPS_CLS_SRAM_L", 0xeb30, 0 },
33037 		{ "VF", 0, 8 },
33038 	{ "MPS_CLS_SRAM_L", 0xeb38, 0 },
33053 		{ "VF", 0, 8 },
33054 	{ "MPS_CLS_SRAM_L", 0xeb40, 0 },
33069 		{ "VF", 0, 8 },
33070 	{ "MPS_CLS_SRAM_L", 0xeb48, 0 },
33085 		{ "VF", 0, 8 },
33086 	{ "MPS_CLS_SRAM_L", 0xeb50, 0 },
33101 		{ "VF", 0, 8 },
33102 	{ "MPS_CLS_SRAM_L", 0xeb58, 0 },
33117 		{ "VF", 0, 8 },
33118 	{ "MPS_CLS_SRAM_L", 0xeb60, 0 },
33133 		{ "VF", 0, 8 },
33134 	{ "MPS_CLS_SRAM_L", 0xeb68, 0 },
33149 		{ "VF", 0, 8 },
33150 	{ "MPS_CLS_SRAM_L", 0xeb70, 0 },
33165 		{ "VF", 0, 8 },
33166 	{ "MPS_CLS_SRAM_L", 0xeb78, 0 },
33181 		{ "VF", 0, 8 },
33182 	{ "MPS_CLS_SRAM_L", 0xeb80, 0 },
33197 		{ "VF", 0, 8 },
33198 	{ "MPS_CLS_SRAM_L", 0xeb88, 0 },
33213 		{ "VF", 0, 8 },
33214 	{ "MPS_CLS_SRAM_L", 0xeb90, 0 },
33229 		{ "VF", 0, 8 },
33230 	{ "MPS_CLS_SRAM_L", 0xeb98, 0 },
33245 		{ "VF", 0, 8 },
33246 	{ "MPS_CLS_SRAM_L", 0xeba0, 0 },
33261 		{ "VF", 0, 8 },
33262 	{ "MPS_CLS_SRAM_L", 0xeba8, 0 },
33277 		{ "VF", 0, 8 },
33278 	{ "MPS_CLS_SRAM_L", 0xebb0, 0 },
33293 		{ "VF", 0, 8 },
33294 	{ "MPS_CLS_SRAM_L", 0xebb8, 0 },
33309 		{ "VF", 0, 8 },
33310 	{ "MPS_CLS_SRAM_L", 0xebc0, 0 },
33325 		{ "VF", 0, 8 },
33326 	{ "MPS_CLS_SRAM_L", 0xebc8, 0 },
33341 		{ "VF", 0, 8 },
33342 	{ "MPS_CLS_SRAM_L", 0xebd0, 0 },
33357 		{ "VF", 0, 8 },
33358 	{ "MPS_CLS_SRAM_L", 0xebd8, 0 },
33373 		{ "VF", 0, 8 },
33374 	{ "MPS_CLS_SRAM_L", 0xebe0, 0 },
33389 		{ "VF", 0, 8 },
33390 	{ "MPS_CLS_SRAM_L", 0xebe8, 0 },
33405 		{ "VF", 0, 8 },
33406 	{ "MPS_CLS_SRAM_L", 0xebf0, 0 },
33421 		{ "VF", 0, 8 },
33422 	{ "MPS_CLS_SRAM_L", 0xebf8, 0 },
33437 		{ "VF", 0, 8 },
33438 	{ "MPS_CLS_SRAM_L", 0xec00, 0 },
33453 		{ "VF", 0, 8 },
33454 	{ "MPS_CLS_SRAM_L", 0xec08, 0 },
33469 		{ "VF", 0, 8 },
33470 	{ "MPS_CLS_SRAM_L", 0xec10, 0 },
33485 		{ "VF", 0, 8 },
33486 	{ "MPS_CLS_SRAM_L", 0xec18, 0 },
33501 		{ "VF", 0, 8 },
33502 	{ "MPS_CLS_SRAM_L", 0xec20, 0 },
33517 		{ "VF", 0, 8 },
33518 	{ "MPS_CLS_SRAM_L", 0xec28, 0 },
33533 		{ "VF", 0, 8 },
33534 	{ "MPS_CLS_SRAM_L", 0xec30, 0 },
33549 		{ "VF", 0, 8 },
33550 	{ "MPS_CLS_SRAM_L", 0xec38, 0 },
33565 		{ "VF", 0, 8 },
33566 	{ "MPS_CLS_SRAM_L", 0xec40, 0 },
33581 		{ "VF", 0, 8 },
33582 	{ "MPS_CLS_SRAM_L", 0xec48, 0 },
33597 		{ "VF", 0, 8 },
33598 	{ "MPS_CLS_SRAM_L", 0xec50, 0 },
33613 		{ "VF", 0, 8 },
33614 	{ "MPS_CLS_SRAM_L", 0xec58, 0 },
33629 		{ "VF", 0, 8 },
33630 	{ "MPS_CLS_SRAM_L", 0xec60, 0 },
33645 		{ "VF", 0, 8 },
33646 	{ "MPS_CLS_SRAM_L", 0xec68, 0 },
33661 		{ "VF", 0, 8 },
33662 	{ "MPS_CLS_SRAM_L", 0xec70, 0 },
33677 		{ "VF", 0, 8 },
33678 	{ "MPS_CLS_SRAM_L", 0xec78, 0 },
33693 		{ "VF", 0, 8 },
33694 	{ "MPS_CLS_SRAM_L", 0xec80, 0 },
33709 		{ "VF", 0, 8 },
33710 	{ "MPS_CLS_SRAM_L", 0xec88, 0 },
33725 		{ "VF", 0, 8 },
33726 	{ "MPS_CLS_SRAM_L", 0xec90, 0 },
33741 		{ "VF", 0, 8 },
33742 	{ "MPS_CLS_SRAM_L", 0xec98, 0 },
33757 		{ "VF", 0, 8 },
33758 	{ "MPS_CLS_SRAM_L", 0xeca0, 0 },
33773 		{ "VF", 0, 8 },
33774 	{ "MPS_CLS_SRAM_L", 0xeca8, 0 },
33789 		{ "VF", 0, 8 },
33790 	{ "MPS_CLS_SRAM_L", 0xecb0, 0 },
33805 		{ "VF", 0, 8 },
33806 	{ "MPS_CLS_SRAM_L", 0xecb8, 0 },
33821 		{ "VF", 0, 8 },
33822 	{ "MPS_CLS_SRAM_L", 0xecc0, 0 },
33837 		{ "VF", 0, 8 },
33838 	{ "MPS_CLS_SRAM_L", 0xecc8, 0 },
33853 		{ "VF", 0, 8 },
33854 	{ "MPS_CLS_SRAM_L", 0xecd0, 0 },
33869 		{ "VF", 0, 8 },
33870 	{ "MPS_CLS_SRAM_L", 0xecd8, 0 },
33885 		{ "VF", 0, 8 },
33886 	{ "MPS_CLS_SRAM_L", 0xece0, 0 },
33901 		{ "VF", 0, 8 },
33902 	{ "MPS_CLS_SRAM_L", 0xece8, 0 },
33917 		{ "VF", 0, 8 },
33918 	{ "MPS_CLS_SRAM_L", 0xecf0, 0 },
33933 		{ "VF", 0, 8 },
33934 	{ "MPS_CLS_SRAM_L", 0xecf8, 0 },
33949 		{ "VF", 0, 8 },
33950 	{ "MPS_CLS_SRAM_L", 0xed00, 0 },
33965 		{ "VF", 0, 8 },
33966 	{ "MPS_CLS_SRAM_L", 0xed08, 0 },
33981 		{ "VF", 0, 8 },
33982 	{ "MPS_CLS_SRAM_L", 0xed10, 0 },
33997 		{ "VF", 0, 8 },
33998 	{ "MPS_CLS_SRAM_L", 0xed18, 0 },
34013 		{ "VF", 0, 8 },
34014 	{ "MPS_CLS_SRAM_L", 0xed20, 0 },
34029 		{ "VF", 0, 8 },
34030 	{ "MPS_CLS_SRAM_L", 0xed28, 0 },
34045 		{ "VF", 0, 8 },
34046 	{ "MPS_CLS_SRAM_L", 0xed30, 0 },
34061 		{ "VF", 0, 8 },
34062 	{ "MPS_CLS_SRAM_L", 0xed38, 0 },
34077 		{ "VF", 0, 8 },
34078 	{ "MPS_CLS_SRAM_L", 0xed40, 0 },
34093 		{ "VF", 0, 8 },
34094 	{ "MPS_CLS_SRAM_L", 0xed48, 0 },
34109 		{ "VF", 0, 8 },
34110 	{ "MPS_CLS_SRAM_L", 0xed50, 0 },
34125 		{ "VF", 0, 8 },
34126 	{ "MPS_CLS_SRAM_L", 0xed58, 0 },
34141 		{ "VF", 0, 8 },
34142 	{ "MPS_CLS_SRAM_L", 0xed60, 0 },
34157 		{ "VF", 0, 8 },
34158 	{ "MPS_CLS_SRAM_L", 0xed68, 0 },
34173 		{ "VF", 0, 8 },
34174 	{ "MPS_CLS_SRAM_L", 0xed70, 0 },
34189 		{ "VF", 0, 8 },
34190 	{ "MPS_CLS_SRAM_L", 0xed78, 0 },
34205 		{ "VF", 0, 8 },
34206 	{ "MPS_CLS_SRAM_L", 0xed80, 0 },
34221 		{ "VF", 0, 8 },
34222 	{ "MPS_CLS_SRAM_L", 0xed88, 0 },
34237 		{ "VF", 0, 8 },
34238 	{ "MPS_CLS_SRAM_L", 0xed90, 0 },
34253 		{ "VF", 0, 8 },
34254 	{ "MPS_CLS_SRAM_L", 0xed98, 0 },
34269 		{ "VF", 0, 8 },
34270 	{ "MPS_CLS_SRAM_L", 0xeda0, 0 },
34285 		{ "VF", 0, 8 },
34286 	{ "MPS_CLS_SRAM_L", 0xeda8, 0 },
34301 		{ "VF", 0, 8 },
34302 	{ "MPS_CLS_SRAM_L", 0xedb0, 0 },
34317 		{ "VF", 0, 8 },
34318 	{ "MPS_CLS_SRAM_L", 0xedb8, 0 },
34333 		{ "VF", 0, 8 },
34334 	{ "MPS_CLS_SRAM_L", 0xedc0, 0 },
34349 		{ "VF", 0, 8 },
34350 	{ "MPS_CLS_SRAM_L", 0xedc8, 0 },
34365 		{ "VF", 0, 8 },
34366 	{ "MPS_CLS_SRAM_L", 0xedd0, 0 },
34381 		{ "VF", 0, 8 },
34382 	{ "MPS_CLS_SRAM_L", 0xedd8, 0 },
34397 		{ "VF", 0, 8 },
34398 	{ "MPS_CLS_SRAM_L", 0xede0, 0 },
34413 		{ "VF", 0, 8 },
34414 	{ "MPS_CLS_SRAM_L", 0xede8, 0 },
34429 		{ "VF", 0, 8 },
34430 	{ "MPS_CLS_SRAM_L", 0xedf0, 0 },
34445 		{ "VF", 0, 8 },
34446 	{ "MPS_CLS_SRAM_L", 0xedf8, 0 },
34461 		{ "VF", 0, 8 },
34462 	{ "MPS_CLS_SRAM_L", 0xee00, 0 },
34477 		{ "VF", 0, 8 },
34478 	{ "MPS_CLS_SRAM_L", 0xee08, 0 },
34493 		{ "VF", 0, 8 },
34494 	{ "MPS_CLS_SRAM_L", 0xee10, 0 },
34509 		{ "VF", 0, 8 },
34510 	{ "MPS_CLS_SRAM_L", 0xee18, 0 },
34525 		{ "VF", 0, 8 },
34526 	{ "MPS_CLS_SRAM_L", 0xee20, 0 },
34541 		{ "VF", 0, 8 },
34542 	{ "MPS_CLS_SRAM_L", 0xee28, 0 },
34557 		{ "VF", 0, 8 },
34558 	{ "MPS_CLS_SRAM_L", 0xee30, 0 },
34573 		{ "VF", 0, 8 },
34574 	{ "MPS_CLS_SRAM_L", 0xee38, 0 },
34589 		{ "VF", 0, 8 },
34590 	{ "MPS_CLS_SRAM_L", 0xee40, 0 },
34605 		{ "VF", 0, 8 },
34606 	{ "MPS_CLS_SRAM_L", 0xee48, 0 },
34621 		{ "VF", 0, 8 },
34622 	{ "MPS_CLS_SRAM_L", 0xee50, 0 },
34637 		{ "VF", 0, 8 },
34638 	{ "MPS_CLS_SRAM_L", 0xee58, 0 },
34653 		{ "VF", 0, 8 },
34654 	{ "MPS_CLS_SRAM_L", 0xee60, 0 },
34669 		{ "VF", 0, 8 },
34670 	{ "MPS_CLS_SRAM_L", 0xee68, 0 },
34685 		{ "VF", 0, 8 },
34686 	{ "MPS_CLS_SRAM_L", 0xee70, 0 },
34701 		{ "VF", 0, 8 },
34702 	{ "MPS_CLS_SRAM_L", 0xee78, 0 },
34717 		{ "VF", 0, 8 },
34718 	{ "MPS_CLS_SRAM_L", 0xee80, 0 },
34733 		{ "VF", 0, 8 },
34734 	{ "MPS_CLS_SRAM_L", 0xee88, 0 },
34749 		{ "VF", 0, 8 },
34750 	{ "MPS_CLS_SRAM_L", 0xee90, 0 },
34765 		{ "VF", 0, 8 },
34766 	{ "MPS_CLS_SRAM_L", 0xee98, 0 },
34781 		{ "VF", 0, 8 },
34782 	{ "MPS_CLS_SRAM_L", 0xeea0, 0 },
34797 		{ "VF", 0, 8 },
34798 	{ "MPS_CLS_SRAM_L", 0xeea8, 0 },
34813 		{ "VF", 0, 8 },
34814 	{ "MPS_CLS_SRAM_L", 0xeeb0, 0 },
34829 		{ "VF", 0, 8 },
34830 	{ "MPS_CLS_SRAM_L", 0xeeb8, 0 },
34845 		{ "VF", 0, 8 },
34846 	{ "MPS_CLS_SRAM_L", 0xeec0, 0 },
34861 		{ "VF", 0, 8 },
34862 	{ "MPS_CLS_SRAM_L", 0xeec8, 0 },
34877 		{ "VF", 0, 8 },
34878 	{ "MPS_CLS_SRAM_L", 0xeed0, 0 },
34893 		{ "VF", 0, 8 },
34894 	{ "MPS_CLS_SRAM_L", 0xeed8, 0 },
34909 		{ "VF", 0, 8 },
34910 	{ "MPS_CLS_SRAM_L", 0xeee0, 0 },
34925 		{ "VF", 0, 8 },
34926 	{ "MPS_CLS_SRAM_L", 0xeee8, 0 },
34941 		{ "VF", 0, 8 },
34942 	{ "MPS_CLS_SRAM_L", 0xeef0, 0 },
34957 		{ "VF", 0, 8 },
34958 	{ "MPS_CLS_SRAM_L", 0xeef8, 0 },
34973 		{ "VF", 0, 8 },
34974 	{ "MPS_CLS_SRAM_L", 0xef00, 0 },
34989 		{ "VF", 0, 8 },
34990 	{ "MPS_CLS_SRAM_L", 0xef08, 0 },
35005 		{ "VF", 0, 8 },
35006 	{ "MPS_CLS_SRAM_L", 0xef10, 0 },
35021 		{ "VF", 0, 8 },
35022 	{ "MPS_CLS_SRAM_L", 0xef18, 0 },
35037 		{ "VF", 0, 8 },
35038 	{ "MPS_CLS_SRAM_L", 0xef20, 0 },
35053 		{ "VF", 0, 8 },
35054 	{ "MPS_CLS_SRAM_L", 0xef28, 0 },
35069 		{ "VF", 0, 8 },
35070 	{ "MPS_CLS_SRAM_L", 0xef30, 0 },
35085 		{ "VF", 0, 8 },
35086 	{ "MPS_CLS_SRAM_L", 0xef38, 0 },
35101 		{ "VF", 0, 8 },
35102 	{ "MPS_CLS_SRAM_L", 0xef40, 0 },
35117 		{ "VF", 0, 8 },
35118 	{ "MPS_CLS_SRAM_L", 0xef48, 0 },
35133 		{ "VF", 0, 8 },
35134 	{ "MPS_CLS_SRAM_L", 0xef50, 0 },
35149 		{ "VF", 0, 8 },
35150 	{ "MPS_CLS_SRAM_L", 0xef58, 0 },
35165 		{ "VF", 0, 8 },
35166 	{ "MPS_CLS_SRAM_L", 0xef60, 0 },
35181 		{ "VF", 0, 8 },
35182 	{ "MPS_CLS_SRAM_L", 0xef68, 0 },
35197 		{ "VF", 0, 8 },
35198 	{ "MPS_CLS_SRAM_L", 0xef70, 0 },
35213 		{ "VF", 0, 8 },
35214 	{ "MPS_CLS_SRAM_L", 0xef78, 0 },
35229 		{ "VF", 0, 8 },
35230 	{ "MPS_CLS_SRAM_L", 0xef80, 0 },
35245 		{ "VF", 0, 8 },
35246 	{ "MPS_CLS_SRAM_L", 0xef88, 0 },
35261 		{ "VF", 0, 8 },
35262 	{ "MPS_CLS_SRAM_L", 0xef90, 0 },
35277 		{ "VF", 0, 8 },
35278 	{ "MPS_CLS_SRAM_L", 0xef98, 0 },
35293 		{ "VF", 0, 8 },
35294 	{ "MPS_CLS_SRAM_L", 0xefa0, 0 },
35309 		{ "VF", 0, 8 },
35310 	{ "MPS_CLS_SRAM_L", 0xefa8, 0 },
35325 		{ "VF", 0, 8 },
35326 	{ "MPS_CLS_SRAM_L", 0xefb0, 0 },
35341 		{ "VF", 0, 8 },
35342 	{ "MPS_CLS_SRAM_L", 0xefb8, 0 },
35357 		{ "VF", 0, 8 },
35358 	{ "MPS_CLS_SRAM_L", 0xefc0, 0 },
35373 		{ "VF", 0, 8 },
35374 	{ "MPS_CLS_SRAM_L", 0xefc8, 0 },
35389 		{ "VF", 0, 8 },
35390 	{ "MPS_CLS_SRAM_L", 0xefd0, 0 },
35405 		{ "VF", 0, 8 },
35406 	{ "MPS_CLS_SRAM_L", 0xefd8, 0 },
35421 		{ "VF", 0, 8 },
35422 	{ "MPS_CLS_SRAM_L", 0xefe0, 0 },
35437 		{ "VF", 0, 8 },
35438 	{ "MPS_CLS_SRAM_L", 0xefe8, 0 },
35453 		{ "VF", 0, 8 },
35454 	{ "MPS_CLS_SRAM_L", 0xeff0, 0 },
35469 		{ "VF", 0, 8 },
35470 	{ "MPS_CLS_SRAM_L", 0xeff8, 0 },
35485 		{ "VF", 0, 8 },
35486 	{ "MPS_CLS_SRAM_H", 0xe004, 0 },
35491 		{ "PortMap", 0, 4 },
35492 	{ "MPS_CLS_SRAM_H", 0xe00c, 0 },
35497 		{ "PortMap", 0, 4 },
35498 	{ "MPS_CLS_SRAM_H", 0xe014, 0 },
35503 		{ "PortMap", 0, 4 },
35504 	{ "MPS_CLS_SRAM_H", 0xe01c, 0 },
35509 		{ "PortMap", 0, 4 },
35510 	{ "MPS_CLS_SRAM_H", 0xe024, 0 },
35515 		{ "PortMap", 0, 4 },
35516 	{ "MPS_CLS_SRAM_H", 0xe02c, 0 },
35521 		{ "PortMap", 0, 4 },
35522 	{ "MPS_CLS_SRAM_H", 0xe034, 0 },
35527 		{ "PortMap", 0, 4 },
35528 	{ "MPS_CLS_SRAM_H", 0xe03c, 0 },
35533 		{ "PortMap", 0, 4 },
35534 	{ "MPS_CLS_SRAM_H", 0xe044, 0 },
35539 		{ "PortMap", 0, 4 },
35540 	{ "MPS_CLS_SRAM_H", 0xe04c, 0 },
35545 		{ "PortMap", 0, 4 },
35546 	{ "MPS_CLS_SRAM_H", 0xe054, 0 },
35551 		{ "PortMap", 0, 4 },
35552 	{ "MPS_CLS_SRAM_H", 0xe05c, 0 },
35557 		{ "PortMap", 0, 4 },
35558 	{ "MPS_CLS_SRAM_H", 0xe064, 0 },
35563 		{ "PortMap", 0, 4 },
35564 	{ "MPS_CLS_SRAM_H", 0xe06c, 0 },
35569 		{ "PortMap", 0, 4 },
35570 	{ "MPS_CLS_SRAM_H", 0xe074, 0 },
35575 		{ "PortMap", 0, 4 },
35576 	{ "MPS_CLS_SRAM_H", 0xe07c, 0 },
35581 		{ "PortMap", 0, 4 },
35582 	{ "MPS_CLS_SRAM_H", 0xe084, 0 },
35587 		{ "PortMap", 0, 4 },
35588 	{ "MPS_CLS_SRAM_H", 0xe08c, 0 },
35593 		{ "PortMap", 0, 4 },
35594 	{ "MPS_CLS_SRAM_H", 0xe094, 0 },
35599 		{ "PortMap", 0, 4 },
35600 	{ "MPS_CLS_SRAM_H", 0xe09c, 0 },
35605 		{ "PortMap", 0, 4 },
35606 	{ "MPS_CLS_SRAM_H", 0xe0a4, 0 },
35611 		{ "PortMap", 0, 4 },
35612 	{ "MPS_CLS_SRAM_H", 0xe0ac, 0 },
35617 		{ "PortMap", 0, 4 },
35618 	{ "MPS_CLS_SRAM_H", 0xe0b4, 0 },
35623 		{ "PortMap", 0, 4 },
35624 	{ "MPS_CLS_SRAM_H", 0xe0bc, 0 },
35629 		{ "PortMap", 0, 4 },
35630 	{ "MPS_CLS_SRAM_H", 0xe0c4, 0 },
35635 		{ "PortMap", 0, 4 },
35636 	{ "MPS_CLS_SRAM_H", 0xe0cc, 0 },
35641 		{ "PortMap", 0, 4 },
35642 	{ "MPS_CLS_SRAM_H", 0xe0d4, 0 },
35647 		{ "PortMap", 0, 4 },
35648 	{ "MPS_CLS_SRAM_H", 0xe0dc, 0 },
35653 		{ "PortMap", 0, 4 },
35654 	{ "MPS_CLS_SRAM_H", 0xe0e4, 0 },
35659 		{ "PortMap", 0, 4 },
35660 	{ "MPS_CLS_SRAM_H", 0xe0ec, 0 },
35665 		{ "PortMap", 0, 4 },
35666 	{ "MPS_CLS_SRAM_H", 0xe0f4, 0 },
35671 		{ "PortMap", 0, 4 },
35672 	{ "MPS_CLS_SRAM_H", 0xe0fc, 0 },
35677 		{ "PortMap", 0, 4 },
35678 	{ "MPS_CLS_SRAM_H", 0xe104, 0 },
35683 		{ "PortMap", 0, 4 },
35684 	{ "MPS_CLS_SRAM_H", 0xe10c, 0 },
35689 		{ "PortMap", 0, 4 },
35690 	{ "MPS_CLS_SRAM_H", 0xe114, 0 },
35695 		{ "PortMap", 0, 4 },
35696 	{ "MPS_CLS_SRAM_H", 0xe11c, 0 },
35701 		{ "PortMap", 0, 4 },
35702 	{ "MPS_CLS_SRAM_H", 0xe124, 0 },
35707 		{ "PortMap", 0, 4 },
35708 	{ "MPS_CLS_SRAM_H", 0xe12c, 0 },
35713 		{ "PortMap", 0, 4 },
35714 	{ "MPS_CLS_SRAM_H", 0xe134, 0 },
35719 		{ "PortMap", 0, 4 },
35720 	{ "MPS_CLS_SRAM_H", 0xe13c, 0 },
35725 		{ "PortMap", 0, 4 },
35726 	{ "MPS_CLS_SRAM_H", 0xe144, 0 },
35731 		{ "PortMap", 0, 4 },
35732 	{ "MPS_CLS_SRAM_H", 0xe14c, 0 },
35737 		{ "PortMap", 0, 4 },
35738 	{ "MPS_CLS_SRAM_H", 0xe154, 0 },
35743 		{ "PortMap", 0, 4 },
35744 	{ "MPS_CLS_SRAM_H", 0xe15c, 0 },
35749 		{ "PortMap", 0, 4 },
35750 	{ "MPS_CLS_SRAM_H", 0xe164, 0 },
35755 		{ "PortMap", 0, 4 },
35756 	{ "MPS_CLS_SRAM_H", 0xe16c, 0 },
35761 		{ "PortMap", 0, 4 },
35762 	{ "MPS_CLS_SRAM_H", 0xe174, 0 },
35767 		{ "PortMap", 0, 4 },
35768 	{ "MPS_CLS_SRAM_H", 0xe17c, 0 },
35773 		{ "PortMap", 0, 4 },
35774 	{ "MPS_CLS_SRAM_H", 0xe184, 0 },
35779 		{ "PortMap", 0, 4 },
35780 	{ "MPS_CLS_SRAM_H", 0xe18c, 0 },
35785 		{ "PortMap", 0, 4 },
35786 	{ "MPS_CLS_SRAM_H", 0xe194, 0 },
35791 		{ "PortMap", 0, 4 },
35792 	{ "MPS_CLS_SRAM_H", 0xe19c, 0 },
35797 		{ "PortMap", 0, 4 },
35798 	{ "MPS_CLS_SRAM_H", 0xe1a4, 0 },
35803 		{ "PortMap", 0, 4 },
35804 	{ "MPS_CLS_SRAM_H", 0xe1ac, 0 },
35809 		{ "PortMap", 0, 4 },
35810 	{ "MPS_CLS_SRAM_H", 0xe1b4, 0 },
35815 		{ "PortMap", 0, 4 },
35816 	{ "MPS_CLS_SRAM_H", 0xe1bc, 0 },
35821 		{ "PortMap", 0, 4 },
35822 	{ "MPS_CLS_SRAM_H", 0xe1c4, 0 },
35827 		{ "PortMap", 0, 4 },
35828 	{ "MPS_CLS_SRAM_H", 0xe1cc, 0 },
35833 		{ "PortMap", 0, 4 },
35834 	{ "MPS_CLS_SRAM_H", 0xe1d4, 0 },
35839 		{ "PortMap", 0, 4 },
35840 	{ "MPS_CLS_SRAM_H", 0xe1dc, 0 },
35845 		{ "PortMap", 0, 4 },
35846 	{ "MPS_CLS_SRAM_H", 0xe1e4, 0 },
35851 		{ "PortMap", 0, 4 },
35852 	{ "MPS_CLS_SRAM_H", 0xe1ec, 0 },
35857 		{ "PortMap", 0, 4 },
35858 	{ "MPS_CLS_SRAM_H", 0xe1f4, 0 },
35863 		{ "PortMap", 0, 4 },
35864 	{ "MPS_CLS_SRAM_H", 0xe1fc, 0 },
35869 		{ "PortMap", 0, 4 },
35870 	{ "MPS_CLS_SRAM_H", 0xe204, 0 },
35875 		{ "PortMap", 0, 4 },
35876 	{ "MPS_CLS_SRAM_H", 0xe20c, 0 },
35881 		{ "PortMap", 0, 4 },
35882 	{ "MPS_CLS_SRAM_H", 0xe214, 0 },
35887 		{ "PortMap", 0, 4 },
35888 	{ "MPS_CLS_SRAM_H", 0xe21c, 0 },
35893 		{ "PortMap", 0, 4 },
35894 	{ "MPS_CLS_SRAM_H", 0xe224, 0 },
35899 		{ "PortMap", 0, 4 },
35900 	{ "MPS_CLS_SRAM_H", 0xe22c, 0 },
35905 		{ "PortMap", 0, 4 },
35906 	{ "MPS_CLS_SRAM_H", 0xe234, 0 },
35911 		{ "PortMap", 0, 4 },
35912 	{ "MPS_CLS_SRAM_H", 0xe23c, 0 },
35917 		{ "PortMap", 0, 4 },
35918 	{ "MPS_CLS_SRAM_H", 0xe244, 0 },
35923 		{ "PortMap", 0, 4 },
35924 	{ "MPS_CLS_SRAM_H", 0xe24c, 0 },
35929 		{ "PortMap", 0, 4 },
35930 	{ "MPS_CLS_SRAM_H", 0xe254, 0 },
35935 		{ "PortMap", 0, 4 },
35936 	{ "MPS_CLS_SRAM_H", 0xe25c, 0 },
35941 		{ "PortMap", 0, 4 },
35942 	{ "MPS_CLS_SRAM_H", 0xe264, 0 },
35947 		{ "PortMap", 0, 4 },
35948 	{ "MPS_CLS_SRAM_H", 0xe26c, 0 },
35953 		{ "PortMap", 0, 4 },
35954 	{ "MPS_CLS_SRAM_H", 0xe274, 0 },
35959 		{ "PortMap", 0, 4 },
35960 	{ "MPS_CLS_SRAM_H", 0xe27c, 0 },
35965 		{ "PortMap", 0, 4 },
35966 	{ "MPS_CLS_SRAM_H", 0xe284, 0 },
35971 		{ "PortMap", 0, 4 },
35972 	{ "MPS_CLS_SRAM_H", 0xe28c, 0 },
35977 		{ "PortMap", 0, 4 },
35978 	{ "MPS_CLS_SRAM_H", 0xe294, 0 },
35983 		{ "PortMap", 0, 4 },
35984 	{ "MPS_CLS_SRAM_H", 0xe29c, 0 },
35989 		{ "PortMap", 0, 4 },
35990 	{ "MPS_CLS_SRAM_H", 0xe2a4, 0 },
35995 		{ "PortMap", 0, 4 },
35996 	{ "MPS_CLS_SRAM_H", 0xe2ac, 0 },
36001 		{ "PortMap", 0, 4 },
36002 	{ "MPS_CLS_SRAM_H", 0xe2b4, 0 },
36007 		{ "PortMap", 0, 4 },
36008 	{ "MPS_CLS_SRAM_H", 0xe2bc, 0 },
36013 		{ "PortMap", 0, 4 },
36014 	{ "MPS_CLS_SRAM_H", 0xe2c4, 0 },
36019 		{ "PortMap", 0, 4 },
36020 	{ "MPS_CLS_SRAM_H", 0xe2cc, 0 },
36025 		{ "PortMap", 0, 4 },
36026 	{ "MPS_CLS_SRAM_H", 0xe2d4, 0 },
36031 		{ "PortMap", 0, 4 },
36032 	{ "MPS_CLS_SRAM_H", 0xe2dc, 0 },
36037 		{ "PortMap", 0, 4 },
36038 	{ "MPS_CLS_SRAM_H", 0xe2e4, 0 },
36043 		{ "PortMap", 0, 4 },
36044 	{ "MPS_CLS_SRAM_H", 0xe2ec, 0 },
36049 		{ "PortMap", 0, 4 },
36050 	{ "MPS_CLS_SRAM_H", 0xe2f4, 0 },
36055 		{ "PortMap", 0, 4 },
36056 	{ "MPS_CLS_SRAM_H", 0xe2fc, 0 },
36061 		{ "PortMap", 0, 4 },
36062 	{ "MPS_CLS_SRAM_H", 0xe304, 0 },
36067 		{ "PortMap", 0, 4 },
36068 	{ "MPS_CLS_SRAM_H", 0xe30c, 0 },
36073 		{ "PortMap", 0, 4 },
36074 	{ "MPS_CLS_SRAM_H", 0xe314, 0 },
36079 		{ "PortMap", 0, 4 },
36080 	{ "MPS_CLS_SRAM_H", 0xe31c, 0 },
36085 		{ "PortMap", 0, 4 },
36086 	{ "MPS_CLS_SRAM_H", 0xe324, 0 },
36091 		{ "PortMap", 0, 4 },
36092 	{ "MPS_CLS_SRAM_H", 0xe32c, 0 },
36097 		{ "PortMap", 0, 4 },
36098 	{ "MPS_CLS_SRAM_H", 0xe334, 0 },
36103 		{ "PortMap", 0, 4 },
36104 	{ "MPS_CLS_SRAM_H", 0xe33c, 0 },
36109 		{ "PortMap", 0, 4 },
36110 	{ "MPS_CLS_SRAM_H", 0xe344, 0 },
36115 		{ "PortMap", 0, 4 },
36116 	{ "MPS_CLS_SRAM_H", 0xe34c, 0 },
36121 		{ "PortMap", 0, 4 },
36122 	{ "MPS_CLS_SRAM_H", 0xe354, 0 },
36127 		{ "PortMap", 0, 4 },
36128 	{ "MPS_CLS_SRAM_H", 0xe35c, 0 },
36133 		{ "PortMap", 0, 4 },
36134 	{ "MPS_CLS_SRAM_H", 0xe364, 0 },
36139 		{ "PortMap", 0, 4 },
36140 	{ "MPS_CLS_SRAM_H", 0xe36c, 0 },
36145 		{ "PortMap", 0, 4 },
36146 	{ "MPS_CLS_SRAM_H", 0xe374, 0 },
36151 		{ "PortMap", 0, 4 },
36152 	{ "MPS_CLS_SRAM_H", 0xe37c, 0 },
36157 		{ "PortMap", 0, 4 },
36158 	{ "MPS_CLS_SRAM_H", 0xe384, 0 },
36163 		{ "PortMap", 0, 4 },
36164 	{ "MPS_CLS_SRAM_H", 0xe38c, 0 },
36169 		{ "PortMap", 0, 4 },
36170 	{ "MPS_CLS_SRAM_H", 0xe394, 0 },
36175 		{ "PortMap", 0, 4 },
36176 	{ "MPS_CLS_SRAM_H", 0xe39c, 0 },
36181 		{ "PortMap", 0, 4 },
36182 	{ "MPS_CLS_SRAM_H", 0xe3a4, 0 },
36187 		{ "PortMap", 0, 4 },
36188 	{ "MPS_CLS_SRAM_H", 0xe3ac, 0 },
36193 		{ "PortMap", 0, 4 },
36194 	{ "MPS_CLS_SRAM_H", 0xe3b4, 0 },
36199 		{ "PortMap", 0, 4 },
36200 	{ "MPS_CLS_SRAM_H", 0xe3bc, 0 },
36205 		{ "PortMap", 0, 4 },
36206 	{ "MPS_CLS_SRAM_H", 0xe3c4, 0 },
36211 		{ "PortMap", 0, 4 },
36212 	{ "MPS_CLS_SRAM_H", 0xe3cc, 0 },
36217 		{ "PortMap", 0, 4 },
36218 	{ "MPS_CLS_SRAM_H", 0xe3d4, 0 },
36223 		{ "PortMap", 0, 4 },
36224 	{ "MPS_CLS_SRAM_H", 0xe3dc, 0 },
36229 		{ "PortMap", 0, 4 },
36230 	{ "MPS_CLS_SRAM_H", 0xe3e4, 0 },
36235 		{ "PortMap", 0, 4 },
36236 	{ "MPS_CLS_SRAM_H", 0xe3ec, 0 },
36241 		{ "PortMap", 0, 4 },
36242 	{ "MPS_CLS_SRAM_H", 0xe3f4, 0 },
36247 		{ "PortMap", 0, 4 },
36248 	{ "MPS_CLS_SRAM_H", 0xe3fc, 0 },
36253 		{ "PortMap", 0, 4 },
36254 	{ "MPS_CLS_SRAM_H", 0xe404, 0 },
36259 		{ "PortMap", 0, 4 },
36260 	{ "MPS_CLS_SRAM_H", 0xe40c, 0 },
36265 		{ "PortMap", 0, 4 },
36266 	{ "MPS_CLS_SRAM_H", 0xe414, 0 },
36271 		{ "PortMap", 0, 4 },
36272 	{ "MPS_CLS_SRAM_H", 0xe41c, 0 },
36277 		{ "PortMap", 0, 4 },
36278 	{ "MPS_CLS_SRAM_H", 0xe424, 0 },
36283 		{ "PortMap", 0, 4 },
36284 	{ "MPS_CLS_SRAM_H", 0xe42c, 0 },
36289 		{ "PortMap", 0, 4 },
36290 	{ "MPS_CLS_SRAM_H", 0xe434, 0 },
36295 		{ "PortMap", 0, 4 },
36296 	{ "MPS_CLS_SRAM_H", 0xe43c, 0 },
36301 		{ "PortMap", 0, 4 },
36302 	{ "MPS_CLS_SRAM_H", 0xe444, 0 },
36307 		{ "PortMap", 0, 4 },
36308 	{ "MPS_CLS_SRAM_H", 0xe44c, 0 },
36313 		{ "PortMap", 0, 4 },
36314 	{ "MPS_CLS_SRAM_H", 0xe454, 0 },
36319 		{ "PortMap", 0, 4 },
36320 	{ "MPS_CLS_SRAM_H", 0xe45c, 0 },
36325 		{ "PortMap", 0, 4 },
36326 	{ "MPS_CLS_SRAM_H", 0xe464, 0 },
36331 		{ "PortMap", 0, 4 },
36332 	{ "MPS_CLS_SRAM_H", 0xe46c, 0 },
36337 		{ "PortMap", 0, 4 },
36338 	{ "MPS_CLS_SRAM_H", 0xe474, 0 },
36343 		{ "PortMap", 0, 4 },
36344 	{ "MPS_CLS_SRAM_H", 0xe47c, 0 },
36349 		{ "PortMap", 0, 4 },
36350 	{ "MPS_CLS_SRAM_H", 0xe484, 0 },
36355 		{ "PortMap", 0, 4 },
36356 	{ "MPS_CLS_SRAM_H", 0xe48c, 0 },
36361 		{ "PortMap", 0, 4 },
36362 	{ "MPS_CLS_SRAM_H", 0xe494, 0 },
36367 		{ "PortMap", 0, 4 },
36368 	{ "MPS_CLS_SRAM_H", 0xe49c, 0 },
36373 		{ "PortMap", 0, 4 },
36374 	{ "MPS_CLS_SRAM_H", 0xe4a4, 0 },
36379 		{ "PortMap", 0, 4 },
36380 	{ "MPS_CLS_SRAM_H", 0xe4ac, 0 },
36385 		{ "PortMap", 0, 4 },
36386 	{ "MPS_CLS_SRAM_H", 0xe4b4, 0 },
36391 		{ "PortMap", 0, 4 },
36392 	{ "MPS_CLS_SRAM_H", 0xe4bc, 0 },
36397 		{ "PortMap", 0, 4 },
36398 	{ "MPS_CLS_SRAM_H", 0xe4c4, 0 },
36403 		{ "PortMap", 0, 4 },
36404 	{ "MPS_CLS_SRAM_H", 0xe4cc, 0 },
36409 		{ "PortMap", 0, 4 },
36410 	{ "MPS_CLS_SRAM_H", 0xe4d4, 0 },
36415 		{ "PortMap", 0, 4 },
36416 	{ "MPS_CLS_SRAM_H", 0xe4dc, 0 },
36421 		{ "PortMap", 0, 4 },
36422 	{ "MPS_CLS_SRAM_H", 0xe4e4, 0 },
36427 		{ "PortMap", 0, 4 },
36428 	{ "MPS_CLS_SRAM_H", 0xe4ec, 0 },
36433 		{ "PortMap", 0, 4 },
36434 	{ "MPS_CLS_SRAM_H", 0xe4f4, 0 },
36439 		{ "PortMap", 0, 4 },
36440 	{ "MPS_CLS_SRAM_H", 0xe4fc, 0 },
36445 		{ "PortMap", 0, 4 },
36446 	{ "MPS_CLS_SRAM_H", 0xe504, 0 },
36451 		{ "PortMap", 0, 4 },
36452 	{ "MPS_CLS_SRAM_H", 0xe50c, 0 },
36457 		{ "PortMap", 0, 4 },
36458 	{ "MPS_CLS_SRAM_H", 0xe514, 0 },
36463 		{ "PortMap", 0, 4 },
36464 	{ "MPS_CLS_SRAM_H", 0xe51c, 0 },
36469 		{ "PortMap", 0, 4 },
36470 	{ "MPS_CLS_SRAM_H", 0xe524, 0 },
36475 		{ "PortMap", 0, 4 },
36476 	{ "MPS_CLS_SRAM_H", 0xe52c, 0 },
36481 		{ "PortMap", 0, 4 },
36482 	{ "MPS_CLS_SRAM_H", 0xe534, 0 },
36487 		{ "PortMap", 0, 4 },
36488 	{ "MPS_CLS_SRAM_H", 0xe53c, 0 },
36493 		{ "PortMap", 0, 4 },
36494 	{ "MPS_CLS_SRAM_H", 0xe544, 0 },
36499 		{ "PortMap", 0, 4 },
36500 	{ "MPS_CLS_SRAM_H", 0xe54c, 0 },
36505 		{ "PortMap", 0, 4 },
36506 	{ "MPS_CLS_SRAM_H", 0xe554, 0 },
36511 		{ "PortMap", 0, 4 },
36512 	{ "MPS_CLS_SRAM_H", 0xe55c, 0 },
36517 		{ "PortMap", 0, 4 },
36518 	{ "MPS_CLS_SRAM_H", 0xe564, 0 },
36523 		{ "PortMap", 0, 4 },
36524 	{ "MPS_CLS_SRAM_H", 0xe56c, 0 },
36529 		{ "PortMap", 0, 4 },
36530 	{ "MPS_CLS_SRAM_H", 0xe574, 0 },
36535 		{ "PortMap", 0, 4 },
36536 	{ "MPS_CLS_SRAM_H", 0xe57c, 0 },
36541 		{ "PortMap", 0, 4 },
36542 	{ "MPS_CLS_SRAM_H", 0xe584, 0 },
36547 		{ "PortMap", 0, 4 },
36548 	{ "MPS_CLS_SRAM_H", 0xe58c, 0 },
36553 		{ "PortMap", 0, 4 },
36554 	{ "MPS_CLS_SRAM_H", 0xe594, 0 },
36559 		{ "PortMap", 0, 4 },
36560 	{ "MPS_CLS_SRAM_H", 0xe59c, 0 },
36565 		{ "PortMap", 0, 4 },
36566 	{ "MPS_CLS_SRAM_H", 0xe5a4, 0 },
36571 		{ "PortMap", 0, 4 },
36572 	{ "MPS_CLS_SRAM_H", 0xe5ac, 0 },
36577 		{ "PortMap", 0, 4 },
36578 	{ "MPS_CLS_SRAM_H", 0xe5b4, 0 },
36583 		{ "PortMap", 0, 4 },
36584 	{ "MPS_CLS_SRAM_H", 0xe5bc, 0 },
36589 		{ "PortMap", 0, 4 },
36590 	{ "MPS_CLS_SRAM_H", 0xe5c4, 0 },
36595 		{ "PortMap", 0, 4 },
36596 	{ "MPS_CLS_SRAM_H", 0xe5cc, 0 },
36601 		{ "PortMap", 0, 4 },
36602 	{ "MPS_CLS_SRAM_H", 0xe5d4, 0 },
36607 		{ "PortMap", 0, 4 },
36608 	{ "MPS_CLS_SRAM_H", 0xe5dc, 0 },
36613 		{ "PortMap", 0, 4 },
36614 	{ "MPS_CLS_SRAM_H", 0xe5e4, 0 },
36619 		{ "PortMap", 0, 4 },
36620 	{ "MPS_CLS_SRAM_H", 0xe5ec, 0 },
36625 		{ "PortMap", 0, 4 },
36626 	{ "MPS_CLS_SRAM_H", 0xe5f4, 0 },
36631 		{ "PortMap", 0, 4 },
36632 	{ "MPS_CLS_SRAM_H", 0xe5fc, 0 },
36637 		{ "PortMap", 0, 4 },
36638 	{ "MPS_CLS_SRAM_H", 0xe604, 0 },
36643 		{ "PortMap", 0, 4 },
36644 	{ "MPS_CLS_SRAM_H", 0xe60c, 0 },
36649 		{ "PortMap", 0, 4 },
36650 	{ "MPS_CLS_SRAM_H", 0xe614, 0 },
36655 		{ "PortMap", 0, 4 },
36656 	{ "MPS_CLS_SRAM_H", 0xe61c, 0 },
36661 		{ "PortMap", 0, 4 },
36662 	{ "MPS_CLS_SRAM_H", 0xe624, 0 },
36667 		{ "PortMap", 0, 4 },
36668 	{ "MPS_CLS_SRAM_H", 0xe62c, 0 },
36673 		{ "PortMap", 0, 4 },
36674 	{ "MPS_CLS_SRAM_H", 0xe634, 0 },
36679 		{ "PortMap", 0, 4 },
36680 	{ "MPS_CLS_SRAM_H", 0xe63c, 0 },
36685 		{ "PortMap", 0, 4 },
36686 	{ "MPS_CLS_SRAM_H", 0xe644, 0 },
36691 		{ "PortMap", 0, 4 },
36692 	{ "MPS_CLS_SRAM_H", 0xe64c, 0 },
36697 		{ "PortMap", 0, 4 },
36698 	{ "MPS_CLS_SRAM_H", 0xe654, 0 },
36703 		{ "PortMap", 0, 4 },
36704 	{ "MPS_CLS_SRAM_H", 0xe65c, 0 },
36709 		{ "PortMap", 0, 4 },
36710 	{ "MPS_CLS_SRAM_H", 0xe664, 0 },
36715 		{ "PortMap", 0, 4 },
36716 	{ "MPS_CLS_SRAM_H", 0xe66c, 0 },
36721 		{ "PortMap", 0, 4 },
36722 	{ "MPS_CLS_SRAM_H", 0xe674, 0 },
36727 		{ "PortMap", 0, 4 },
36728 	{ "MPS_CLS_SRAM_H", 0xe67c, 0 },
36733 		{ "PortMap", 0, 4 },
36734 	{ "MPS_CLS_SRAM_H", 0xe684, 0 },
36739 		{ "PortMap", 0, 4 },
36740 	{ "MPS_CLS_SRAM_H", 0xe68c, 0 },
36745 		{ "PortMap", 0, 4 },
36746 	{ "MPS_CLS_SRAM_H", 0xe694, 0 },
36751 		{ "PortMap", 0, 4 },
36752 	{ "MPS_CLS_SRAM_H", 0xe69c, 0 },
36757 		{ "PortMap", 0, 4 },
36758 	{ "MPS_CLS_SRAM_H", 0xe6a4, 0 },
36763 		{ "PortMap", 0, 4 },
36764 	{ "MPS_CLS_SRAM_H", 0xe6ac, 0 },
36769 		{ "PortMap", 0, 4 },
36770 	{ "MPS_CLS_SRAM_H", 0xe6b4, 0 },
36775 		{ "PortMap", 0, 4 },
36776 	{ "MPS_CLS_SRAM_H", 0xe6bc, 0 },
36781 		{ "PortMap", 0, 4 },
36782 	{ "MPS_CLS_SRAM_H", 0xe6c4, 0 },
36787 		{ "PortMap", 0, 4 },
36788 	{ "MPS_CLS_SRAM_H", 0xe6cc, 0 },
36793 		{ "PortMap", 0, 4 },
36794 	{ "MPS_CLS_SRAM_H", 0xe6d4, 0 },
36799 		{ "PortMap", 0, 4 },
36800 	{ "MPS_CLS_SRAM_H", 0xe6dc, 0 },
36805 		{ "PortMap", 0, 4 },
36806 	{ "MPS_CLS_SRAM_H", 0xe6e4, 0 },
36811 		{ "PortMap", 0, 4 },
36812 	{ "MPS_CLS_SRAM_H", 0xe6ec, 0 },
36817 		{ "PortMap", 0, 4 },
36818 	{ "MPS_CLS_SRAM_H", 0xe6f4, 0 },
36823 		{ "PortMap", 0, 4 },
36824 	{ "MPS_CLS_SRAM_H", 0xe6fc, 0 },
36829 		{ "PortMap", 0, 4 },
36830 	{ "MPS_CLS_SRAM_H", 0xe704, 0 },
36835 		{ "PortMap", 0, 4 },
36836 	{ "MPS_CLS_SRAM_H", 0xe70c, 0 },
36841 		{ "PortMap", 0, 4 },
36842 	{ "MPS_CLS_SRAM_H", 0xe714, 0 },
36847 		{ "PortMap", 0, 4 },
36848 	{ "MPS_CLS_SRAM_H", 0xe71c, 0 },
36853 		{ "PortMap", 0, 4 },
36854 	{ "MPS_CLS_SRAM_H", 0xe724, 0 },
36859 		{ "PortMap", 0, 4 },
36860 	{ "MPS_CLS_SRAM_H", 0xe72c, 0 },
36865 		{ "PortMap", 0, 4 },
36866 	{ "MPS_CLS_SRAM_H", 0xe734, 0 },
36871 		{ "PortMap", 0, 4 },
36872 	{ "MPS_CLS_SRAM_H", 0xe73c, 0 },
36877 		{ "PortMap", 0, 4 },
36878 	{ "MPS_CLS_SRAM_H", 0xe744, 0 },
36883 		{ "PortMap", 0, 4 },
36884 	{ "MPS_CLS_SRAM_H", 0xe74c, 0 },
36889 		{ "PortMap", 0, 4 },
36890 	{ "MPS_CLS_SRAM_H", 0xe754, 0 },
36895 		{ "PortMap", 0, 4 },
36896 	{ "MPS_CLS_SRAM_H", 0xe75c, 0 },
36901 		{ "PortMap", 0, 4 },
36902 	{ "MPS_CLS_SRAM_H", 0xe764, 0 },
36907 		{ "PortMap", 0, 4 },
36908 	{ "MPS_CLS_SRAM_H", 0xe76c, 0 },
36913 		{ "PortMap", 0, 4 },
36914 	{ "MPS_CLS_SRAM_H", 0xe774, 0 },
36919 		{ "PortMap", 0, 4 },
36920 	{ "MPS_CLS_SRAM_H", 0xe77c, 0 },
36925 		{ "PortMap", 0, 4 },
36926 	{ "MPS_CLS_SRAM_H", 0xe784, 0 },
36931 		{ "PortMap", 0, 4 },
36932 	{ "MPS_CLS_SRAM_H", 0xe78c, 0 },
36937 		{ "PortMap", 0, 4 },
36938 	{ "MPS_CLS_SRAM_H", 0xe794, 0 },
36943 		{ "PortMap", 0, 4 },
36944 	{ "MPS_CLS_SRAM_H", 0xe79c, 0 },
36949 		{ "PortMap", 0, 4 },
36950 	{ "MPS_CLS_SRAM_H", 0xe7a4, 0 },
36955 		{ "PortMap", 0, 4 },
36956 	{ "MPS_CLS_SRAM_H", 0xe7ac, 0 },
36961 		{ "PortMap", 0, 4 },
36962 	{ "MPS_CLS_SRAM_H", 0xe7b4, 0 },
36967 		{ "PortMap", 0, 4 },
36968 	{ "MPS_CLS_SRAM_H", 0xe7bc, 0 },
36973 		{ "PortMap", 0, 4 },
36974 	{ "MPS_CLS_SRAM_H", 0xe7c4, 0 },
36979 		{ "PortMap", 0, 4 },
36980 	{ "MPS_CLS_SRAM_H", 0xe7cc, 0 },
36985 		{ "PortMap", 0, 4 },
36986 	{ "MPS_CLS_SRAM_H", 0xe7d4, 0 },
36991 		{ "PortMap", 0, 4 },
36992 	{ "MPS_CLS_SRAM_H", 0xe7dc, 0 },
36997 		{ "PortMap", 0, 4 },
36998 	{ "MPS_CLS_SRAM_H", 0xe7e4, 0 },
37003 		{ "PortMap", 0, 4 },
37004 	{ "MPS_CLS_SRAM_H", 0xe7ec, 0 },
37009 		{ "PortMap", 0, 4 },
37010 	{ "MPS_CLS_SRAM_H", 0xe7f4, 0 },
37015 		{ "PortMap", 0, 4 },
37016 	{ "MPS_CLS_SRAM_H", 0xe7fc, 0 },
37021 		{ "PortMap", 0, 4 },
37022 	{ "MPS_CLS_SRAM_H", 0xe804, 0 },
37027 		{ "PortMap", 0, 4 },
37028 	{ "MPS_CLS_SRAM_H", 0xe80c, 0 },
37033 		{ "PortMap", 0, 4 },
37034 	{ "MPS_CLS_SRAM_H", 0xe814, 0 },
37039 		{ "PortMap", 0, 4 },
37040 	{ "MPS_CLS_SRAM_H", 0xe81c, 0 },
37045 		{ "PortMap", 0, 4 },
37046 	{ "MPS_CLS_SRAM_H", 0xe824, 0 },
37051 		{ "PortMap", 0, 4 },
37052 	{ "MPS_CLS_SRAM_H", 0xe82c, 0 },
37057 		{ "PortMap", 0, 4 },
37058 	{ "MPS_CLS_SRAM_H", 0xe834, 0 },
37063 		{ "PortMap", 0, 4 },
37064 	{ "MPS_CLS_SRAM_H", 0xe83c, 0 },
37069 		{ "PortMap", 0, 4 },
37070 	{ "MPS_CLS_SRAM_H", 0xe844, 0 },
37075 		{ "PortMap", 0, 4 },
37076 	{ "MPS_CLS_SRAM_H", 0xe84c, 0 },
37081 		{ "PortMap", 0, 4 },
37082 	{ "MPS_CLS_SRAM_H", 0xe854, 0 },
37087 		{ "PortMap", 0, 4 },
37088 	{ "MPS_CLS_SRAM_H", 0xe85c, 0 },
37093 		{ "PortMap", 0, 4 },
37094 	{ "MPS_CLS_SRAM_H", 0xe864, 0 },
37099 		{ "PortMap", 0, 4 },
37100 	{ "MPS_CLS_SRAM_H", 0xe86c, 0 },
37105 		{ "PortMap", 0, 4 },
37106 	{ "MPS_CLS_SRAM_H", 0xe874, 0 },
37111 		{ "PortMap", 0, 4 },
37112 	{ "MPS_CLS_SRAM_H", 0xe87c, 0 },
37117 		{ "PortMap", 0, 4 },
37118 	{ "MPS_CLS_SRAM_H", 0xe884, 0 },
37123 		{ "PortMap", 0, 4 },
37124 	{ "MPS_CLS_SRAM_H", 0xe88c, 0 },
37129 		{ "PortMap", 0, 4 },
37130 	{ "MPS_CLS_SRAM_H", 0xe894, 0 },
37135 		{ "PortMap", 0, 4 },
37136 	{ "MPS_CLS_SRAM_H", 0xe89c, 0 },
37141 		{ "PortMap", 0, 4 },
37142 	{ "MPS_CLS_SRAM_H", 0xe8a4, 0 },
37147 		{ "PortMap", 0, 4 },
37148 	{ "MPS_CLS_SRAM_H", 0xe8ac, 0 },
37153 		{ "PortMap", 0, 4 },
37154 	{ "MPS_CLS_SRAM_H", 0xe8b4, 0 },
37159 		{ "PortMap", 0, 4 },
37160 	{ "MPS_CLS_SRAM_H", 0xe8bc, 0 },
37165 		{ "PortMap", 0, 4 },
37166 	{ "MPS_CLS_SRAM_H", 0xe8c4, 0 },
37171 		{ "PortMap", 0, 4 },
37172 	{ "MPS_CLS_SRAM_H", 0xe8cc, 0 },
37177 		{ "PortMap", 0, 4 },
37178 	{ "MPS_CLS_SRAM_H", 0xe8d4, 0 },
37183 		{ "PortMap", 0, 4 },
37184 	{ "MPS_CLS_SRAM_H", 0xe8dc, 0 },
37189 		{ "PortMap", 0, 4 },
37190 	{ "MPS_CLS_SRAM_H", 0xe8e4, 0 },
37195 		{ "PortMap", 0, 4 },
37196 	{ "MPS_CLS_SRAM_H", 0xe8ec, 0 },
37201 		{ "PortMap", 0, 4 },
37202 	{ "MPS_CLS_SRAM_H", 0xe8f4, 0 },
37207 		{ "PortMap", 0, 4 },
37208 	{ "MPS_CLS_SRAM_H", 0xe8fc, 0 },
37213 		{ "PortMap", 0, 4 },
37214 	{ "MPS_CLS_SRAM_H", 0xe904, 0 },
37219 		{ "PortMap", 0, 4 },
37220 	{ "MPS_CLS_SRAM_H", 0xe90c, 0 },
37225 		{ "PortMap", 0, 4 },
37226 	{ "MPS_CLS_SRAM_H", 0xe914, 0 },
37231 		{ "PortMap", 0, 4 },
37232 	{ "MPS_CLS_SRAM_H", 0xe91c, 0 },
37237 		{ "PortMap", 0, 4 },
37238 	{ "MPS_CLS_SRAM_H", 0xe924, 0 },
37243 		{ "PortMap", 0, 4 },
37244 	{ "MPS_CLS_SRAM_H", 0xe92c, 0 },
37249 		{ "PortMap", 0, 4 },
37250 	{ "MPS_CLS_SRAM_H", 0xe934, 0 },
37255 		{ "PortMap", 0, 4 },
37256 	{ "MPS_CLS_SRAM_H", 0xe93c, 0 },
37261 		{ "PortMap", 0, 4 },
37262 	{ "MPS_CLS_SRAM_H", 0xe944, 0 },
37267 		{ "PortMap", 0, 4 },
37268 	{ "MPS_CLS_SRAM_H", 0xe94c, 0 },
37273 		{ "PortMap", 0, 4 },
37274 	{ "MPS_CLS_SRAM_H", 0xe954, 0 },
37279 		{ "PortMap", 0, 4 },
37280 	{ "MPS_CLS_SRAM_H", 0xe95c, 0 },
37285 		{ "PortMap", 0, 4 },
37286 	{ "MPS_CLS_SRAM_H", 0xe964, 0 },
37291 		{ "PortMap", 0, 4 },
37292 	{ "MPS_CLS_SRAM_H", 0xe96c, 0 },
37297 		{ "PortMap", 0, 4 },
37298 	{ "MPS_CLS_SRAM_H", 0xe974, 0 },
37303 		{ "PortMap", 0, 4 },
37304 	{ "MPS_CLS_SRAM_H", 0xe97c, 0 },
37309 		{ "PortMap", 0, 4 },
37310 	{ "MPS_CLS_SRAM_H", 0xe984, 0 },
37315 		{ "PortMap", 0, 4 },
37316 	{ "MPS_CLS_SRAM_H", 0xe98c, 0 },
37321 		{ "PortMap", 0, 4 },
37322 	{ "MPS_CLS_SRAM_H", 0xe994, 0 },
37327 		{ "PortMap", 0, 4 },
37328 	{ "MPS_CLS_SRAM_H", 0xe99c, 0 },
37333 		{ "PortMap", 0, 4 },
37334 	{ "MPS_CLS_SRAM_H", 0xe9a4, 0 },
37339 		{ "PortMap", 0, 4 },
37340 	{ "MPS_CLS_SRAM_H", 0xe9ac, 0 },
37345 		{ "PortMap", 0, 4 },
37346 	{ "MPS_CLS_SRAM_H", 0xe9b4, 0 },
37351 		{ "PortMap", 0, 4 },
37352 	{ "MPS_CLS_SRAM_H", 0xe9bc, 0 },
37357 		{ "PortMap", 0, 4 },
37358 	{ "MPS_CLS_SRAM_H", 0xe9c4, 0 },
37363 		{ "PortMap", 0, 4 },
37364 	{ "MPS_CLS_SRAM_H", 0xe9cc, 0 },
37369 		{ "PortMap", 0, 4 },
37370 	{ "MPS_CLS_SRAM_H", 0xe9d4, 0 },
37375 		{ "PortMap", 0, 4 },
37376 	{ "MPS_CLS_SRAM_H", 0xe9dc, 0 },
37381 		{ "PortMap", 0, 4 },
37382 	{ "MPS_CLS_SRAM_H", 0xe9e4, 0 },
37387 		{ "PortMap", 0, 4 },
37388 	{ "MPS_CLS_SRAM_H", 0xe9ec, 0 },
37393 		{ "PortMap", 0, 4 },
37394 	{ "MPS_CLS_SRAM_H", 0xe9f4, 0 },
37399 		{ "PortMap", 0, 4 },
37400 	{ "MPS_CLS_SRAM_H", 0xe9fc, 0 },
37405 		{ "PortMap", 0, 4 },
37406 	{ "MPS_CLS_SRAM_H", 0xea04, 0 },
37411 		{ "PortMap", 0, 4 },
37412 	{ "MPS_CLS_SRAM_H", 0xea0c, 0 },
37417 		{ "PortMap", 0, 4 },
37418 	{ "MPS_CLS_SRAM_H", 0xea14, 0 },
37423 		{ "PortMap", 0, 4 },
37424 	{ "MPS_CLS_SRAM_H", 0xea1c, 0 },
37429 		{ "PortMap", 0, 4 },
37430 	{ "MPS_CLS_SRAM_H", 0xea24, 0 },
37435 		{ "PortMap", 0, 4 },
37436 	{ "MPS_CLS_SRAM_H", 0xea2c, 0 },
37441 		{ "PortMap", 0, 4 },
37442 	{ "MPS_CLS_SRAM_H", 0xea34, 0 },
37447 		{ "PortMap", 0, 4 },
37448 	{ "MPS_CLS_SRAM_H", 0xea3c, 0 },
37453 		{ "PortMap", 0, 4 },
37454 	{ "MPS_CLS_SRAM_H", 0xea44, 0 },
37459 		{ "PortMap", 0, 4 },
37460 	{ "MPS_CLS_SRAM_H", 0xea4c, 0 },
37465 		{ "PortMap", 0, 4 },
37466 	{ "MPS_CLS_SRAM_H", 0xea54, 0 },
37471 		{ "PortMap", 0, 4 },
37472 	{ "MPS_CLS_SRAM_H", 0xea5c, 0 },
37477 		{ "PortMap", 0, 4 },
37478 	{ "MPS_CLS_SRAM_H", 0xea64, 0 },
37483 		{ "PortMap", 0, 4 },
37484 	{ "MPS_CLS_SRAM_H", 0xea6c, 0 },
37489 		{ "PortMap", 0, 4 },
37490 	{ "MPS_CLS_SRAM_H", 0xea74, 0 },
37495 		{ "PortMap", 0, 4 },
37496 	{ "MPS_CLS_SRAM_H", 0xea7c, 0 },
37501 		{ "PortMap", 0, 4 },
37502 	{ "MPS_CLS_SRAM_H", 0xea84, 0 },
37507 		{ "PortMap", 0, 4 },
37508 	{ "MPS_CLS_SRAM_H", 0xea8c, 0 },
37513 		{ "PortMap", 0, 4 },
37514 	{ "MPS_CLS_SRAM_H", 0xea94, 0 },
37519 		{ "PortMap", 0, 4 },
37520 	{ "MPS_CLS_SRAM_H", 0xea9c, 0 },
37525 		{ "PortMap", 0, 4 },
37526 	{ "MPS_CLS_SRAM_H", 0xeaa4, 0 },
37531 		{ "PortMap", 0, 4 },
37532 	{ "MPS_CLS_SRAM_H", 0xeaac, 0 },
37537 		{ "PortMap", 0, 4 },
37538 	{ "MPS_CLS_SRAM_H", 0xeab4, 0 },
37543 		{ "PortMap", 0, 4 },
37544 	{ "MPS_CLS_SRAM_H", 0xeabc, 0 },
37549 		{ "PortMap", 0, 4 },
37550 	{ "MPS_CLS_SRAM_H", 0xeac4, 0 },
37555 		{ "PortMap", 0, 4 },
37556 	{ "MPS_CLS_SRAM_H", 0xeacc, 0 },
37561 		{ "PortMap", 0, 4 },
37562 	{ "MPS_CLS_SRAM_H", 0xead4, 0 },
37567 		{ "PortMap", 0, 4 },
37568 	{ "MPS_CLS_SRAM_H", 0xeadc, 0 },
37573 		{ "PortMap", 0, 4 },
37574 	{ "MPS_CLS_SRAM_H", 0xeae4, 0 },
37579 		{ "PortMap", 0, 4 },
37580 	{ "MPS_CLS_SRAM_H", 0xeaec, 0 },
37585 		{ "PortMap", 0, 4 },
37586 	{ "MPS_CLS_SRAM_H", 0xeaf4, 0 },
37591 		{ "PortMap", 0, 4 },
37592 	{ "MPS_CLS_SRAM_H", 0xeafc, 0 },
37597 		{ "PortMap", 0, 4 },
37598 	{ "MPS_CLS_SRAM_H", 0xeb04, 0 },
37603 		{ "PortMap", 0, 4 },
37604 	{ "MPS_CLS_SRAM_H", 0xeb0c, 0 },
37609 		{ "PortMap", 0, 4 },
37610 	{ "MPS_CLS_SRAM_H", 0xeb14, 0 },
37615 		{ "PortMap", 0, 4 },
37616 	{ "MPS_CLS_SRAM_H", 0xeb1c, 0 },
37621 		{ "PortMap", 0, 4 },
37622 	{ "MPS_CLS_SRAM_H", 0xeb24, 0 },
37627 		{ "PortMap", 0, 4 },
37628 	{ "MPS_CLS_SRAM_H", 0xeb2c, 0 },
37633 		{ "PortMap", 0, 4 },
37634 	{ "MPS_CLS_SRAM_H", 0xeb34, 0 },
37639 		{ "PortMap", 0, 4 },
37640 	{ "MPS_CLS_SRAM_H", 0xeb3c, 0 },
37645 		{ "PortMap", 0, 4 },
37646 	{ "MPS_CLS_SRAM_H", 0xeb44, 0 },
37651 		{ "PortMap", 0, 4 },
37652 	{ "MPS_CLS_SRAM_H", 0xeb4c, 0 },
37657 		{ "PortMap", 0, 4 },
37658 	{ "MPS_CLS_SRAM_H", 0xeb54, 0 },
37663 		{ "PortMap", 0, 4 },
37664 	{ "MPS_CLS_SRAM_H", 0xeb5c, 0 },
37669 		{ "PortMap", 0, 4 },
37670 	{ "MPS_CLS_SRAM_H", 0xeb64, 0 },
37675 		{ "PortMap", 0, 4 },
37676 	{ "MPS_CLS_SRAM_H", 0xeb6c, 0 },
37681 		{ "PortMap", 0, 4 },
37682 	{ "MPS_CLS_SRAM_H", 0xeb74, 0 },
37687 		{ "PortMap", 0, 4 },
37688 	{ "MPS_CLS_SRAM_H", 0xeb7c, 0 },
37693 		{ "PortMap", 0, 4 },
37694 	{ "MPS_CLS_SRAM_H", 0xeb84, 0 },
37699 		{ "PortMap", 0, 4 },
37700 	{ "MPS_CLS_SRAM_H", 0xeb8c, 0 },
37705 		{ "PortMap", 0, 4 },
37706 	{ "MPS_CLS_SRAM_H", 0xeb94, 0 },
37711 		{ "PortMap", 0, 4 },
37712 	{ "MPS_CLS_SRAM_H", 0xeb9c, 0 },
37717 		{ "PortMap", 0, 4 },
37718 	{ "MPS_CLS_SRAM_H", 0xeba4, 0 },
37723 		{ "PortMap", 0, 4 },
37724 	{ "MPS_CLS_SRAM_H", 0xebac, 0 },
37729 		{ "PortMap", 0, 4 },
37730 	{ "MPS_CLS_SRAM_H", 0xebb4, 0 },
37735 		{ "PortMap", 0, 4 },
37736 	{ "MPS_CLS_SRAM_H", 0xebbc, 0 },
37741 		{ "PortMap", 0, 4 },
37742 	{ "MPS_CLS_SRAM_H", 0xebc4, 0 },
37747 		{ "PortMap", 0, 4 },
37748 	{ "MPS_CLS_SRAM_H", 0xebcc, 0 },
37753 		{ "PortMap", 0, 4 },
37754 	{ "MPS_CLS_SRAM_H", 0xebd4, 0 },
37759 		{ "PortMap", 0, 4 },
37760 	{ "MPS_CLS_SRAM_H", 0xebdc, 0 },
37765 		{ "PortMap", 0, 4 },
37766 	{ "MPS_CLS_SRAM_H", 0xebe4, 0 },
37771 		{ "PortMap", 0, 4 },
37772 	{ "MPS_CLS_SRAM_H", 0xebec, 0 },
37777 		{ "PortMap", 0, 4 },
37778 	{ "MPS_CLS_SRAM_H", 0xebf4, 0 },
37783 		{ "PortMap", 0, 4 },
37784 	{ "MPS_CLS_SRAM_H", 0xebfc, 0 },
37789 		{ "PortMap", 0, 4 },
37790 	{ "MPS_CLS_SRAM_H", 0xec04, 0 },
37795 		{ "PortMap", 0, 4 },
37796 	{ "MPS_CLS_SRAM_H", 0xec0c, 0 },
37801 		{ "PortMap", 0, 4 },
37802 	{ "MPS_CLS_SRAM_H", 0xec14, 0 },
37807 		{ "PortMap", 0, 4 },
37808 	{ "MPS_CLS_SRAM_H", 0xec1c, 0 },
37813 		{ "PortMap", 0, 4 },
37814 	{ "MPS_CLS_SRAM_H", 0xec24, 0 },
37819 		{ "PortMap", 0, 4 },
37820 	{ "MPS_CLS_SRAM_H", 0xec2c, 0 },
37825 		{ "PortMap", 0, 4 },
37826 	{ "MPS_CLS_SRAM_H", 0xec34, 0 },
37831 		{ "PortMap", 0, 4 },
37832 	{ "MPS_CLS_SRAM_H", 0xec3c, 0 },
37837 		{ "PortMap", 0, 4 },
37838 	{ "MPS_CLS_SRAM_H", 0xec44, 0 },
37843 		{ "PortMap", 0, 4 },
37844 	{ "MPS_CLS_SRAM_H", 0xec4c, 0 },
37849 		{ "PortMap", 0, 4 },
37850 	{ "MPS_CLS_SRAM_H", 0xec54, 0 },
37855 		{ "PortMap", 0, 4 },
37856 	{ "MPS_CLS_SRAM_H", 0xec5c, 0 },
37861 		{ "PortMap", 0, 4 },
37862 	{ "MPS_CLS_SRAM_H", 0xec64, 0 },
37867 		{ "PortMap", 0, 4 },
37868 	{ "MPS_CLS_SRAM_H", 0xec6c, 0 },
37873 		{ "PortMap", 0, 4 },
37874 	{ "MPS_CLS_SRAM_H", 0xec74, 0 },
37879 		{ "PortMap", 0, 4 },
37880 	{ "MPS_CLS_SRAM_H", 0xec7c, 0 },
37885 		{ "PortMap", 0, 4 },
37886 	{ "MPS_CLS_SRAM_H", 0xec84, 0 },
37891 		{ "PortMap", 0, 4 },
37892 	{ "MPS_CLS_SRAM_H", 0xec8c, 0 },
37897 		{ "PortMap", 0, 4 },
37898 	{ "MPS_CLS_SRAM_H", 0xec94, 0 },
37903 		{ "PortMap", 0, 4 },
37904 	{ "MPS_CLS_SRAM_H", 0xec9c, 0 },
37909 		{ "PortMap", 0, 4 },
37910 	{ "MPS_CLS_SRAM_H", 0xeca4, 0 },
37915 		{ "PortMap", 0, 4 },
37916 	{ "MPS_CLS_SRAM_H", 0xecac, 0 },
37921 		{ "PortMap", 0, 4 },
37922 	{ "MPS_CLS_SRAM_H", 0xecb4, 0 },
37927 		{ "PortMap", 0, 4 },
37928 	{ "MPS_CLS_SRAM_H", 0xecbc, 0 },
37933 		{ "PortMap", 0, 4 },
37934 	{ "MPS_CLS_SRAM_H", 0xecc4, 0 },
37939 		{ "PortMap", 0, 4 },
37940 	{ "MPS_CLS_SRAM_H", 0xeccc, 0 },
37945 		{ "PortMap", 0, 4 },
37946 	{ "MPS_CLS_SRAM_H", 0xecd4, 0 },
37951 		{ "PortMap", 0, 4 },
37952 	{ "MPS_CLS_SRAM_H", 0xecdc, 0 },
37957 		{ "PortMap", 0, 4 },
37958 	{ "MPS_CLS_SRAM_H", 0xece4, 0 },
37963 		{ "PortMap", 0, 4 },
37964 	{ "MPS_CLS_SRAM_H", 0xecec, 0 },
37969 		{ "PortMap", 0, 4 },
37970 	{ "MPS_CLS_SRAM_H", 0xecf4, 0 },
37975 		{ "PortMap", 0, 4 },
37976 	{ "MPS_CLS_SRAM_H", 0xecfc, 0 },
37981 		{ "PortMap", 0, 4 },
37982 	{ "MPS_CLS_SRAM_H", 0xed04, 0 },
37987 		{ "PortMap", 0, 4 },
37988 	{ "MPS_CLS_SRAM_H", 0xed0c, 0 },
37993 		{ "PortMap", 0, 4 },
37994 	{ "MPS_CLS_SRAM_H", 0xed14, 0 },
37999 		{ "PortMap", 0, 4 },
38000 	{ "MPS_CLS_SRAM_H", 0xed1c, 0 },
38005 		{ "PortMap", 0, 4 },
38006 	{ "MPS_CLS_SRAM_H", 0xed24, 0 },
38011 		{ "PortMap", 0, 4 },
38012 	{ "MPS_CLS_SRAM_H", 0xed2c, 0 },
38017 		{ "PortMap", 0, 4 },
38018 	{ "MPS_CLS_SRAM_H", 0xed34, 0 },
38023 		{ "PortMap", 0, 4 },
38024 	{ "MPS_CLS_SRAM_H", 0xed3c, 0 },
38029 		{ "PortMap", 0, 4 },
38030 	{ "MPS_CLS_SRAM_H", 0xed44, 0 },
38035 		{ "PortMap", 0, 4 },
38036 	{ "MPS_CLS_SRAM_H", 0xed4c, 0 },
38041 		{ "PortMap", 0, 4 },
38042 	{ "MPS_CLS_SRAM_H", 0xed54, 0 },
38047 		{ "PortMap", 0, 4 },
38048 	{ "MPS_CLS_SRAM_H", 0xed5c, 0 },
38053 		{ "PortMap", 0, 4 },
38054 	{ "MPS_CLS_SRAM_H", 0xed64, 0 },
38059 		{ "PortMap", 0, 4 },
38060 	{ "MPS_CLS_SRAM_H", 0xed6c, 0 },
38065 		{ "PortMap", 0, 4 },
38066 	{ "MPS_CLS_SRAM_H", 0xed74, 0 },
38071 		{ "PortMap", 0, 4 },
38072 	{ "MPS_CLS_SRAM_H", 0xed7c, 0 },
38077 		{ "PortMap", 0, 4 },
38078 	{ "MPS_CLS_SRAM_H", 0xed84, 0 },
38083 		{ "PortMap", 0, 4 },
38084 	{ "MPS_CLS_SRAM_H", 0xed8c, 0 },
38089 		{ "PortMap", 0, 4 },
38090 	{ "MPS_CLS_SRAM_H", 0xed94, 0 },
38095 		{ "PortMap", 0, 4 },
38096 	{ "MPS_CLS_SRAM_H", 0xed9c, 0 },
38101 		{ "PortMap", 0, 4 },
38102 	{ "MPS_CLS_SRAM_H", 0xeda4, 0 },
38107 		{ "PortMap", 0, 4 },
38108 	{ "MPS_CLS_SRAM_H", 0xedac, 0 },
38113 		{ "PortMap", 0, 4 },
38114 	{ "MPS_CLS_SRAM_H", 0xedb4, 0 },
38119 		{ "PortMap", 0, 4 },
38120 	{ "MPS_CLS_SRAM_H", 0xedbc, 0 },
38125 		{ "PortMap", 0, 4 },
38126 	{ "MPS_CLS_SRAM_H", 0xedc4, 0 },
38131 		{ "PortMap", 0, 4 },
38132 	{ "MPS_CLS_SRAM_H", 0xedcc, 0 },
38137 		{ "PortMap", 0, 4 },
38138 	{ "MPS_CLS_SRAM_H", 0xedd4, 0 },
38143 		{ "PortMap", 0, 4 },
38144 	{ "MPS_CLS_SRAM_H", 0xeddc, 0 },
38149 		{ "PortMap", 0, 4 },
38150 	{ "MPS_CLS_SRAM_H", 0xede4, 0 },
38155 		{ "PortMap", 0, 4 },
38156 	{ "MPS_CLS_SRAM_H", 0xedec, 0 },
38161 		{ "PortMap", 0, 4 },
38162 	{ "MPS_CLS_SRAM_H", 0xedf4, 0 },
38167 		{ "PortMap", 0, 4 },
38168 	{ "MPS_CLS_SRAM_H", 0xedfc, 0 },
38173 		{ "PortMap", 0, 4 },
38174 	{ "MPS_CLS_SRAM_H", 0xee04, 0 },
38179 		{ "PortMap", 0, 4 },
38180 	{ "MPS_CLS_SRAM_H", 0xee0c, 0 },
38185 		{ "PortMap", 0, 4 },
38186 	{ "MPS_CLS_SRAM_H", 0xee14, 0 },
38191 		{ "PortMap", 0, 4 },
38192 	{ "MPS_CLS_SRAM_H", 0xee1c, 0 },
38197 		{ "PortMap", 0, 4 },
38198 	{ "MPS_CLS_SRAM_H", 0xee24, 0 },
38203 		{ "PortMap", 0, 4 },
38204 	{ "MPS_CLS_SRAM_H", 0xee2c, 0 },
38209 		{ "PortMap", 0, 4 },
38210 	{ "MPS_CLS_SRAM_H", 0xee34, 0 },
38215 		{ "PortMap", 0, 4 },
38216 	{ "MPS_CLS_SRAM_H", 0xee3c, 0 },
38221 		{ "PortMap", 0, 4 },
38222 	{ "MPS_CLS_SRAM_H", 0xee44, 0 },
38227 		{ "PortMap", 0, 4 },
38228 	{ "MPS_CLS_SRAM_H", 0xee4c, 0 },
38233 		{ "PortMap", 0, 4 },
38234 	{ "MPS_CLS_SRAM_H", 0xee54, 0 },
38239 		{ "PortMap", 0, 4 },
38240 	{ "MPS_CLS_SRAM_H", 0xee5c, 0 },
38245 		{ "PortMap", 0, 4 },
38246 	{ "MPS_CLS_SRAM_H", 0xee64, 0 },
38251 		{ "PortMap", 0, 4 },
38252 	{ "MPS_CLS_SRAM_H", 0xee6c, 0 },
38257 		{ "PortMap", 0, 4 },
38258 	{ "MPS_CLS_SRAM_H", 0xee74, 0 },
38263 		{ "PortMap", 0, 4 },
38264 	{ "MPS_CLS_SRAM_H", 0xee7c, 0 },
38269 		{ "PortMap", 0, 4 },
38270 	{ "MPS_CLS_SRAM_H", 0xee84, 0 },
38275 		{ "PortMap", 0, 4 },
38276 	{ "MPS_CLS_SRAM_H", 0xee8c, 0 },
38281 		{ "PortMap", 0, 4 },
38282 	{ "MPS_CLS_SRAM_H", 0xee94, 0 },
38287 		{ "PortMap", 0, 4 },
38288 	{ "MPS_CLS_SRAM_H", 0xee9c, 0 },
38293 		{ "PortMap", 0, 4 },
38294 	{ "MPS_CLS_SRAM_H", 0xeea4, 0 },
38299 		{ "PortMap", 0, 4 },
38300 	{ "MPS_CLS_SRAM_H", 0xeeac, 0 },
38305 		{ "PortMap", 0, 4 },
38306 	{ "MPS_CLS_SRAM_H", 0xeeb4, 0 },
38311 		{ "PortMap", 0, 4 },
38312 	{ "MPS_CLS_SRAM_H", 0xeebc, 0 },
38317 		{ "PortMap", 0, 4 },
38318 	{ "MPS_CLS_SRAM_H", 0xeec4, 0 },
38323 		{ "PortMap", 0, 4 },
38324 	{ "MPS_CLS_SRAM_H", 0xeecc, 0 },
38329 		{ "PortMap", 0, 4 },
38330 	{ "MPS_CLS_SRAM_H", 0xeed4, 0 },
38335 		{ "PortMap", 0, 4 },
38336 	{ "MPS_CLS_SRAM_H", 0xeedc, 0 },
38341 		{ "PortMap", 0, 4 },
38342 	{ "MPS_CLS_SRAM_H", 0xeee4, 0 },
38347 		{ "PortMap", 0, 4 },
38348 	{ "MPS_CLS_SRAM_H", 0xeeec, 0 },
38353 		{ "PortMap", 0, 4 },
38354 	{ "MPS_CLS_SRAM_H", 0xeef4, 0 },
38359 		{ "PortMap", 0, 4 },
38360 	{ "MPS_CLS_SRAM_H", 0xeefc, 0 },
38365 		{ "PortMap", 0, 4 },
38366 	{ "MPS_CLS_SRAM_H", 0xef04, 0 },
38371 		{ "PortMap", 0, 4 },
38372 	{ "MPS_CLS_SRAM_H", 0xef0c, 0 },
38377 		{ "PortMap", 0, 4 },
38378 	{ "MPS_CLS_SRAM_H", 0xef14, 0 },
38383 		{ "PortMap", 0, 4 },
38384 	{ "MPS_CLS_SRAM_H", 0xef1c, 0 },
38389 		{ "PortMap", 0, 4 },
38390 	{ "MPS_CLS_SRAM_H", 0xef24, 0 },
38395 		{ "PortMap", 0, 4 },
38396 	{ "MPS_CLS_SRAM_H", 0xef2c, 0 },
38401 		{ "PortMap", 0, 4 },
38402 	{ "MPS_CLS_SRAM_H", 0xef34, 0 },
38407 		{ "PortMap", 0, 4 },
38408 	{ "MPS_CLS_SRAM_H", 0xef3c, 0 },
38413 		{ "PortMap", 0, 4 },
38414 	{ "MPS_CLS_SRAM_H", 0xef44, 0 },
38419 		{ "PortMap", 0, 4 },
38420 	{ "MPS_CLS_SRAM_H", 0xef4c, 0 },
38425 		{ "PortMap", 0, 4 },
38426 	{ "MPS_CLS_SRAM_H", 0xef54, 0 },
38431 		{ "PortMap", 0, 4 },
38432 	{ "MPS_CLS_SRAM_H", 0xef5c, 0 },
38437 		{ "PortMap", 0, 4 },
38438 	{ "MPS_CLS_SRAM_H", 0xef64, 0 },
38443 		{ "PortMap", 0, 4 },
38444 	{ "MPS_CLS_SRAM_H", 0xef6c, 0 },
38449 		{ "PortMap", 0, 4 },
38450 	{ "MPS_CLS_SRAM_H", 0xef74, 0 },
38455 		{ "PortMap", 0, 4 },
38456 	{ "MPS_CLS_SRAM_H", 0xef7c, 0 },
38461 		{ "PortMap", 0, 4 },
38462 	{ "MPS_CLS_SRAM_H", 0xef84, 0 },
38467 		{ "PortMap", 0, 4 },
38468 	{ "MPS_CLS_SRAM_H", 0xef8c, 0 },
38473 		{ "PortMap", 0, 4 },
38474 	{ "MPS_CLS_SRAM_H", 0xef94, 0 },
38479 		{ "PortMap", 0, 4 },
38480 	{ "MPS_CLS_SRAM_H", 0xef9c, 0 },
38485 		{ "PortMap", 0, 4 },
38486 	{ "MPS_CLS_SRAM_H", 0xefa4, 0 },
38491 		{ "PortMap", 0, 4 },
38492 	{ "MPS_CLS_SRAM_H", 0xefac, 0 },
38497 		{ "PortMap", 0, 4 },
38498 	{ "MPS_CLS_SRAM_H", 0xefb4, 0 },
38503 		{ "PortMap", 0, 4 },
38504 	{ "MPS_CLS_SRAM_H", 0xefbc, 0 },
38509 		{ "PortMap", 0, 4 },
38510 	{ "MPS_CLS_SRAM_H", 0xefc4, 0 },
38515 		{ "PortMap", 0, 4 },
38516 	{ "MPS_CLS_SRAM_H", 0xefcc, 0 },
38521 		{ "PortMap", 0, 4 },
38522 	{ "MPS_CLS_SRAM_H", 0xefd4, 0 },
38527 		{ "PortMap", 0, 4 },
38528 	{ "MPS_CLS_SRAM_H", 0xefdc, 0 },
38533 		{ "PortMap", 0, 4 },
38534 	{ "MPS_CLS_SRAM_H", 0xefe4, 0 },
38539 		{ "PortMap", 0, 4 },
38540 	{ "MPS_CLS_SRAM_H", 0xefec, 0 },
38545 		{ "PortMap", 0, 4 },
38546 	{ "MPS_CLS_SRAM_H", 0xeff4, 0 },
38551 		{ "PortMap", 0, 4 },
38552 	{ "MPS_CLS_SRAM_H", 0xeffc, 0 },
38557 		{ "PortMap", 0, 4 },
38558 	{ "MPS_CLS_TCAM_DATA0", 0xf000, 0 },
38559 	{ "MPS_CLS_TCAM_DATA1", 0xf004, 0 },
38561 		{ "DMACH", 0, 16 },
38562 	{ "MPS_CLS_TCAM_DATA2_CTL", 0xf008, 0 },
38572 		{ "DataVIDH1", 0, 7 },
38573 	{ "MPS_CLS_TCAM_RDATA0_REQ_ID0", 0xf010, 0 },
38574 	{ "MPS_CLS_TCAM_RDATA1_REQ_ID0", 0xf014, 0 },
38576 		{ "DMACH", 0, 16 },
38577 	{ "MPS_CLS_TCAM_RDATA2_REQ_ID0", 0xf018, 0 },
38582 		{ "DataVIDH1", 0, 7 },
38583 	{ "MPS_CLS_TCAM_RDATA0_REQ_ID1", 0xf020, 0 },
38584 	{ "MPS_CLS_TCAM_RDATA1_REQ_ID1", 0xf024, 0 },
38586 		{ "DMACH", 0, 16 },
38587 	{ "MPS_CLS_TCAM_RDATA2_REQ_ID1", 0xf028, 0 },
38592 		{ "DataVIDH1", 0, 7 },
38597 	{ "CPL_SWITCH_CNTRL", 0x19040, 0 },
38605 		{ "cim_enable", 0, 1 },
38606 	{ "CPL_SWITCH_TBL_IDX", 0x19044, 0 },
38607 	{ "CPL_SWITCH_TBL_DATA", 0x19048, 0 },
38608 	{ "CPL_SWITCH_ZERO_ERROR", 0x1904c, 0 },
38610 		{ "zero_cmd_ch0", 0, 8 },
38611 	{ "CPL_INTR_ENABLE", 0x19050, 0 },
38619 		{ "zero_switch_error", 0, 1 },
38620 	{ "CPL_INTR_CAUSE", 0x19054, 0 },
38628 		{ "zero_switch_error", 0, 1 },
38629 	{ "CPL_MAP_TBL_IDX", 0x19058, 0 },
38631 		{ "cpl_map_tbl_idx", 0, 8 },
38632 	{ "CPL_MAP_TBL_DATA", 0x1905c, 0 },
38637 	{ "SMB_GLOBAL_TIME_CFG", 0x19060, 0 },
38639 		{ "MicroCntCfg", 0, 8 },
38640 	{ "SMB_MST_TIMEOUT_CFG", 0x19064, 0 },
38641 	{ "SMB_MST_CTL_CFG", 0x19068, 0 },
38647 		{ "MstCtlEn", 0, 1 },
38648 	{ "SMB_MST_CTL_STS", 0x1906c, 0 },
38651 		{ "MstBusySts", 0, 1 },
38652 	{ "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 },
38653 	{ "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 },
38654 	{ "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 },
38655 	{ "SMB_SLV_CTL_CFG", 0x1907c, 0 },
38665 		{ "SlvCtlEn", 0, 1 },
38666 	{ "SMB_SLV_CTL_STS", 0x19080, 0 },
38670 		{ "SlvBusySts", 0, 1 },
38671 	{ "SMB_SLV_FIFO_RDWR", 0x19084, 0 },
38672 	{ "SMB_INT_ENABLE", 0x1908c, 0 },
38694 		{ "MstDoneIntEn", 0, 1 },
38695 	{ "SMB_INT_CAUSE", 0x19090, 0 },
38717 		{ "MstDoneInt", 0, 1 },
38718 	{ "SMB_DEBUG_DATA", 0x19094, 0 },
38720 		{ "DebugDataL", 0, 16 },
38721 	{ "SMB_PERR_EN", 0x19098, 0 },
38727 		{ "SlvFifoPerrEn", 0, 1 },
38728 	{ "SMB_PERR_INJ", 0x1909c, 0 },
38732 		{ "FifoInjDataErrEn", 0, 1 },
38733 	{ "SMB_SLV_ARP_CTL", 0x190a0, 0 },
38736 		{ "ArpAddrVal", 0, 1 },
38737 	{ "SMB_ARP_UDID0", 0x190a4, 0 },
38738 	{ "SMB_ARP_UDID1", 0x190a8, 0 },
38740 		{ "SubsystemDeviceID", 0, 16 },
38741 	{ "SMB_ARP_UDID2", 0x190ac, 0 },
38743 		{ "Interface", 0, 16 },
38744 	{ "SMB_ARP_UDID3", 0x190b0, 0 },
38747 		{ "VendorID", 0, 16 },
38748 	{ "SMB_SLV_AUX_ADDR0", 0x190b4, 0 },
38750 		{ "AuxAddr0", 0, 6 },
38751 	{ "SMB_SLV_AUX_ADDR1", 0x190b8, 0 },
38753 		{ "AuxAddr1", 0, 6 },
38754 	{ "SMB_SLV_AUX_ADDR2", 0x190bc, 0 },
38756 		{ "AuxAddr2", 0, 6 },
38757 	{ "SMB_SLV_AUX_ADDR3", 0x190c0, 0 },
38759 		{ "AuxAddr3", 0, 6 },
38760 	{ "SMB_COMMAND_CODE0", 0x190c4, 0 },
38761 	{ "SMB_COMMAND_CODE1", 0x190c8, 0 },
38762 	{ "SMB_COMMAND_CODE2", 0x190cc, 0 },
38763 	{ "SMB_COMMAND_CODE3", 0x190d0, 0 },
38764 	{ "SMB_COMMAND_CODE4", 0x190d4, 0 },
38765 	{ "SMB_COMMAND_CODE5", 0x190d8, 0 },
38766 	{ "SMB_COMMAND_CODE6", 0x190dc, 0 },
38767 	{ "SMB_COMMAND_CODE7", 0x190e0, 0 },
38768 	{ "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
38770 		{ "MicroCntClkCfg", 0, 8 },
38771 	{ "SMB_CTL_STATUS", 0x190e8, 0 },
38774 		{ "BusBusy", 0, 1 },
38779 	{ "I2CM_CFG", 0x190f0, 0 },
38780 	{ "I2CM_DATA", 0x190f4, 0 },
38781 	{ "I2CM_OP", 0x190f8, 0 },
38785 		{ "Op", 0, 1 },
38790 	{ "MI_CFG", 0x19100, 0 },
38796 		{ "MDIO_1P2V_Sel", 0, 1 },
38797 	{ "MI_ADDR", 0x19104, 0 },
38799 		{ "RegAddr", 0, 5 },
38800 	{ "MI_DATA", 0x19108, 0 },
38801 	{ "MI_OP", 0x1910c, 0 },
38805 		{ "Op", 0, 2 },
38810 	{ "UART_CONFIG", 0x19110, 0 },
38814 		{ "ClkDiv", 0, 12 },
38819 	{ "PMU_PART_CG_PWRMODE", 0x19120, 0 },
38829 		{ "InitPowerMode", 0, 2 },
38830 	{ "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 },
38837 		{ "WakeUp", 0, 1 },
38842 	{ "ULP_RX_CTL", 0x19150, 0 },
38856 		{ "TddpTagTcb", 0, 1 },
38857 	{ "ULP_RX_INT_ENABLE", 0x19154, 0 },
38884 		{ "ENABLE_MPARC_0", 0, 1 },
38885 	{ "ULP_RX_INT_CAUSE", 0x19158, 0 },
38912 		{ "CAUSE_MPARC_0", 0, 1 },
38913 	{ "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
38915 	{ "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
38917 	{ "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 },
38919 	{ "ULP_RX_ISCSI_PSZ", 0x19168, 0 },
38923 		{ "Hpz0", 0, 4 },
38924 	{ "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 },
38926 	{ "ULP_RX_TDDP_ULIMIT", 0x19170, 0 },
38928 	{ "ULP_RX_TDDP_TAGMASK", 0x19174, 0 },
38930 	{ "ULP_RX_TDDP_PSZ", 0x19178, 0 },
38934 		{ "Hpz0", 0, 4 },
38935 	{ "ULP_RX_STAG_LLIMIT", 0x1917c, 0 },
38936 	{ "ULP_RX_STAG_ULIMIT", 0x19180, 0 },
38937 	{ "ULP_RX_RQ_LLIMIT", 0x19184, 0 },
38938 	{ "ULP_RX_RQ_ULIMIT", 0x19188, 0 },
38939 	{ "ULP_RX_PBL_LLIMIT", 0x1918c, 0 },
38940 	{ "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
38941 	{ "ULP_RX_CTX_BASE", 0x19194, 0 },
38942 	{ "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
38969 		{ "PERR_ENABLE_MPARC_0", 0, 1 },
38970 	{ "ULP_RX_PERR_INJECT", 0x191a0, 0 },
38972 		{ "InjectDataErr", 0, 1 },
38973 	{ "ULP_RX_RQUDP_LLIMIT", 0x191a4, 0 },
38974 	{ "ULP_RX_RQUDP_ULIMIT", 0x191a8, 0 },
38975 	{ "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 },
38978 		{ "TID", 0, 20 },
38979 	{ "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 },
38982 		{ "TID", 0, 20 },
38983 	{ "ULP_RX_SE_CNT_ERR", 0x191d0, 0 },
38985 		{ "ERR_CH0", 0, 4 },
38986 	{ "ULP_RX_SE_CNT_CLR", 0x191d4, 0 },
38988 		{ "CLR_CH1", 0, 4 },
38989 	{ "ULP_RX_SE_CNT_CH0", 0x191d8, 0 },
38997 		{ "EOP_CNT_IN0", 0, 4 },
38998 	{ "ULP_RX_SE_CNT_CH1", 0x191dc, 0 },
39006 		{ "EOP_CNT_IN1", 0, 4 },
39007 	{ "ULP_RX_DBG_CTL", 0x191e0, 0 },
39011 		{ "SEL_L", 0, 8 },
39012 	{ "ULP_RX_DBG_DATAH", 0x191e4, 0 },
39013 	{ "ULP_RX_DBG_DATAL", 0x191e8, 0 },
39014 	{ "ULP_RX_LA_CHNL", 0x19238, 0 },
39015 	{ "ULP_RX_LA_CTL", 0x1923c, 0 },
39016 	{ "ULP_RX_LA_RDPTR", 0x19240, 0 },
39017 	{ "ULP_RX_LA_RDDATA", 0x19244, 0 },
39018 	{ "ULP_RX_LA_WRPTR", 0x19248, 0 },
39019 	{ "ULP_RX_LA_RESERVED", 0x1924c, 0 },
39020 	{ "ULP_RX_CQE_GEN_EN", 0x19250, 0 },
39022 		{ "Terminate_with_err", 0, 1 },
39023 	{ "ULP_RX_ATOMIC_OPCODES", 0x19254, 0 },
39031 		{ "immediate_with_se_opcode", 0, 4 },
39032 	{ "ULP_RX_T10_CRC_ENDIAN_SWITCHING", 0x19258, 0 },
39033 	{ "ULP_RX_MISC_FEATURE_ENABLE", 0x1925c, 0 },
39055 		{ "sdc_crc_prot_en", 0, 1 },
39056 	{ "ULP_RX_CH0_CGEN", 0x19260, 0 },
39064 		{ "Rdma_DataPath_CGEN", 0, 1 },
39065 	{ "ULP_RX_CH1_CGEN", 0x19264, 0 },
39073 		{ "Rdma_DataPath_CGEN", 0, 1 },
39074 	{ "ULP_RX_RFE_DISABLE", 0x19268, 0 },
39075 	{ "ULP_RX_INT_ENABLE_2", 0x1926c, 0 },
39084 		{ "DDP_HINT_0", 0, 1 },
39085 	{ "ULP_RX_INT_CAUSE_2", 0x19270, 0 },
39094 		{ "DDP_HINT_0", 0, 1 },
39095 	{ "ULP_RX_PERR_ENABLE_2", 0x19274, 0 },
39104 		{ "ENABLE_DDP_HINT_0", 0, 1 },
39105 	{ "ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT", 0x19278, 0 },
39106 	{ "ULP_RX_ATOMIC_LEN", 0x1927c, 0 },
39109 		{ "atomic_immediate_len", 0, 8 },
39110 	{ "ULP_RX_CGEN_GLOBAL", 0x19280, 0 },
39111 	{ "ULP_RX_CTX_SKIP_MA_REQ", 0x19284, 0 },
39115 		{ "skip_ma_req_en0", 0, 1 },
39116 	{ "ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x19288, 0 },
39117 	{ "ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1928c, 0 },
39118 	{ "ULP_RX_MSN_CHECK_ENABLE", 0x19290, 0 },
39121 		{ "send_msn_check_enable", 0, 1 },
39122 	{ "ULP_RX_TLS_PP_LLIMIT", 0x192a4, 0 },
39124 	{ "ULP_RX_TLS_PP_ULIMIT", 0x192a8, 0 },
39126 	{ "ULP_RX_TLS_KEY_LLIMIT", 0x192ac, 0 },
39128 	{ "ULP_RX_TLS_KEY_ULIMIT", 0x192b0, 0 },
39130 	{ "ULP_RX_TLS_CTL", 0x192bc, 0 },
39134 		{ "TlsDisable", 0, 1 },
39135 	{ "ULP_RX_TLS_IND_CMD", 0x19348, 0 },
39136 	{ "ULP_RX_TLS_IND_DATA", 0x1934c, 0 },
39141 	{ "SF_DATA", 0x193f8, 0 },
39142 	{ "SF_OP", 0x193fc, 0 },
39147 		{ "Op", 0, 1 },
39152 	{ "PL_PF_INT_CAUSE", 0x1e3c0, 0 },
39155 		{ "MPS", 0, 1 },
39156 	{ "PL_PF_INT_ENABLE", 0x1e3c4, 0 },
39159 		{ "MPS", 0, 1 },
39160 	{ "PL_PF_CTL", 0x1e3c8, 0 },
39161 	{ "PL_PF_INT_CAUSE", 0x1e7c0, 0 },
39164 		{ "MPS", 0, 1 },
39165 	{ "PL_PF_INT_ENABLE", 0x1e7c4, 0 },
39168 		{ "MPS", 0, 1 },
39169 	{ "PL_PF_CTL", 0x1e7c8, 0 },
39170 	{ "PL_PF_INT_CAUSE", 0x1ebc0, 0 },
39173 		{ "MPS", 0, 1 },
39174 	{ "PL_PF_INT_ENABLE", 0x1ebc4, 0 },
39177 		{ "MPS", 0, 1 },
39178 	{ "PL_PF_CTL", 0x1ebc8, 0 },
39179 	{ "PL_PF_INT_CAUSE", 0x1efc0, 0 },
39182 		{ "MPS", 0, 1 },
39183 	{ "PL_PF_INT_ENABLE", 0x1efc4, 0 },
39186 		{ "MPS", 0, 1 },
39187 	{ "PL_PF_CTL", 0x1efc8, 0 },
39188 	{ "PL_PF_INT_CAUSE", 0x1f3c0, 0 },
39191 		{ "MPS", 0, 1 },
39192 	{ "PL_PF_INT_ENABLE", 0x1f3c4, 0 },
39195 		{ "MPS", 0, 1 },
39196 	{ "PL_PF_CTL", 0x1f3c8, 0 },
39197 	{ "PL_PF_INT_CAUSE", 0x1f7c0, 0 },
39200 		{ "MPS", 0, 1 },
39201 	{ "PL_PF_INT_ENABLE", 0x1f7c4, 0 },
39204 		{ "MPS", 0, 1 },
39205 	{ "PL_PF_CTL", 0x1f7c8, 0 },
39206 	{ "PL_PF_INT_CAUSE", 0x1fbc0, 0 },
39209 		{ "MPS", 0, 1 },
39210 	{ "PL_PF_INT_ENABLE", 0x1fbc4, 0 },
39213 		{ "MPS", 0, 1 },
39214 	{ "PL_PF_CTL", 0x1fbc8, 0 },
39215 	{ "PL_PF_INT_CAUSE", 0x1ffc0, 0 },
39218 		{ "MPS", 0, 1 },
39219 	{ "PL_PF_INT_ENABLE", 0x1ffc4, 0 },
39222 		{ "MPS", 0, 1 },
39223 	{ "PL_PF_CTL", 0x1ffc8, 0 },
39224 	{ "PL_WHOAMI", 0x19400, 0 },
39229 		{ "VFID", 0, 8 },
39230 	{ "PL_PERR_CAUSE", 0x19404, 0 },
39256 		{ "CIM", 0, 1 },
39257 	{ "PL_PERR_ENABLE", 0x19408, 0 },
39283 		{ "CIM", 0, 1 },
39284 	{ "PL_INT_CAUSE", 0x1940c, 0 },
39313 		{ "CIM", 0, 1 },
39314 	{ "PL_INT_ENABLE", 0x19410, 0 },
39343 		{ "CIM", 0, 1 },
39344 	{ "PL_INT_MAP0", 0x19414, 0 },
39346 		{ "MapDefault", 0, 9 },
39347 	{ "PL_INT_MAP1", 0x19418, 0 },
39349 		{ "MapMAC0", 0, 9 },
39350 	{ "PL_INT_MAP3", 0x19420, 0 },
39352 		{ "MapSMB", 0, 9 },
39353 	{ "PL_INT_MAP4", 0x19424, 0 },
39355 		{ "MapI2CM", 0, 9 },
39356 	{ "PL_RST", 0x19428, 0 },
39361 		{ "PIORstMode", 0, 1 },
39362 	{ "PL_PL_INT_CAUSE", 0x19430, 0 },
39368 	{ "PL_PL_INT_ENABLE", 0x19434, 0 },
39374 	{ "PL_PL_PERR_ENABLE", 0x19438, 0 },
39376 	{ "PL_REV", 0x1943c, 0 },
39378 		{ "Rev", 0, 4 },
39379 	{ "PL_PCIE_LINK", 0x19440, 0 },
39388 		{ "LTSSM", 0, 6 },
39389 	{ "PL_PCIE_CTL_STAT", 0x19444, 0 },
39391 		{ "Control", 0, 16 },
39392 	{ "PL_SEMAPHORE_CTL", 0x1944c, 0 },
39395 		{ "EnablePF", 0, 8 },
39396 	{ "PL_SEMAPHORE_LOCK", 0x19450, 0 },
39399 		{ "SourcePF", 0, 3 },
39400 	{ "PL_SEMAPHORE_LOCK", 0x19454, 0 },
39403 		{ "SourcePF", 0, 3 },
39404 	{ "PL_SEMAPHORE_LOCK", 0x19458, 0 },
39407 		{ "SourcePF", 0, 3 },
39408 	{ "PL_SEMAPHORE_LOCK", 0x1945c, 0 },
39411 		{ "SourcePF", 0, 3 },
39412 	{ "PL_SEMAPHORE_LOCK", 0x19460, 0 },
39415 		{ "SourcePF", 0, 3 },
39416 	{ "PL_SEMAPHORE_LOCK", 0x19464, 0 },
39419 		{ "SourcePF", 0, 3 },
39420 	{ "PL_SEMAPHORE_LOCK", 0x19468, 0 },
39423 		{ "SourcePF", 0, 3 },
39424 	{ "PL_SEMAPHORE_LOCK", 0x1946c, 0 },
39427 		{ "SourcePF", 0, 3 },
39428 	{ "PL_PORTX_MAP", 0x19474, 0 },
39436 		{ "MAP0", 0, 3 },
39437 	{ "PL_VF_SLICE_L", 0x19490, 0 },
39439 		{ "BaseAddr", 0, 10 },
39440 	{ "PL_VF_SLICE_L", 0x19498, 0 },
39442 		{ "BaseAddr", 0, 10 },
39443 	{ "PL_VF_SLICE_L", 0x194a0, 0 },
39445 		{ "BaseAddr", 0, 10 },
39446 	{ "PL_VF_SLICE_L", 0x194a8, 0 },
39448 		{ "BaseAddr", 0, 10 },
39449 	{ "PL_VF_SLICE_L", 0x194b0, 0 },
39451 		{ "BaseAddr", 0, 10 },
39452 	{ "PL_VF_SLICE_L", 0x194b8, 0 },
39454 		{ "BaseAddr", 0, 10 },
39455 	{ "PL_VF_SLICE_L", 0x194c0, 0 },
39457 		{ "BaseAddr", 0, 10 },
39458 	{ "PL_VF_SLICE_L", 0x194c8, 0 },
39460 		{ "BaseAddr", 0, 10 },
39461 	{ "PL_VF_SLICE_H", 0x19494, 0 },
39463 		{ "ModOffset", 0, 10 },
39464 	{ "PL_VF_SLICE_H", 0x1949c, 0 },
39466 		{ "ModOffset", 0, 10 },
39467 	{ "PL_VF_SLICE_H", 0x194a4, 0 },
39469 		{ "ModOffset", 0, 10 },
39470 	{ "PL_VF_SLICE_H", 0x194ac, 0 },
39472 		{ "ModOffset", 0, 10 },
39473 	{ "PL_VF_SLICE_H", 0x194b4, 0 },
39475 		{ "ModOffset", 0, 10 },
39476 	{ "PL_VF_SLICE_H", 0x194bc, 0 },
39478 		{ "ModOffset", 0, 10 },
39479 	{ "PL_VF_SLICE_H", 0x194c4, 0 },
39481 		{ "ModOffset", 0, 10 },
39482 	{ "PL_VF_SLICE_H", 0x194cc, 0 },
39484 		{ "ModOffset", 0, 10 },
39485 	{ "PL_TIMEOUT_CTL", 0x194f0, 0 },
39487 		{ "Timeout", 0, 16 },
39488 	{ "PL_TIMEOUT_STATUS0", 0x194f4, 0 },
39490 	{ "PL_TIMEOUT_STATUS1", 0x194f8, 0 },
39496 		{ "VFID", 0, 9 },
39501 	{ "LE_DB_ID", 0x19c00, 0 },
39502 	{ "LE_DB_CONFIG", 0x19c04, 0 },
39517 		{ "REGION_EN", 0, 4 },
39518 	{ "LE_DB_EXEC_CTRL", 0x19c08, 0 },
39522 		{ "CMDLIMIT", 0, 8 },
39523 	{ "LE_DB_PS_CTRL", 0x19c0c, 0 },
39532 	{ "LE_DB_ACTIVE_TABLE_START_INDEX", 0x19c10, 0 },
39533 	{ "LE_DB_NORM_FILT_TABLE_START_INDEX", 0x19c14, 0 },
39534 	{ "LE_DB_SRVR_START_INDEX", 0x19c18, 0 },
39535 	{ "LE_DB_HPRI_FILT_TABLE_START_INDEX", 0x19c1c, 0 },
39536 	{ "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 },
39537 	{ "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 },
39538 	{ "LE_DB_ACT_CNT_IPV4_TCAM", 0x19c94, 0 },
39539 	{ "LE_DB_ACT_CNT_IPV6_TCAM", 0x19c98, 0 },
39540 	{ "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 },
39542 		{ "ReqCnt", 0, 16 },
39543 	{ "LE_HASH_COLLISION", 0x19fc4, 0 },
39544 	{ "LE_GLOBAL_COLLISION", 0x19fc8, 0 },
39545 	{ "LE_DB_HASH_CONFIG", 0x19c28, 0 },
39548 	{ "LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES", 0x19c2c, 0 },
39549 	{ "LE_DB_MAX_NUM_HASH_ENTRIES", 0x19c70, 0 },
39550 	{ "LE_DB_RSP_CODE_0", 0x19c74, 0 },
39556 		{ "TCAM_ACTV_HIT", 0, 5 },
39557 	{ "LE_DB_RSP_CODE_1", 0x19c78, 0 },
39563 		{ "ACTV_FULL_ERR", 0, 5 },
39564 	{ "LE_DB_RSP_CODE_2", 0x19c7c, 0 },
39570 		{ "INTERNAL_ERR", 0, 5 },
39571 	{ "LE_DB_RSP_CODE_3", 0x19c80, 0 },
39576 	{ "LE_DB_HASH_TBL_BASE_ADDR", 0x19c30, 0 },
39578 	{ "LE_TCAM_SIZE", 0x19c34, 0 },
39579 	{ "LE_DB_INT_ENABLE", 0x19c38, 0 },
39609 		{ "PipelineErr", 0, 1 },
39610 	{ "LE_DB_INT_CAUSE", 0x19c3c, 0 },
39640 		{ "PipelineErr", 0, 1 },
39641 	{ "LE_PERR_ENABLE", 0x19cf8, 0 },
39659 		{ "PipelineErr", 0, 1 },
39660 	{ "LE_DB_ERR_CMD_TID", 0x19c48, 0 },
39663 		{ "ERR_TID", 0, 20 },
39664 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c50, 0 },
39665 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c54, 0 },
39666 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c58, 0 },
39667 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c5c, 0 },
39668 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c60, 0 },
39669 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c64, 0 },
39670 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c68, 0 },
39671 	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c6c, 0 },
39672 	{ "LE_DB_DBG_MATCH_DATA", 0x19ca0, 0 },
39673 	{ "LE_DB_DBG_MATCH_DATA", 0x19ca4, 0 },
39674 	{ "LE_DB_DBG_MATCH_DATA", 0x19ca8, 0 },
39675 	{ "LE_DB_DBG_MATCH_DATA", 0x19cac, 0 },
39676 	{ "LE_DB_DBG_MATCH_DATA", 0x19cb0, 0 },
39677 	{ "LE_DB_DBG_MATCH_DATA", 0x19cb4, 0 },
39678 	{ "LE_DB_DBG_MATCH_DATA", 0x19cb8, 0 },
39679 	{ "LE_DB_DBG_MATCH_DATA", 0x19cbc, 0 },
39680 	{ "LE_DB_DBG_MATCH_CMD_IDX_MASK", 0x19c40, 0 },
39682 		{ "TID_CMP_MASK", 0, 20 },
39683 	{ "LE_DB_DBG_MATCH_CMD_IDX_DATA", 0x19c44, 0 },
39685 		{ "TID_CMP", 0, 20 },
39686 	{ "LE_DB_DBGI_CONFIG", 0x19cf0, 0 },
39696 		{ "DBGICMDMODE", 0, 2 },
39697 	{ "LE_DB_DBGI_REQ_CMD", 0x19cf4, 0 },
39699 		{ "DBGITID", 0, 20 },
39700 	{ "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 },
39701 	{ "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 },
39702 	{ "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 },
39703 	{ "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 },
39704 	{ "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 },
39705 	{ "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 },
39706 	{ "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 },
39707 	{ "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 },
39708 	{ "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 },
39709 	{ "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 },
39710 	{ "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 },
39711 	{ "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 },
39712 	{ "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 },
39713 	{ "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 },
39714 	{ "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 },
39715 	{ "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 },
39716 	{ "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 },
39717 	{ "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 },
39718 	{ "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 },
39719 	{ "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 },
39720 	{ "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 },
39721 	{ "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 },
39722 	{ "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 },
39727 		{ "DBGIRspValid", 0, 1 },
39728 	{ "LE_DBG_SEL", 0x19d98, 0 },
39729 	{ "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 },
39730 	{ "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 },
39731 	{ "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 },
39732 	{ "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 },
39733 	{ "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 },
39734 	{ "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 },
39735 	{ "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 },
39736 	{ "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 },
39737 	{ "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 },
39738 	{ "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 },
39739 	{ "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 },
39740 	{ "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 },
39741 	{ "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 },
39742 	{ "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 },
39743 	{ "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 },
39744 	{ "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 },
39745 	{ "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 },
39746 	{ "LE_DB_TCAM_TID_BASE", 0x19df0, 0 },
39747 	{ "LE_DB_CLCAM_TID_BASE", 0x19df4, 0 },
39748 	{ "LE_DB_HASH_TID_BASE", 0x19df8, 0 },
39749 	{ "LE_DB_SSRAM_TID_BASE", 0x19dfc, 0 },
39750 	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 },
39751 	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 },
39752 	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 },
39753 	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 },
39754 	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 },
39755 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 },
39756 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 },
39757 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 },
39758 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 },
39759 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 },
39760 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 },
39761 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 },
39762 	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 },
39763 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea0, 0 },
39764 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea4, 0 },
39765 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea8, 0 },
39766 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eac, 0 },
39767 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb0, 0 },
39768 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb4, 0 },
39769 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb8, 0 },
39770 	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ebc, 0 },
39771 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec4, 0 },
39772 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec8, 0 },
39773 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ecc, 0 },
39774 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed0, 0 },
39775 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed4, 0 },
39776 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed8, 0 },
39777 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19edc, 0 },
39778 	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ee0, 0 },
39779 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee4, 0 },
39780 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee8, 0 },
39781 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19eec, 0 },
39782 	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef0, 0 },
39783 	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef4, 0 },
39784 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f04, 0 },
39785 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f08, 0 },
39786 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f0c, 0 },
39787 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f10, 0 },
39788 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f14, 0 },
39789 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f18, 0 },
39790 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f1c, 0 },
39791 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f20, 0 },
39792 	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f24, 0 },
39793 	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f28, 0 },
39794 	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f2c, 0 },
39795 	{ "LE_DB_SRVR_SRAM_CONFIG", 0x19f34, 0 },
39800 		{ "SRVRINIT", 0, 1 },
39801 	{ "LE_DB_SRVR_VF_SRCH_TABLE_CTRL", 0x19f38, 0 },
39805 		{ "VFINDEX", 0, 8 },
39806 	{ "LE_DB_SRVR_VF_SRCH_TABLE_DATA", 0x19f3c, 0 },
39808 		{ "SRCHLADDR", 0, 12 },
39809 	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f40, 0 },
39810 	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f44, 0 },
39811 	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f48, 0 },
39812 	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f4c, 0 },
39813 	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f50, 0 },
39814 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f90, 0 },
39815 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f94, 0 },
39816 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f98, 0 },
39817 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f9c, 0 },
39818 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa0, 0 },
39819 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa4, 0 },
39820 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa8, 0 },
39821 	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fac, 0 },
39822 	{ "LE_DEBUG_LA_CONFIG", 0x19fd0, 0 },
39823 	{ "LE_REQ_DEBUG_LA_DATA", 0x19fd4, 0 },
39824 	{ "LE_REQ_DEBUG_LA_WRPTR", 0x19fd8, 0 },
39825 	{ "LE_RSP_DEBUG_LA_DATA", 0x19fdc, 0 },
39826 	{ "LE_RSP_DEBUG_LA_WRPTR", 0x19fe0, 0 },
39827 	{ "LE_DEBUG_LA_SEL_DATA", 0x19fe4, 0 },
39832 	{ "NCSI_PORT_CFGREG", 0x1a000, 0 },
39843 	{ "NCSI_RST_CTRL", 0x1a004, 0 },
39846 		{ "mac_tx_rst", 0, 1 },
39847 	{ "NCSI_CH0_SADDR_LOW", 0x1a010, 0 },
39848 	{ "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 },
39850 		{ "CH0_SADDR_HIGH", 0, 16 },
39851 	{ "NCSI_CH1_SADDR_LOW", 0x1a018, 0 },
39852 	{ "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 },
39854 		{ "CH1_SADDR_HIGH", 0, 16 },
39855 	{ "NCSI_CH2_SADDR_LOW", 0x1a020, 0 },
39856 	{ "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 },
39858 		{ "CH2_SADDR_HIGH", 0, 16 },
39859 	{ "NCSI_CH3_SADDR_LOW", 0x1a028, 0 },
39860 	{ "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 },
39862 		{ "CH3_SADDR_HIGH", 0, 16 },
39863 	{ "NCSI_WORK_REQHDR_0", 0x1a030, 0 },
39864 	{ "NCSI_WORK_REQHDR_1", 0x1a034, 0 },
39865 	{ "NCSI_WORK_REQHDR_2", 0x1a038, 0 },
39866 	{ "NCSI_WORK_REQHDR_3", 0x1a03c, 0 },
39867 	{ "NCSI_MPS_HDR_LO", 0x1a040, 0 },
39868 	{ "NCSI_MPS_HDR_HI", 0x1a044, 0 },
39869 	{ "NCSI_CTL", 0x1a048, 0 },
39873 		{ "FWD_BMC", 0, 1 },
39874 	{ "NCSI_NCSI_ETYPE", 0x1a04c, 0 },
39875 	{ "NCSI_RX_FIFO_CNT", 0x1a050, 0 },
39876 	{ "NCSI_RX_ERR_CNT", 0x1a054, 0 },
39877 	{ "NCSI_RX_OF_CNT", 0x1a058, 0 },
39878 	{ "NCSI_RX_MS_CNT", 0x1a05c, 0 },
39879 	{ "NCSI_RX_IE_CNT", 0x1a060, 0 },
39880 	{ "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 },
39882 		{ "MPS2BMC_CNT", 0, 9 },
39883 	{ "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 },
39885 		{ "CIM2BMC_CNT", 0, 9 },
39886 	{ "NCSI_TX_FIFO_CNT", 0x1a06c, 0 },
39887 	{ "NCSI_SE_CNT_CTL", 0x1a0b0, 0 },
39888 	{ "NCSI_SE_CNT_MPS", 0x1a0b4, 0 },
39889 	{ "NCSI_SE_CNT_CIM", 0x1a0b8, 0 },
39890 	{ "NCSI_BUS_DEBUG", 0x1a0bc, 0 },
39891 	{ "NCSI_LA_RDPTR", 0x1a0c0, 0 },
39892 	{ "NCSI_LA_RDDATA", 0x1a0c4, 0 },
39893 	{ "NCSI_LA_WRPTR", 0x1a0c8, 0 },
39894 	{ "NCSI_LA_RESERVED", 0x1a0cc, 0 },
39895 	{ "NCSI_LA_CTL", 0x1a0d0, 0 },
39896 	{ "NCSI_INT_ENABLE", 0x1a0d4, 0 },
39905 		{ "RXFIFO_prty_err", 0, 1 },
39906 	{ "NCSI_INT_CAUSE", 0x1a0d8, 0 },
39915 		{ "RXFIFO_prty_err", 0, 1 },
39916 	{ "NCSI_STATUS", 0x1a0dc, 0 },
39918 		{ "arb_status", 0, 1 },
39919 	{ "NCSI_PAUSE_CTRL", 0x1a0e0, 0 },
39920 	{ "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 },
39921 	{ "NCSI_PAUSE_WM", 0x1a0ec, 0 },
39923 		{ "PauseLWM", 0, 11 },
39924 	{ "NCSI_DEBUG", 0x1a0f0, 0 },
39927 		{ "PKG_ID", 0, 3 },
39928 	{ "NCSI_PERR_INJECT", 0x1a0f4, 0 },
39930 		{ "InjectDataErr", 0, 1 },
39931 	{ "NCSI_PERR_ENABLE", 0x1a0f8, 0 },
39935 		{ "RXFIFO_prty_err", 0, 1 },
39936 	{ "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 },
39949 		{ "LoopPHY", 0, 1 },
39950 	{ "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 },
39971 		{ "Speed", 0, 1 },
39972 	{ "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 },
39975 		{ "LinkStatus", 0, 1 },
39976 	{ "NCSI_MACB_TX_STATUS", 0x1a114, 0 },
39983 		{ "UsedBitRead", 0, 1 },
39984 	{ "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 },
39986 	{ "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 },
39988 	{ "NCSI_MACB_RX_STATUS", 0x1a120, 0 },
39991 		{ "NoRxBuf", 0, 1 },
39992 	{ "NCSI_MACB_INT_STATUS", 0x1a124, 0 },
40005 		{ "MgmtFrameSent", 0, 1 },
40006 	{ "NCSI_MACB_INT_EN", 0x1a128, 0 },
40019 		{ "MgmtFrameSent", 0, 1 },
40020 	{ "NCSI_MACB_INT_DIS", 0x1a12c, 0 },
40033 		{ "MgmtFrameSent", 0, 1 },
40034 	{ "NCSI_MACB_INT_MASK", 0x1a130, 0 },
40047 		{ "MgmtFrameSent", 0, 1 },
40048 	{ "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 },
40049 	{ "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 },
40050 	{ "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 },
40051 	{ "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 },
40052 	{ "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 },
40053 	{ "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 },
40054 	{ "NCSI_MACB_FCS_ERR", 0x1a150, 0 },
40055 	{ "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 },
40056 	{ "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 },
40057 	{ "NCSI_MACB_LATE_COL", 0x1a15c, 0 },
40058 	{ "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 },
40059 	{ "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 },
40060 	{ "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 },
40061 	{ "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 },
40062 	{ "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 },
40063 	{ "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 },
40064 	{ "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 },
40065 	{ "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 },
40066 	{ "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 },
40067 	{ "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 },
40068 	{ "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 },
40069 	{ "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 },
40070 	{ "NCSI_MACB_HASH_LOW", 0x1a190, 0 },
40071 	{ "NCSI_MACB_HASH_HIGH", 0x1a194, 0 },
40072 	{ "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 },
40073 	{ "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 },
40074 	{ "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 },
40075 	{ "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 },
40076 	{ "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 },
40077 	{ "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 },
40078 	{ "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 },
40079 	{ "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 },
40080 	{ "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 },
40081 	{ "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 },
40082 	{ "NCSI_MACB_USER_IO", 0x1a1c0, 0 },
40084 		{ "UserProgOutput", 0, 16 },
40085 	{ "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 },
40090 		{ "ARPIPAddr", 0, 16 },
40091 	{ "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
40093 		{ "DesRev", 0, 16 },
40098 	{ "MAC_PORT_CFG", 0x30800, 0 },
40123 		{ "Port_Sel", 0, 1 },
40124 	{ "MAC_PORT_RESET_CTRL", 0x30804, 0 },
40156 		{ "HSS_Reset", 0, 1 },
40157 	{ "MAC_PORT_LED_CFG", 0x30808, 0 },
40167 		{ "Led0_Polarity_Inv", 0, 1 },
40168 	{ "MAC_PORT_LED_COUNTHI", 0x3080c, 0 },
40169 	{ "MAC_PORT_LED_COUNTLO", 0x30810, 0 },
40170 	{ "MAC_PORT_CFG3", 0x30814, 0 },
40185 		{ "HSSC16C20SEL", 0, 4 },
40186 	{ "MAC_PORT_CFG2", 0x30818, 0 },
40195 		{ "T5_AEC_PMA_RX_READY", 0, 4 },
40196 	{ "MAC_PORT_PKT_COUNT", 0x3081c, 0 },
40200 		{ "rx_eop_count", 0, 8 },
40201 	{ "MAC_PORT_CFG4", 0x30820, 0 },
40209 		{ "AEC0_TX_WIDTH", 0, 2 },
40210 	{ "MAC_PORT_MAGIC_MACID_LO", 0x30824, 0 },
40211 	{ "MAC_PORT_MAGIC_MACID_HI", 0x30828, 0 },
40212 	{ "MAC_PORT_MTIP_RESET_CTRL", 0x3082c, 0 },
40244 		{ "xgmii_clk_reset", 0, 1 },
40245 	{ "MAC_PORT_MTIP_GATE_CTRL", 0x30830, 0 },
40277 		{ "an_clk_enable", 0, 1 },
40278 	{ "MAC_PORT_LINK_STATUS", 0x30834, 0 },
40286 		{ "linkdn", 0, 1 },
40287 	{ "MAC_PORT_AEC_ADD_CTL_STAT_0", 0x30838, 0 },
40295 		{ "AEC_SYS_LANE_SELECT_O", 0, 2 },
40296 	{ "MAC_PORT_AEC_ADD_CTL_STAT_1", 0x3083c, 0 },
40304 		{ "AEC_RX_LANE_ID_O", 0, 2 },
40305 	{ "MAC_PORT_AEC_XGMII_TIMER_LO_40G", 0x30840, 0 },
40306 	{ "MAC_PORT_AEC_XGMII_TIMER_HI_40G", 0x30844, 0 },
40307 	{ "MAC_PORT_AEC_XGMII_TIMER_LO_100G", 0x30848, 0 },
40308 	{ "MAC_PORT_AEC_XGMII_TIMER_HI_100G", 0x3084c, 0 },
40309 	{ "MAC_PORT_AEC_DEBUG_LO_0", 0x30850, 0 },
40325 		{ "REG_MAN_DEC_REQ", 0, 1 },
40326 	{ "MAC_PORT_AEC_DEBUG_HI_0", 0x30854, 0 },
40331 		{ "LCK_FSM_CUR_STATE", 0, 3 },
40332 	{ "MAC_PORT_AEC_DEBUG_LO_1", 0x30858, 0 },
40348 		{ "REG_MAN_DEC_REQ", 0, 1 },
40349 	{ "MAC_PORT_AEC_DEBUG_HI_1", 0x3085c, 0 },
40354 		{ "LCK_FSM_CUR_STATE", 0, 3 },
40355 	{ "MAC_PORT_AEC_DEBUG_LO_2", 0x30860, 0 },
40371 		{ "REG_MAN_DEC_REQ", 0, 1 },
40372 	{ "MAC_PORT_AEC_DEBUG_HI_2", 0x30864, 0 },
40377 		{ "LCK_FSM_CUR_STATE", 0, 3 },
40378 	{ "MAC_PORT_AEC_DEBUG_LO_3", 0x30868, 0 },
40394 		{ "REG_MAN_DEC_REQ", 0, 1 },
40395 	{ "MAC_PORT_AEC_DEBUG_HI_3", 0x3086c, 0 },
40400 		{ "LCK_FSM_CUR_STATE", 0, 3 },
40401 	{ "MAC_PORT_MAC_DEBUG_RO", 0x30870, 0 },
40414 		{ "mac1g10g_tx_underflow", 0, 1 },
40415 	{ "MAC_PORT_MAC_CTRL_RW", 0x30874, 0 },
40425 		{ "mac1g_loop_bck", 0, 1 },
40426 	{ "MAC_PORT_PCS_DEBUG0_RO", 0x30878, 0 },
40445 		{ "sgmii_sg_speed", 0, 2 },
40446 	{ "MAC_PORT_PCS_CTRL_RW", 0x3087c, 0 },
40457 		{ "sgmii_tx_lane_thresh", 0, 4 },
40458 	{ "MAC_PORT_PCS_DEBUG1_RO", 0x30880, 0 },
40461 		{ "pcs100g_block_lock", 0, 20 },
40462 	{ "MAC_PORT_PERR_INT_EN_100G", 0x30884, 0 },
40492 		{ "Perr_rx0_pcs100g", 0, 1 },
40493 	{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x30888, 0 },
40523 		{ "Perr_rx0_pcs100g", 0, 1 },
40524 	{ "MAC_PORT_PERR_ENABLE_100G", 0x3088c, 0 },
40554 		{ "Perr_rx0_pcs100g", 0, 1 },
40555 	{ "MAC_PORT_MAC_STAT_DEBUG", 0x30890, 0 },
40556 	{ "MAC_PORT_MAC_25G_50G_AM0", 0x30894, 0 },
40557 	{ "MAC_PORT_MAC_25G_50G_AM1", 0x30898, 0 },
40558 	{ "MAC_PORT_MAC_25G_50G_AM2", 0x3089c, 0 },
40559 	{ "MAC_PORT_MAC_25G_50G_AM3", 0x308a0, 0 },
40560 	{ "MAC_PORT_MAC_AN_STATE_STATUS", 0x308a4, 0 },
40561 	{ "MAC_PORT_EPIO_DATA0", 0x308c0, 0 },
40562 	{ "MAC_PORT_EPIO_DATA1", 0x308c4, 0 },
40563 	{ "MAC_PORT_EPIO_DATA2", 0x308c8, 0 },
40564 	{ "MAC_PORT_EPIO_DATA3", 0x308cc, 0 },
40565 	{ "MAC_PORT_EPIO_OP", 0x308d0, 0 },
40568 		{ "Address", 0, 8 },
40569 	{ "MAC_PORT_WOL_STATUS", 0x308d4, 0 },
40574 		{ "MatchedFilter", 0, 3 },
40575 	{ "MAC_PORT_INT_EN", 0x308d8, 0 },
40598 		{ "RxFifo_prty_err", 0, 1 },
40599 	{ "MAC_PORT_INT_CAUSE", 0x308dc, 0 },
40622 		{ "RxFifo_prty_err", 0, 1 },
40623 	{ "MAC_PORT_PERR_INT_EN", 0x308e0, 0 },
40655 		{ "Perr_tx_pcs1g", 0, 1 },
40656 	{ "MAC_PORT_PERR_INT_CAUSE", 0x308e4, 0 },
40688 		{ "Perr_tx_pcs1g", 0, 1 },
40689 	{ "MAC_PORT_PERR_ENABLE", 0x308e8, 0 },
40721 		{ "Perr_tx_pcs1g", 0, 1 },
40722 	{ "MAC_PORT_PERR_INJECT", 0x308ec, 0 },
40724 		{ "InjectDataErr", 0, 1 },
40725 	{ "MAC_PORT_HSS_CFG0", 0x308f0, 0 },
40751 	{ "MAC_PORT_HSS_CFG1", 0x308f4, 0 },
40775 		{ "TXDREFRESH", 0, 1 },
40776 	{ "MAC_PORT_HSS_CFG2", 0x308f8, 0 },
40808 		{ "RXAPHSUPIN", 0, 1 },
40809 	{ "MAC_PORT_HSS_CFG3", 0x308fc, 0 },
40813 		{ "HSSPLLCONFIGA", 0, 8 },
40814 	{ "MAC_PORT_HSS_CFG4", 0x30900, 0 },
40820 		{ "HSSDIVSELB", 0, 9 },
40821 	{ "MAC_PORT_HSS_STATUS", 0x30904, 0 },
40841 		{ "HSSPRTREADYA", 0, 1 },
40842 	{ "MAC_PORT_HSS_EEE_STATUS", 0x30908, 0 },
40858 		{ "TXDREFRESH_STATUS", 0, 1 },
40859 	{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3090c, 0 },
40860 	{ "MAC_PORT_HSS_PL_CTL", 0x30910, 0 },
40863 		{ "IPW", 0, 8 },
40864 	{ "MAC_PORT_RUNT_FRAME", 0x30914, 0 },
40866 		{ "runt", 0, 16 },
40867 	{ "MAC_PORT_EEE_STATUS", 0x30918, 0 },
40875 		{ "pma_tx_quiet", 0, 1 },
40876 	{ "MAC_PORT_CGEN", 0x3091c, 0 },
40885 		{ "sd0_CGEN", 0, 1 },
40886 	{ "MAC_PORT_CGEN_MTIP", 0x30920, 0 },
40898 		{ "PCSSEG0_CGEN", 0, 1 },
40899 	{ "MAC_PORT_TX_TS_ID", 0x30924, 0 },
40900 	{ "MAC_PORT_TX_TS_VAL_LO", 0x30928, 0 },
40901 	{ "MAC_PORT_TX_TS_VAL_HI", 0x3092c, 0 },
40902 	{ "MAC_PORT_EEE_CTL", 0x30930, 0 },
40905 		{ "En", 0, 1 },
40906 	{ "MAC_PORT_EEE_TX_CTL", 0x30934, 0 },
40913 		{ "EEE_TX_RESET", 0, 1 },
40914 	{ "MAC_PORT_EEE_RX_CTL", 0x30938, 0 },
40919 		{ "EEE_RX_RESET", 0, 1 },
40920 	{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3093c, 0 },
40921 	{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x30940, 0 },
40922 	{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x30944, 0 },
40923 	{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x30948, 0 },
40924 	{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3094c, 0 },
40925 	{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x30950, 0 },
40926 	{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x30954, 0 },
40927 	{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x30958, 0 },
40928 	{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3095c, 0 },
40929 	{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x30960, 0 },
40930 	{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x30964, 0 },
40931 	{ "MAC_PORT_EEE_WF_COUNT", 0x30968, 0 },
40933 		{ "wake_cnt", 0, 16 },
40934 	{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3096c, 0 },
40935 	{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x30970, 0 },
40936 	{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x30974, 0 },
40937 	{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x30978, 0 },
40938 	{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3097c, 0 },
40939 	{ "MAC_PORT_PTP_TIMER_WR_HI", 0x30980, 0 },
40940 	{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x30984, 0 },
40941 	{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x30988, 0 },
40942 	{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3098c, 0 },
40943 	{ "MAC_PORT_PTP_SUM_LO", 0x30990, 0 },
40944 	{ "MAC_PORT_PTP_SUM_HI", 0x30994, 0 },
40945 	{ "MAC_PORT_PTP_TIMER_INCR0", 0x30998, 0 },
40947 		{ "X", 0, 16 },
40948 	{ "MAC_PORT_PTP_TIMER_INCR1", 0x3099c, 0 },
40950 		{ "X_TICK", 0, 16 },
40951 	{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x309a0, 0 },
40952 	{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x309a4, 0 },
40954 		{ "A", 0, 16 },
40955 	{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x309a8, 0 },
40956 	{ "MAC_PORT_PTP_CFG", 0x309ac, 0 },
40964 		{ "Q", 0, 8 },
40965 	{ "MAC_PORT_PTP_PPS", 0x309b0, 0 },
40966 	{ "MAC_PORT_PTP_SINGLE_ALARM", 0x309b4, 0 },
40967 	{ "MAC_PORT_PTP_PERIODIC_ALARM", 0x309b8, 0 },
40968 	{ "MAC_PORT_PTP_STATUS", 0x309bc, 0 },
40969 	{ "MAC_PORT_MTIP_REVISION", 0x30a00, 0 },
40972 		{ "REV", 0, 8 },
40973 	{ "MAC_PORT_MTIP_SCRATCH", 0x30a04, 0 },
40974 	{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x30a08, 0 },
40996 		{ "TX_ENA", 0, 1 },
40997 	{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x30a0c, 0 },
40998 	{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x30a10, 0 },
40999 	{ "MAC_PORT_MTIP_FRM_LENGTH", 0x30a14, 0 },
41000 	{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x30a1c, 0 },
41002 		{ "EMPTY", 0, 16 },
41003 	{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x30a20, 0 },
41005 		{ "EMPTY", 0, 16 },
41006 	{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x30a24, 0 },
41008 		{ "AlmstEmpty", 0, 16 },
41009 	{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x30a28, 0 },
41011 		{ "AlmstEmpty", 0, 16 },
41012 	{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x30a2c, 0 },
41014 		{ "ADDR", 0, 6 },
41015 	{ "MAC_PORT_MTIP_MAC_STATUS", 0x30a40, 0 },
41019 		{ "RX_LOC_FAULT", 0, 1 },
41020 	{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x30a44, 0 },
41021 	{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x30a48, 0 },
41022 	{ "MAC_PORT_MTIP_INIT_CREDIT", 0x30a4c, 0 },
41023 	{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x30a50, 0 },
41024 	{ "MAC_PORT_RX_PAUSE_STATUS", 0x30a74, 0 },
41025 	{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x30a7c, 0 },
41026 	{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x30a80, 0 },
41027 	{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x30a84, 0 },
41028 	{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x30a88, 0 },
41029 	{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x30a8c, 0 },
41030 	{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x30a90, 0 },
41031 	{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x30a94, 0 },
41032 	{ "MAC_PORT_AALIGNMENTERRORS", 0x30a98, 0 },
41033 	{ "MAC_PORT_AALIGNMENTERRORSHI", 0x30a9c, 0 },
41034 	{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x30aa0, 0 },
41035 	{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x30aa4, 0 },
41036 	{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x30aa8, 0 },
41037 	{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x30aac, 0 },
41038 	{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x30ab0, 0 },
41039 	{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x30ab4, 0 },
41040 	{ "MAC_PORT_AINRANGELENGTHERRORS", 0x30ab8, 0 },
41041 	{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x30abc, 0 },
41042 	{ "MAC_PORT_VLANTRANSMITTEDOK", 0x30ac0, 0 },
41043 	{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x30ac4, 0 },
41044 	{ "MAC_PORT_VLANRECEIVEDOK", 0x30ac8, 0 },
41045 	{ "MAC_PORT_VLANRECEIVEDOKHI", 0x30acc, 0 },
41046 	{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x30ad0, 0 },
41047 	{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x30ad4, 0 },
41048 	{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x30ad8, 0 },
41049 	{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x30adc, 0 },
41050 	{ "MAC_PORT_IFINUCASTPKTS", 0x30ae0, 0 },
41051 	{ "MAC_PORT_IFINUCASTPKTSHI", 0x30ae4, 0 },
41052 	{ "MAC_PORT_IFINMULTICASTPKTS", 0x30ae8, 0 },
41053 	{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x30aec, 0 },
41054 	{ "MAC_PORT_IFINBROADCASTPKTS", 0x30af0, 0 },
41055 	{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x30af4, 0 },
41056 	{ "MAC_PORT_IFOUTERRORS", 0x30af8, 0 },
41057 	{ "MAC_PORT_IFOUTERRORSHI", 0x30afc, 0 },
41058 	{ "MAC_PORT_IFOUTUCASTPKTS", 0x30b08, 0 },
41059 	{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x30b0c, 0 },
41060 	{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x30b10, 0 },
41061 	{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x30b14, 0 },
41062 	{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x30b18, 0 },
41063 	{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x30b1c, 0 },
41064 	{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x30b20, 0 },
41065 	{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x30b24, 0 },
41066 	{ "MAC_PORT_ETHERSTATSOCTETS", 0x30b28, 0 },
41067 	{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x30b2c, 0 },
41068 	{ "MAC_PORT_ETHERSTATSPKTS", 0x30b30, 0 },
41069 	{ "MAC_PORT_ETHERSTATSPKTSHI", 0x30b34, 0 },
41070 	{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x30b38, 0 },
41071 	{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x30b3c, 0 },
41072 	{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x30b40, 0 },
41073 	{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x30b44, 0 },
41074 	{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x30b48, 0 },
41075 	{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x30b4c, 0 },
41076 	{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x30b50, 0 },
41077 	{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x30b54, 0 },
41078 	{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x30b58, 0 },
41079 	{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x30b5c, 0 },
41080 	{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x30b60, 0 },
41081 	{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30b64, 0 },
41082 	{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x30b68, 0 },
41083 	{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30b6c, 0 },
41084 	{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x30b70, 0 },
41085 	{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x30b74, 0 },
41086 	{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x30b78, 0 },
41087 	{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x30b7c, 0 },
41088 	{ "MAC_PORT_ETHERSTATSJABBERS", 0x30b80, 0 },
41089 	{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x30b84, 0 },
41090 	{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x30b88, 0 },
41091 	{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x30b8c, 0 },
41092 	{ "MAC_PORT_IFINERRORS", 0x30b90, 0 },
41093 	{ "MAC_PORT_IFINERRORSHI", 0x30b94, 0 },
41094 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x30b98, 0 },
41095 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x30b9c, 0 },
41096 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x30ba0, 0 },
41097 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x30ba4, 0 },
41098 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x30ba8, 0 },
41099 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x30bac, 0 },
41100 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x30bb0, 0 },
41101 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x30bb4, 0 },
41102 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x30bb8, 0 },
41103 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x30bbc, 0 },
41104 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x30bc0, 0 },
41105 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x30bc4, 0 },
41106 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x30bc8, 0 },
41107 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x30bcc, 0 },
41108 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x30bd0, 0 },
41109 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x30bd4, 0 },
41110 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x30bd8, 0 },
41111 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x30bdc, 0 },
41112 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x30be0, 0 },
41113 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x30be4, 0 },
41114 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x30be8, 0 },
41115 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x30bec, 0 },
41116 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x30bf0, 0 },
41117 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x30bf4, 0 },
41118 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x30bf8, 0 },
41119 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x30bfc, 0 },
41120 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x30c00, 0 },
41121 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x30c04, 0 },
41122 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x30c08, 0 },
41123 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x30c0c, 0 },
41124 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x30c10, 0 },
41125 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x30c14, 0 },
41126 	{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x30c18, 0 },
41127 	{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x30c1c, 0 },
41128 	{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x30c20, 0 },
41129 	{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x30c24, 0 },
41130 	{ "MAC_PORT_MTIP_1G10G_REVISION", 0x30d00, 0 },
41133 		{ "REV", 0, 8 },
41134 	{ "MAC_PORT_MTIP_1G10G_SCRATCH", 0x30d04, 0 },
41135 	{ "MAC_PORT_MTIP_1G10G_COMMAND_CONFIG", 0x30d08, 0 },
41160 		{ "TX_ENAMAC", 0, 1 },
41161 	{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_0", 0x30d0c, 0 },
41162 	{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_1", 0x30d10, 0 },
41163 	{ "MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU", 0x30d14, 0 },
41165 		{ "FRM_LEN_SET", 0, 16 },
41166 	{ "MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS", 0x30d1c, 0 },
41168 		{ "AVAIL", 0, 16 },
41169 	{ "MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS", 0x30d20, 0 },
41171 		{ "AVAIL", 0, 16 },
41172 	{ "MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E", 0x30d24, 0 },
41174 		{ "AlmostEmpty", 0, 16 },
41175 	{ "MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E", 0x30d28, 0 },
41177 		{ "AlmostEmpty", 0, 16 },
41178 	{ "MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD", 0x30d2c, 0 },
41179 	{ "MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS", 0x30d30, 0 },
41185 		{ "MDIO_Busy", 0, 1 },
41186 	{ "MAC_PORT_MTIP_1G10G_MDIO_COMMAND", 0x30d34, 0 },
41190 		{ "Device_Reg_Addr", 0, 5 },
41191 	{ "MAC_PORT_MTIP_1G10G_MDIO_DATA", 0x30d38, 0 },
41192 	{ "MAC_PORT_MTIP_1G10G_MDIO_REGADDR", 0x30d3c, 0 },
41193 	{ "MAC_PORT_MTIP_1G10G_STATUS", 0x30d40, 0 },
41201 		{ "RX_LOC_FAULT", 0, 1 },
41202 	{ "MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH", 0x30d44, 0 },
41203 	{ "MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER", 0x30d48, 0 },
41204 	{ "MAC_PORT_MTIP_1G10G_INIT_CREDIT", 0x30d4c, 0 },
41205 	{ "MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA", 0x30d54, 0 },
41207 		{ "CL0_PAUSE_QUANTA", 0, 16 },
41208 	{ "MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA", 0x30d58, 0 },
41210 		{ "CL2_PAUSE_QUANTA", 0, 16 },
41211 	{ "MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA", 0x30d5c, 0 },
41213 		{ "CL4_PAUSE_QUANTA", 0, 16 },
41214 	{ "MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA", 0x30d60, 0 },
41216 		{ "CL6_PAUSE_QUANTA", 0, 16 },
41217 	{ "MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH", 0x30d64, 0 },
41219 		{ "CL0_QUANTA_THRESH", 0, 16 },
41220 	{ "MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH", 0x30d68, 0 },
41222 		{ "CL2_QUANTA_THRESH", 0, 16 },
41223 	{ "MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH", 0x30d6c, 0 },
41225 		{ "CL4_QUANTA_THRESH", 0, 16 },
41226 	{ "MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH", 0x30d70, 0 },
41228 		{ "CL6_QUANTA_THRESH", 0, 16 },
41229 	{ "MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS", 0x30d74, 0 },
41230 	{ "MAC_PORT_MTIP_1G10G_TS_TIMESTAMP", 0x30d7c, 0 },
41231 	{ "MAC_PORT_MTIP_1G10G_STATN_CONFIG", 0x30de0, 0 },
41234 		{ "SATURATE", 0, 1 },
41235 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS", 0x30e00, 0 },
41236 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI", 0x30e04, 0 },
41237 	{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOK", 0x30e08, 0 },
41238 	{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI", 0x30e0c, 0 },
41239 	{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS", 0x30e10, 0 },
41240 	{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI", 0x30e14, 0 },
41241 	{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES", 0x30e18, 0 },
41242 	{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI", 0x30e1c, 0 },
41243 	{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOK", 0x30e20, 0 },
41244 	{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI", 0x30e24, 0 },
41245 	{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORS", 0x30e28, 0 },
41246 	{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI", 0x30e2c, 0 },
41247 	{ "MAC_PORT_MTIP_1G10G_RX_VLANOK", 0x30e30, 0 },
41248 	{ "MAC_PORT_MTIP_1G10G_RX_VLANOKHI", 0x30e34, 0 },
41249 	{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORS", 0x30e38, 0 },
41250 	{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI", 0x30e3c, 0 },
41251 	{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS", 0x30e40, 0 },
41252 	{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI", 0x30e44, 0 },
41253 	{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS", 0x30e48, 0 },
41254 	{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI", 0x30e4c, 0 },
41255 	{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS", 0x30e50, 0 },
41256 	{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI", 0x30e54, 0 },
41257 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS", 0x30e58, 0 },
41258 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI", 0x30e5c, 0 },
41259 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS", 0x30e60, 0 },
41260 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI", 0x30e64, 0 },
41261 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS", 0x30e68, 0 },
41262 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI", 0x30e6c, 0 },
41263 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS", 0x30e70, 0 },
41264 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI", 0x30e74, 0 },
41265 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS", 0x30e78, 0 },
41266 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI", 0x30e7c, 0 },
41267 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS", 0x30e80, 0 },
41268 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI", 0x30e84, 0 },
41269 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS", 0x30e88, 0 },
41270 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI", 0x30e8c, 0 },
41271 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS", 0x30e90, 0 },
41272 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30e94, 0 },
41273 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS", 0x30e98, 0 },
41274 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30e9c, 0 },
41275 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX", 0x30ea0, 0 },
41276 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI", 0x30ea4, 0 },
41277 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS", 0x30ea8, 0 },
41278 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI", 0x30eac, 0 },
41279 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS", 0x30eb0, 0 },
41280 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI", 0x30eb4, 0 },
41281 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS", 0x30eb8, 0 },
41282 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI", 0x30ebc, 0 },
41283 	{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED", 0x30ec0, 0 },
41284 	{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI", 0x30ec4, 0 },
41285 	{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG", 0x30ec8, 0 },
41286 	{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI", 0x30ecc, 0 },
41287 	{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS", 0x30ed0, 0 },
41288 	{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI", 0x30ed4, 0 },
41289 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS", 0x30f00, 0 },
41290 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI", 0x30f04, 0 },
41291 	{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOK", 0x30f08, 0 },
41292 	{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI", 0x30f0c, 0 },
41293 	{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS", 0x30f10, 0 },
41294 	{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI", 0x30f14, 0 },
41295 	{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES", 0x30f18, 0 },
41296 	{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI", 0x30f1c, 0 },
41297 	{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOK", 0x30f20, 0 },
41298 	{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI", 0x30f24, 0 },
41299 	{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORS", 0x30f28, 0 },
41300 	{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI", 0x30f2c, 0 },
41301 	{ "MAC_PORT_MTIP_1G10G_TX_VLANOK", 0x30f30, 0 },
41302 	{ "MAC_PORT_MTIP_1G10G_TX_VLANOKHI", 0x30f34, 0 },
41303 	{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS", 0x30f38, 0 },
41304 	{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI", 0x30f3c, 0 },
41305 	{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS", 0x30f40, 0 },
41306 	{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI", 0x30f44, 0 },
41307 	{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS", 0x30f48, 0 },
41308 	{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI", 0x30f4c, 0 },
41309 	{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS", 0x30f50, 0 },
41310 	{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI", 0x30f54, 0 },
41311 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS", 0x30f58, 0 },
41312 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI", 0x30f5c, 0 },
41313 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS", 0x30f60, 0 },
41314 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI", 0x30f64, 0 },
41315 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS", 0x30f68, 0 },
41316 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI", 0x30f6c, 0 },
41317 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS", 0x30f70, 0 },
41318 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI", 0x30f74, 0 },
41319 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS", 0x30f78, 0 },
41320 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI", 0x30f7c, 0 },
41321 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS", 0x30f80, 0 },
41322 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI", 0x30f84, 0 },
41323 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS", 0x30f88, 0 },
41324 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI", 0x30f8c, 0 },
41325 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS", 0x30f90, 0 },
41326 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30f94, 0 },
41327 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS", 0x30f98, 0 },
41328 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30f9c, 0 },
41329 	{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU", 0x30fa0, 0 },
41330 	{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI", 0x30fa4, 0 },
41331 	{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES", 0x30fc0, 0 },
41332 	{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI", 0x30fc4, 0 },
41333 	{ "MAC_PORT_MTIP_1G10G_IF_MODE", 0x31000, 0 },
41335 		{ "IF_MODE", 0, 2 },
41336 	{ "MAC_PORT_MTIP_1G10G_IF_STATUS", 0x31004, 0 },
41337 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0", 0x31080, 0 },
41338 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI", 0x31084, 0 },
41339 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1", 0x31088, 0 },
41340 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI", 0x3108c, 0 },
41341 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2", 0x31090, 0 },
41342 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI", 0x31094, 0 },
41343 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3", 0x31098, 0 },
41344 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI", 0x3109c, 0 },
41345 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4", 0x310a0, 0 },
41346 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI", 0x310a4, 0 },
41347 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5", 0x310a8, 0 },
41348 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI", 0x310ac, 0 },
41349 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6", 0x310b0, 0 },
41350 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI", 0x310b4, 0 },
41351 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7", 0x310b8, 0 },
41352 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI", 0x310bc, 0 },
41353 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0", 0x310c0, 0 },
41354 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI", 0x310c4, 0 },
41355 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1", 0x310c8, 0 },
41356 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI", 0x310cc, 0 },
41357 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2", 0x310d0, 0 },
41358 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI", 0x310d4, 0 },
41359 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3", 0x310d8, 0 },
41360 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI", 0x310dc, 0 },
41361 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4", 0x310e0, 0 },
41362 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI", 0x310e4, 0 },
41363 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5", 0x310e8, 0 },
41364 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI", 0x310ec, 0 },
41365 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6", 0x310f0, 0 },
41366 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI", 0x310f4, 0 },
41367 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7", 0x310f8, 0 },
41368 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI", 0x310fc, 0 },
41369 	{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x31200, 0 },
41380 	{ "MAC_PORT_MTIP_SGMII_STATUS", 0x31204, 0 },
41394 		{ "ExtdCapability", 0, 1 },
41395 	{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x31208, 0 },
41396 	{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3120c, 0 },
41397 	{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x31210, 0 },
41406 	{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x31214, 0 },
41411 	{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x31218, 0 },
41414 	{ "MAC_PORT_MTIP_SGMII_NP_TX", 0x3121c, 0 },
41415 	{ "MAC_PORT_MTIP_SGMII_LP_NP_RX", 0x31220, 0 },
41416 	{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3123c, 0 },
41417 	{ "MAC_PORT_MTIP_SGMII_SCRATCH", 0x31240, 0 },
41418 	{ "MAC_PORT_MTIP_SGMII_REV", 0x31244, 0 },
41421 		{ "REV", 0, 8 },
41422 	{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x31248, 0 },
41423 	{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3124c, 0 },
41424 	{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x31250, 0 },
41428 		{ "SGMII_ENA", 0, 1 },
41429 	{ "MAC_PORT_MTIP_SGMII_DECODE_ERROR", 0x31254, 0 },
41430 	{ "MAC_PORT_MTIP_KR_PCS_CONTROL_1", 0x31300, 0 },
41437 	{ "MAC_PORT_MTIP_KR_PCS_STATUS_1", 0x31304, 0 },
41445 	{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1", 0x31308, 0 },
41446 	{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2", 0x3130c, 0 },
41447 	{ "MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY", 0x31310, 0 },
41448 	{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO", 0x31314, 0 },
41455 		{ "Clause_22_Reg_Present", 0, 1 },
41456 	{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI", 0x31318, 0 },
41463 		{ "Clause_22_Reg_Present", 0, 1 },
41464 	{ "MAC_PORT_MTIP_KR_PCS_CONTROL_2", 0x3131c, 0 },
41465 	{ "MAC_PORT_MTIP_KR_PCS_STATUS_2", 0x31320, 0 },
41471 		{ "10GBASE_R_Capable", 0, 1 },
41472 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO", 0x31338, 0 },
41473 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI", 0x3133c, 0 },
41474 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1", 0x31380, 0 },
41479 		{ "10GBASE_R_PCS_Block_Lock", 0, 1 },
41480 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2", 0x31384, 0 },
41484 		{ "ErrBlkCnt", 0, 8 },
41485 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0", 0x31388, 0 },
41486 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1", 0x3138c, 0 },
41487 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2", 0x31390, 0 },
41488 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3", 0x31394, 0 },
41489 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0", 0x31398, 0 },
41490 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1", 0x3139c, 0 },
41491 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2", 0x313a0, 0 },
41492 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3", 0x313a4, 0 },
41493 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL", 0x313a8, 0 },
41500 		{ "Data_Pattern_Select", 0, 1 },
41501 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER", 0x313ac, 0 },
41502 	{ "MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS", 0x313b4, 0 },
41504 		{ "Receive_FIFO_Fault", 0, 1 },
41505 	{ "MAC_PORT_MTIP_KR4_CONTROL_1", 0x31400, 0 },
41512 	{ "MAC_PORT_MTIP_KR4_STATUS_1", 0x31404, 0 },
41516 	{ "MAC_PORT_MTIP_KR4_DEVICE_ID0", 0x31408, 0 },
41517 	{ "MAC_PORT_MTIP_KR4_DEVICE_ID1", 0x3140c, 0 },
41519 	{ "MAC_PORT_MTIP_KR4_SPEED_ABILITY", 0x31410, 0 },
41523 		{ "10G_capable", 0, 1 },
41524 	{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1", 0x31414, 0 },
41531 		{ "Clause_22_reg", 0, 1 },
41532 	{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2", 0x31418, 0 },
41536 	{ "MAC_PORT_MTIP_KR4_CONTROL_2", 0x3141c, 0 },
41537 	{ "MAC_PORT_MTIP_KR4_STATUS_2", 0x31420, 0 },
41546 		{ "10GBase_R_capable", 0, 1 },
41547 	{ "MAC_PORT_MTIP_KR4_PKG_ID0", 0x31438, 0 },
41548 	{ "MAC_PORT_MTIP_KR4_PKG_ID1", 0x3143c, 0 },
41549 	{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_1", 0x31480, 0 },
41552 		{ "Block_lock", 0, 1 },
41553 	{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_2", 0x31484, 0 },
41557 		{ "Err_bl_cnt", 0, 8 },
41558 	{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL", 0x314a8, 0 },
41561 	{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT", 0x314ac, 0 },
41562 	{ "MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT", 0x314b0, 0 },
41563 	{ "MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT", 0x314b4, 0 },
41565 		{ "ERR_BLK_CNTR", 0, 14 },
41566 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1", 0x314c8, 0 },
41571 		{ "LANE_0_BLK_LCK", 0, 1 },
41572 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2", 0x314cc, 0 },
41573 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3", 0x314d0, 0 },
41577 		{ "LANE_0_ALIGN_MRKR_LCK", 0, 1 },
41578 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4", 0x314d4, 0 },
41579 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0", 0x31720, 0 },
41580 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1", 0x31724, 0 },
41581 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2", 0x31728, 0 },
41582 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3", 0x3172c, 0 },
41583 	{ "MAC_PORT_MTIP_KR4_LANE_0_MAPPING", 0x31a40, 0 },
41584 	{ "MAC_PORT_MTIP_KR4_LANE_1_MAPPING", 0x31a44, 0 },
41585 	{ "MAC_PORT_MTIP_KR4_LANE_2_MAPPING", 0x31a48, 0 },
41586 	{ "MAC_PORT_MTIP_KR4_LANE_3_MAPPING", 0x31a4c, 0 },
41587 	{ "MAC_PORT_MTIP_KR4_SCRATCH", 0x31af0, 0 },
41588 	{ "MAC_PORT_MTIP_KR4_CORE_REVISION", 0x31af4, 0 },
41589 	{ "MAC_PORT_MTIP_KR4_VL_INTVL", 0x31af8, 0 },
41590 	{ "MAC_PORT_MTIP_KR4_TX_LANE_THRESH", 0x31afc, 0 },
41591 	{ "MAC_PORT_MTIP_CR4_CONTROL_1", 0x31b00, 0 },
41598 	{ "MAC_PORT_MTIP_CR4_STATUS_1", 0x31b04, 0 },
41602 	{ "MAC_PORT_MTIP_CR4_DEVICE_ID0", 0x31b08, 0 },
41603 	{ "MAC_PORT_MTIP_CR4_DEVICE_ID1", 0x31b0c, 0 },
41604 	{ "MAC_PORT_MTIP_CR4_SPEED_ABILITY", 0x31b10, 0 },
41608 		{ "10G_capable", 0, 1 },
41609 	{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1", 0x31b14, 0 },
41616 		{ "Clause22reg_present", 0, 1 },
41617 	{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2", 0x31b18, 0 },
41621 	{ "MAC_PORT_MTIP_CR4_CONTROL_2", 0x31b1c, 0 },
41622 	{ "MAC_PORT_MTIP_CR4_STATUS_2", 0x31b20, 0 },
41631 		{ "10GBase_R_capable", 0, 1 },
41632 	{ "MAC_PORT_MTIP_CR4_PKG_ID0", 0x31b38, 0 },
41633 	{ "MAC_PORT_MTIP_CR4_PKG_ID1", 0x31b3c, 0 },
41634 	{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_1", 0x31b80, 0 },
41637 		{ "Block_Lock", 0, 1 },
41638 	{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_2", 0x31b84, 0 },
41642 		{ "Errored_blocks_cntr", 0, 8 },
41643 	{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL", 0x31ba8, 0 },
41645 	{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT", 0x31bac, 0 },
41646 	{ "MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT", 0x31bb0, 0 },
41647 	{ "MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT", 0x31bb4, 0 },
41649 		{ "ERR_BLKS_CNTR", 0, 14 },
41650 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1", 0x31bc8, 0 },
41659 		{ "Lane_0_blck_lck", 0, 1 },
41660 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2", 0x31bcc, 0 },
41672 		{ "Lane_8_blck_lck", 0, 1 },
41673 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3", 0x31bd0, 0 },
41681 		{ "Lane0_algn_mrkr_lck", 0, 1 },
41682 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4", 0x31bd4, 0 },
41694 		{ "Lane8_algn_mrkr_lck", 0, 1 },
41695 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0", 0x31e20, 0 },
41696 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1", 0x31e24, 0 },
41697 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2", 0x31e28, 0 },
41698 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3", 0x31e2c, 0 },
41699 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4", 0x31e30, 0 },
41700 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5", 0x31e34, 0 },
41701 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6", 0x31e38, 0 },
41702 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7", 0x31e3c, 0 },
41703 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8", 0x31e40, 0 },
41704 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9", 0x31e44, 0 },
41705 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10", 0x31e48, 0 },
41706 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11", 0x31e4c, 0 },
41707 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12", 0x31e50, 0 },
41708 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13", 0x31e54, 0 },
41709 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14", 0x31e58, 0 },
41710 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15", 0x31e5c, 0 },
41711 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16", 0x31e60, 0 },
41712 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17", 0x31e64, 0 },
41713 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18", 0x31e68, 0 },
41714 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19", 0x31e6c, 0 },
41715 	{ "MAC_PORT_MTIP_CR4_LANE_0_MAPPING", 0x32140, 0 },
41716 	{ "MAC_PORT_MTIP_CR4_LANE_1_MAPPING", 0x32144, 0 },
41717 	{ "MAC_PORT_MTIP_CR4_LANE_2_MAPPING", 0x32148, 0 },
41718 	{ "MAC_PORT_MTIP_CR4_LANE_3_MAPPING", 0x3214c, 0 },
41719 	{ "MAC_PORT_MTIP_CR4_LANE_4_MAPPING", 0x32150, 0 },
41720 	{ "MAC_PORT_MTIP_CR4_LANE_5_MAPPING", 0x32154, 0 },
41721 	{ "MAC_PORT_MTIP_CR4_LANE_6_MAPPING", 0x32158, 0 },
41722 	{ "MAC_PORT_MTIP_CR4_LANE_7_MAPPING", 0x3215c, 0 },
41723 	{ "MAC_PORT_MTIP_CR4_LANE_8_MAPPING", 0x32160, 0 },
41724 	{ "MAC_PORT_MTIP_CR4_LANE_9_MAPPING", 0x32164, 0 },
41725 	{ "MAC_PORT_MTIP_CR4_LANE_10_MAPPING", 0x32168, 0 },
41726 	{ "MAC_PORT_MTIP_CR4_LANE_11_MAPPING", 0x3216c, 0 },
41727 	{ "MAC_PORT_MTIP_CR4_LANE_12_MAPPING", 0x32170, 0 },
41728 	{ "MAC_PORT_MTIP_CR4_LANE_13_MAPPING", 0x32174, 0 },
41729 	{ "MAC_PORT_MTIP_CR4_LANE_14_MAPPING", 0x32178, 0 },
41730 	{ "MAC_PORT_MTIP_CR4_LANE_15_MAPPING", 0x3217c, 0 },
41731 	{ "MAC_PORT_MTIP_CR4_LANE_16_MAPPING", 0x32180, 0 },
41732 	{ "MAC_PORT_MTIP_CR4_LANE_17_MAPPING", 0x32184, 0 },
41733 	{ "MAC_PORT_MTIP_CR4_LANE_18_MAPPING", 0x32188, 0 },
41734 	{ "MAC_PORT_MTIP_CR4_LANE_19_MAPPING", 0x3218c, 0 },
41735 	{ "MAC_PORT_MTIP_CR4_SCRATCH", 0x321f0, 0 },
41736 	{ "MAC_PORT_MTIP_CR4_CORE_REVISION", 0x321f4, 0 },
41737 	{ "MAC_PORT_MTIP_RS_FEC_CONTROL", 0x32200, 0 },
41739 		{ "RS_FEC_Bypass_Correction", 0, 1 },
41740 	{ "MAC_PORT_MTIP_RS_FEC_STATUS", 0x32204, 0 },
41745 		{ "RS_FEC_bypass_correction_ability", 0, 1 },
41746 	{ "MAC_PORT_MTIP_RS_FEC_CCW_LO", 0x32208, 0 },
41747 	{ "MAC_PORT_MTIP_RS_FEC_CCW_HI", 0x3220c, 0 },
41748 	{ "MAC_PORT_MTIP_RS_FEC_NCCW_LO", 0x32210, 0 },
41749 	{ "MAC_PORT_MTIP_RS_FEC_NCCW_HI", 0x32214, 0 },
41750 	{ "MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI", 0x32218, 0 },
41751 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO", 0x32228, 0 },
41752 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI", 0x3222c, 0 },
41753 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO", 0x32230, 0 },
41754 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI", 0x32234, 0 },
41755 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO", 0x32238, 0 },
41756 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI", 0x3223c, 0 },
41757 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO", 0x32240, 0 },
41758 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI", 0x32244, 0 },
41759 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL", 0x32400, 0 },
41762 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1", 0x32404, 0 },
41771 		{ "amps_lock", 0, 4 },
41772 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2", 0x32408, 0 },
41773 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION", 0x3240c, 0 },
41774 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY", 0x32410, 0 },
41775 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS", 0x32414, 0 },
41776 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN", 0x32418, 0 },
41777 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER", 0x3241c, 0 },
41778 	{ "MAC_PORT_MTIP_FEC_ABILITY", 0x32618, 0 },
41780 		{ "BASE_R_FEC_Ability", 0, 1 },
41781 	{ "MAC_PORT_FEC_CONTROL", 0x3261c, 0 },
41783 		{ "fec_en", 0, 1 },
41784 	{ "MAC_PORT_FEC_STATUS", 0x32620, 0 },
41786 		{ "FEC_LOCKED", 0, 1 },
41787 	{ "MAC_PORT_MTIP_FEC0_CERR_CNT_0", 0x32624, 0 },
41788 	{ "MAC_PORT_MTIP_FEC0_CERR_CNT_1", 0x32628, 0 },
41789 	{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_0", 0x3262c, 0 },
41790 	{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_1", 0x32630, 0 },
41791 	{ "MAC_PORT_MTIP_FEC_STATUS1", 0x32664, 0 },
41793 		{ "FEC_LOCKED", 0, 1 },
41794 	{ "MAC_PORT_MTIP_FEC1_CERR_CNT_0", 0x32668, 0 },
41795 	{ "MAC_PORT_MTIP_FEC1_CERR_CNT_1", 0x3266c, 0 },
41796 	{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_0", 0x32670, 0 },
41797 	{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_1", 0x32674, 0 },
41798 	{ "MAC_PORT_MTIP_FEC_STATUS2", 0x326a8, 0 },
41800 		{ "FEC_LOCKED", 0, 1 },
41801 	{ "MAC_PORT_MTIP_FEC2_CERR_CNT_0", 0x326ac, 0 },
41802 	{ "MAC_PORT_MTIP_FEC2_CERR_CNT_1", 0x326b0, 0 },
41803 	{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_0", 0x326b4, 0 },
41804 	{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_1", 0x326b8, 0 },
41805 	{ "MAC_PORT_MTIP_FEC_STATUS3", 0x326ec, 0 },
41807 		{ "FEC_LOCKED", 0, 1 },
41808 	{ "MAC_PORT_MTIP_FEC3_CERR_CNT_0", 0x326f0, 0 },
41809 	{ "MAC_PORT_MTIP_FEC3_CERR_CNT_1", 0x326f4, 0 },
41810 	{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_0", 0x326f8, 0 },
41811 	{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_1", 0x326fc, 0 },
41812 	{ "MAC_PORT_BEAN_CTL", 0x32c00, 0 },
41817 	{ "MAC_PORT_BEAN_STATUS", 0x32c04, 0 },
41825 		{ "LP_BEAN_ABILITY", 0, 1 },
41826 	{ "MAC_PORT_BEAN_ABILITY_0", 0x32c08, 0 },
41832 		{ "SELECTOR", 0, 5 },
41833 	{ "MAC_PORT_BEAN_ABILITY_1", 0x32c0c, 0 },
41835 		{ "TX_NONCE", 0, 5 },
41836 	{ "MAC_PORT_BEAN_ABILITY_2", 0x32c10, 0 },
41838 		{ "TECH_ABILITY_2", 0, 14 },
41839 	{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x32c14, 0 },
41845 		{ "SELECTOR", 0, 5 },
41846 	{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x32c18, 0 },
41848 		{ "TX_NONCE", 0, 5 },
41849 	{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x32c1c, 0 },
41851 		{ "TECH_ABILITY_2", 0, 14 },
41852 	{ "MAC_PORT_BEAN_MS_COUNT", 0x32c20, 0 },
41853 	{ "MAC_PORT_BEAN_XNP_0", 0x32c24, 0 },
41859 		{ "MU", 0, 11 },
41860 	{ "MAC_PORT_BEAN_XNP_1", 0x32c28, 0 },
41861 	{ "MAC_PORT_BEAN_XNP_2", 0x32c2c, 0 },
41862 	{ "MAC_PORT_LP_BEAN_XNP_0", 0x32c30, 0 },
41868 		{ "MU", 0, 11 },
41869 	{ "MAC_PORT_LP_BEAN_XNP_1", 0x32c34, 0 },
41870 	{ "MAC_PORT_LP_BEAN_XNP_2", 0x32c38, 0 },
41871 	{ "MAC_PORT_BEAN_ETH_STATUS", 0x32c3c, 0 },
41882 	{ "MAC_PORT_AE_RX_COEF_REQ", 0x32a00, 0 },
41888 		{ "T5_RXREQ_C0", 0, 2 },
41889 	{ "MAC_PORT_AE_RX_COEF_STAT", 0x32a04, 0 },
41897 		{ "T5_AE0_RXSTAT_C0", 0, 2 },
41898 	{ "MAC_PORT_AE_TX_COEF_REQ", 0x32a08, 0 },
41905 		{ "T5_TXREQ_C0", 0, 2 },
41906 	{ "MAC_PORT_AE_TX_COEF_STAT", 0x32a0c, 0 },
41911 		{ "T5_TXSTAT_C0", 0, 2 },
41912 	{ "MAC_PORT_AE_REG_MODE", 0x32a10, 0 },
41925 		{ "STICKY_MODE", 0, 1 },
41926 	{ "MAC_PORT_AE_PRBS_CTL", 0x32a14, 0 },
41933 		{ "PRBS_GEN_OFF", 0, 1 },
41934 	{ "MAC_PORT_AE_FSM_CTL", 0x32a18, 0 },
41946 		{ "FSM_TR_EN", 0, 1 },
41947 	{ "MAC_PORT_AE_FSM_STATE", 0x32a1c, 0 },
41952 		{ "TFSM_STATE", 0, 3 },
41953 	{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x32a20, 0 },
41959 		{ "T5_RXREQ_C0", 0, 2 },
41960 	{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x32a24, 0 },
41968 		{ "T5_AE1_RXSTAT_C0", 0, 2 },
41969 	{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x32a28, 0 },
41976 		{ "T5_TXREQ_C0", 0, 2 },
41977 	{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x32a2c, 0 },
41982 		{ "T5_TXSTAT_C0", 0, 2 },
41983 	{ "MAC_PORT_AE_REG_MODE_1", 0x32a30, 0 },
41996 		{ "STICKY_MODE", 0, 1 },
41997 	{ "MAC_PORT_AE_PRBS_CTL_1", 0x32a34, 0 },
42004 		{ "PRBS_GEN_OFF", 0, 1 },
42005 	{ "MAC_PORT_AE_FSM_CTL_1", 0x32a38, 0 },
42017 		{ "FSM_TR_EN", 0, 1 },
42018 	{ "MAC_PORT_AE_FSM_STATE_1", 0x32a3c, 0 },
42023 		{ "TFSM_STATE", 0, 3 },
42024 	{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x32a40, 0 },
42030 		{ "T5_RXREQ_C0", 0, 2 },
42031 	{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x32a44, 0 },
42039 		{ "T5_AE2_RXSTAT_C0", 0, 2 },
42040 	{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x32a48, 0 },
42047 		{ "T5_TXREQ_C0", 0, 2 },
42048 	{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x32a4c, 0 },
42053 		{ "T5_TXSTAT_C0", 0, 2 },
42054 	{ "MAC_PORT_AE_REG_MODE_2", 0x32a50, 0 },
42067 		{ "STICKY_MODE", 0, 1 },
42068 	{ "MAC_PORT_AE_PRBS_CTL_2", 0x32a54, 0 },
42075 		{ "PRBS_GEN_OFF", 0, 1 },
42076 	{ "MAC_PORT_AE_FSM_CTL_2", 0x32a58, 0 },
42088 		{ "FSM_TR_EN", 0, 1 },
42089 	{ "MAC_PORT_AE_FSM_STATE_2", 0x32a5c, 0 },
42094 		{ "TFSM_STATE", 0, 3 },
42095 	{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x32a60, 0 },
42101 		{ "T5_RXREQ_C0", 0, 2 },
42102 	{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x32a64, 0 },
42110 		{ "T5_AE3_RXSTAT_C0", 0, 2 },
42111 	{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x32a68, 0 },
42118 		{ "T5_TXREQ_C0", 0, 2 },
42119 	{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x32a6c, 0 },
42124 		{ "T5_TXSTAT_C0", 0, 2 },
42125 	{ "MAC_PORT_AE_REG_MODE_3", 0x32a70, 0 },
42138 		{ "STICKY_MODE", 0, 1 },
42139 	{ "MAC_PORT_AE_PRBS_CTL_3", 0x32a74, 0 },
42146 		{ "PRBS_GEN_OFF", 0, 1 },
42147 	{ "MAC_PORT_AE_FSM_CTL_3", 0x32a78, 0 },
42159 		{ "FSM_TR_EN", 0, 1 },
42160 	{ "MAC_PORT_AE_FSM_STATE_3", 0x32a7c, 0 },
42165 		{ "TFSM_STATE", 0, 3 },
42166 	{ "MAC_PORT_AE_TX_DIS", 0x32a80, 0 },
42167 	{ "MAC_PORT_AE_KR_CTRL", 0x32a84, 0 },
42169 		{ "Restart_Training", 0, 1 },
42170 	{ "MAC_PORT_AE_RX_SIGDET", 0x32a88, 0 },
42171 	{ "MAC_PORT_AE_KR_STATUS", 0x32a8c, 0 },
42175 		{ "RX_Trained", 0, 1 },
42176 	{ "MAC_PORT_AE_TX_DIS_1", 0x32a90, 0 },
42177 	{ "MAC_PORT_AE_KR_CTRL_1", 0x32a94, 0 },
42179 		{ "Restart_Training", 0, 1 },
42180 	{ "MAC_PORT_AE_RX_SIGDET_1", 0x32a98, 0 },
42181 	{ "MAC_PORT_AE_KR_STATUS_1", 0x32a9c, 0 },
42185 		{ "RX_Trained", 0, 1 },
42186 	{ "MAC_PORT_AE_TX_DIS_2", 0x32aa0, 0 },
42187 	{ "MAC_PORT_AE_KR_CTRL_2", 0x32aa4, 0 },
42189 		{ "Restart_Training", 0, 1 },
42190 	{ "MAC_PORT_AE_RX_SIGDET_2", 0x32aa8, 0 },
42191 	{ "MAC_PORT_AE_KR_STATUS_2", 0x32aac, 0 },
42195 		{ "RX_Trained", 0, 1 },
42196 	{ "MAC_PORT_AE_TX_DIS_3", 0x32ab0, 0 },
42197 	{ "MAC_PORT_AE_KR_CTRL_3", 0x32ab4, 0 },
42199 		{ "Restart_Training", 0, 1 },
42200 	{ "MAC_PORT_AE_RX_SIGDET_3", 0x32ab8, 0 },
42201 	{ "MAC_PORT_AE_KR_STATUS_3", 0x32abc, 0 },
42205 		{ "RX_Trained", 0, 1 },
42206 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x32b00, 0 },
42213 		{ "H1TEQ_GOAL", 0, 3 },
42214 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x32b04, 0 },
42222 		{ "AMIN_TH", 0, 4 },
42223 	{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x32b08, 0 },
42226 		{ "TOG_LIM", 0, 4 },
42227 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x32b0c, 0 },
42233 	{ "MAC_PORT_AET_STATUS_0", 0x32b10, 0 },
42236 		{ "CTRL_STATE", 0, 4 },
42237 	{ "MAC_PORT_AET_STATUS_20", 0x32b14, 0 },
42238 	{ "MAC_PORT_AET_LIMITS0", 0x32b18, 0 },
42239 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x32b20, 0 },
42246 		{ "H1TEQ_GOAL", 0, 3 },
42247 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x32b24, 0 },
42255 		{ "AMIN_TH", 0, 4 },
42256 	{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x32b28, 0 },
42259 		{ "TOG_LIM", 0, 4 },
42260 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x32b2c, 0 },
42266 	{ "MAC_PORT_AET_STATUS_1", 0x32b30, 0 },
42269 		{ "CTRL_STATE", 0, 4 },
42270 	{ "MAC_PORT_AET_STATUS_21", 0x32b34, 0 },
42271 	{ "MAC_PORT_AET_LIMITS1", 0x32b38, 0 },
42272 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x32b40, 0 },
42279 		{ "H1TEQ_GOAL", 0, 3 },
42280 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x32b44, 0 },
42288 		{ "AMIN_TH", 0, 4 },
42289 	{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x32b48, 0 },
42292 		{ "TOG_LIM", 0, 4 },
42293 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x32b4c, 0 },
42299 	{ "MAC_PORT_AET_STATUS_2", 0x32b50, 0 },
42302 		{ "CTRL_STATE", 0, 4 },
42303 	{ "MAC_PORT_AET_STATUS_22", 0x32b54, 0 },
42304 	{ "MAC_PORT_AET_LIMITS2", 0x32b58, 0 },
42305 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x32b60, 0 },
42312 		{ "H1TEQ_GOAL", 0, 3 },
42313 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x32b64, 0 },
42321 		{ "AMIN_TH", 0, 4 },
42322 	{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x32b68, 0 },
42325 		{ "TOG_LIM", 0, 4 },
42326 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x32b6c, 0 },
42332 	{ "MAC_PORT_AET_STATUS_3", 0x32b70, 0 },
42335 		{ "CTRL_STATE", 0, 4 },
42336 	{ "MAC_PORT_AET_STATUS_23", 0x32b74, 0 },
42337 	{ "MAC_PORT_AET_LIMITS3", 0x32b78, 0 },
42338 	{ "MAC_PORT_ANALOG_TEST_MUX", 0x33814, 0 },
42339 	{ "MAC_PORT_PLLREFSEL_CONTROL", 0x33854, 0 },
42340 	{ "MAC_PORT_REFISINK_CONTROL", 0x33858, 0 },
42341 	{ "MAC_PORT_REFISRC_CONTROL", 0x3385c, 0 },
42342 	{ "MAC_PORT_REFVREG_CONTROL", 0x33860, 0 },
42343 	{ "MAC_PORT_VBGENDOC_CONTROL", 0x33864, 0 },
42345 		{ "VBGENDOC", 0, 2 },
42346 	{ "MAC_PORT_VREFTUNE_CONTROL", 0x33868, 0 },
42347 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL", 0x33880, 0 },
42351 		{ "RCAL_RESET", 0, 1 },
42352 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1", 0x33884, 0 },
42356 		{ "RCALCOMP", 0, 1 },
42357 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2", 0x33888, 0 },
42358 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3", 0x3388c, 0 },
42359 	{ "MAC_PORT_INEQUALITY_CONTROL_AND_RESULT", 0x338c0, 0 },
42365 		{ "INEQ", 0, 1 },
42366 	{ "MAC_PORT_INEQUALITY_LOW_LIMIT", 0x338c4, 0 },
42367 	{ "MAC_PORT_INEQUALITY_LOW_LIMIT_MASK", 0x338c8, 0 },
42368 	{ "MAC_PORT_INEQUALITY_HIGH_LIMIT", 0x338cc, 0 },
42369 	{ "MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK", 0x338d0, 0 },
42370 	{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x338e8, 0 },
42374 		{ "HSSACJAC", 0, 1 },
42375 	{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x338ec, 0 },
42382 		{ "MACROTEST", 0, 1 },
42383 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x33b00, 0 },
42384 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x33b04, 0 },
42388 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x33b08, 0 },
42389 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x33b0c, 0 },
42393 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x33b10, 0 },
42396 		{ "CCLD", 0, 1 },
42397 	{ "MAC_PORT_PLLA_POWER_CONTROL", 0x33b24, 0 },
42399 		{ "NPWRENA", 0, 1 },
42400 	{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x33b28, 0 },
42401 	{ "MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL", 0x33b38, 0 },
42402 	{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x33b3c, 0 },
42404 		{ "PCKSEL", 0, 3 },
42405 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x33b40, 0 },
42408 		{ "EMIS", 0, 1 },
42409 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x33b44, 0 },
42410 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x33b48, 0 },
42411 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x33b4c, 0 },
42412 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x33b50, 0 },
42413 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x33bf0, 0 },
42415 		{ "REFDIV", 0, 4 },
42416 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x33bf4, 0 },
42422 		{ "DIVSEL8", 0, 1 },
42423 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x33bf8, 0 },
42424 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x33bfc, 0 },
42425 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x33c00, 0 },
42426 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x33c04, 0 },
42430 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x33c08, 0 },
42431 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x33c0c, 0 },
42435 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x33c10, 0 },
42438 		{ "CCLD", 0, 1 },
42439 	{ "MAC_PORT_PLLB_POWER_CONTROL", 0x33c24, 0 },
42441 		{ "NPWRENA", 0, 1 },
42442 	{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x33c28, 0 },
42443 	{ "MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL", 0x33c38, 0 },
42444 	{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x33c3c, 0 },
42446 		{ "PCKSEL", 0, 3 },
42447 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x33c40, 0 },
42450 		{ "EMIS", 0, 1 },
42451 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x33c44, 0 },
42452 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x33c48, 0 },
42453 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x33c4c, 0 },
42454 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x33c50, 0 },
42455 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x33cf0, 0 },
42457 		{ "REFDIV", 0, 4 },
42458 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x33cf4, 0 },
42464 		{ "DIVSEL8", 0, 1 },
42465 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x33cf8, 0 },
42466 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x33cfc, 0 },
42467 	{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x33000, 0 },
42479 		{ "T5_TX_RTSEL", 0, 2 },
42480 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x33004, 0 },
42488 		{ "TPSEL", 0, 3 },
42489 	{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x33008, 0 },
42497 		{ "ALOAD", 0, 1 },
42498 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3300c, 0 },
42501 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33010, 0 },
42503 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33014, 0 },
42508 	{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33018, 0 },
42510 		{ "CALSSTP", 0, 6 },
42511 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3301c, 0 },
42513 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x33020, 0 },
42514 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x33024, 0 },
42515 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x33028, 0 },
42516 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT", 0x3302c, 0 },
42517 	{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x33034, 0 },
42518 	{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33038, 0 },
42525 		{ "C1UPDT", 0, 2 },
42526 	{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3303c, 0 },
42530 		{ "C1STAT", 0, 2 },
42531 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33040, 0 },
42532 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33044, 0 },
42533 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33048, 0 },
42534 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3304c, 0 },
42535 	{ "MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33050, 0 },
42537 		{ "ATUNEP", 0, 8 },
42538 	{ "MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33058, 0 },
42540 	{ "MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED", 0x33060, 0 },
42548 		{ "AS4X0", 0, 2 },
42549 	{ "MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED", 0x33064, 0 },
42553 		{ "AS2X0", 0, 2 },
42554 	{ "MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED", 0x33068, 0 },
42562 		{ "AS1X0", 0, 2 },
42563 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3306c, 0 },
42564 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33070, 0 },
42566 		{ "AT4X", 0, 8 },
42567 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33074, 0 },
42568 	{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33078, 0 },
42569 	{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3307c, 0 },
42571 		{ "XWR", 0, 1 },
42572 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33080, 0 },
42573 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33084, 0 },
42574 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33088, 0 },
42575 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3308c, 0 },
42576 	{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3309c, 0 },
42577 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x330a0, 0 },
42583 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x330a4, 0 },
42589 		{ "DCCOEN", 0, 1 },
42590 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x330a8, 0 },
42592 		{ "DCCAAMP", 0, 7 },
42593 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x330ac, 0 },
42594 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE", 0x330c0, 0 },
42595 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x330c8, 0 },
42603 		{ "OS4X0", 0, 2 },
42604 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x330cc, 0 },
42608 		{ "OS2X0", 0, 2 },
42609 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x330d0, 0 },
42617 		{ "OS1X0", 0, 2 },
42618 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x330d8, 0 },
42619 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x330dc, 0 },
42620 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x330e0, 0 },
42621 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5", 0x330ec, 0 },
42629 		{ "DATASIGN", 0, 1 },
42630 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x330f0, 0 },
42631 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x330f4, 0 },
42632 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x330f8, 0 },
42635 		{ "AECMD70", 0, 8 },
42636 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x330fc, 0 },
42644 		{ "OBS", 0, 1 },
42645 	{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x33100, 0 },
42657 		{ "T5_TX_RTSEL", 0, 2 },
42658 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x33104, 0 },
42666 		{ "TPSEL", 0, 3 },
42667 	{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x33108, 0 },
42675 		{ "ALOAD", 0, 1 },
42676 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3310c, 0 },
42679 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33110, 0 },
42681 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33114, 0 },
42686 	{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33118, 0 },
42688 		{ "CALSSTP", 0, 6 },
42689 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3311c, 0 },
42691 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x33120, 0 },
42692 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x33124, 0 },
42693 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x33128, 0 },
42694 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT", 0x3312c, 0 },
42695 	{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x33134, 0 },
42696 	{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33138, 0 },
42703 		{ "C1UPDT", 0, 2 },
42704 	{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3313c, 0 },
42708 		{ "C1STAT", 0, 2 },
42709 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33140, 0 },
42710 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33144, 0 },
42711 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33148, 0 },
42712 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3314c, 0 },
42713 	{ "MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33150, 0 },
42715 		{ "ATUNEP", 0, 8 },
42716 	{ "MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33158, 0 },
42718 	{ "MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED", 0x33160, 0 },
42726 		{ "AS4X0", 0, 2 },
42727 	{ "MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED", 0x33164, 0 },
42731 		{ "AS2X0", 0, 2 },
42732 	{ "MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED", 0x33168, 0 },
42740 		{ "AS1X0", 0, 2 },
42741 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3316c, 0 },
42742 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33170, 0 },
42744 		{ "AT4X", 0, 8 },
42745 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33174, 0 },
42746 	{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33178, 0 },
42747 	{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3317c, 0 },
42749 		{ "XWR", 0, 1 },
42750 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33180, 0 },
42751 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33184, 0 },
42752 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33188, 0 },
42753 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3318c, 0 },
42754 	{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3319c, 0 },
42755 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x331a0, 0 },
42761 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x331a4, 0 },
42767 		{ "DCCOEN", 0, 1 },
42768 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x331a8, 0 },
42770 		{ "DCCAAMP", 0, 7 },
42771 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x331ac, 0 },
42772 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE", 0x331c0, 0 },
42773 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x331c8, 0 },
42781 		{ "OS4X0", 0, 2 },
42782 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x331cc, 0 },
42786 		{ "OS2X0", 0, 2 },
42787 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x331d0, 0 },
42795 		{ "OS1X0", 0, 2 },
42796 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x331d8, 0 },
42797 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x331dc, 0 },
42798 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x331e0, 0 },
42799 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5", 0x331ec, 0 },
42807 		{ "DATASIGN", 0, 1 },
42808 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x331f0, 0 },
42809 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x331f4, 0 },
42810 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x331f8, 0 },
42813 		{ "AECMD70", 0, 8 },
42814 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x331fc, 0 },
42822 		{ "OBS", 0, 1 },
42823 	{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x33400, 0 },
42835 		{ "T5_TX_RTSEL", 0, 2 },
42836 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x33404, 0 },
42844 		{ "TPSEL", 0, 3 },
42845 	{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x33408, 0 },
42853 		{ "ALOAD", 0, 1 },
42854 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3340c, 0 },
42857 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33410, 0 },
42859 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33414, 0 },
42864 	{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33418, 0 },
42866 		{ "CALSSTP", 0, 6 },
42867 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3341c, 0 },
42869 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x33420, 0 },
42870 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x33424, 0 },
42871 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x33428, 0 },
42872 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT", 0x3342c, 0 },
42873 	{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x33434, 0 },
42874 	{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33438, 0 },
42881 		{ "C1UPDT", 0, 2 },
42882 	{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3343c, 0 },
42886 		{ "C1STAT", 0, 2 },
42887 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33440, 0 },
42888 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33444, 0 },
42889 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33448, 0 },
42890 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3344c, 0 },
42891 	{ "MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33450, 0 },
42893 		{ "ATUNEP", 0, 8 },
42894 	{ "MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33458, 0 },
42896 	{ "MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED", 0x33460, 0 },
42904 		{ "AS4X0", 0, 2 },
42905 	{ "MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED", 0x33464, 0 },
42909 		{ "AS2X0", 0, 2 },
42910 	{ "MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED", 0x33468, 0 },
42918 		{ "AS1X0", 0, 2 },
42919 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3346c, 0 },
42920 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33470, 0 },
42922 		{ "AT4X", 0, 8 },
42923 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33474, 0 },
42924 	{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33478, 0 },
42925 	{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3347c, 0 },
42927 		{ "XWR", 0, 1 },
42928 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33480, 0 },
42929 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33484, 0 },
42930 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33488, 0 },
42931 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3348c, 0 },
42932 	{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3349c, 0 },
42933 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x334a0, 0 },
42939 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x334a4, 0 },
42945 		{ "DCCOEN", 0, 1 },
42946 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x334a8, 0 },
42948 		{ "DCCAAMP", 0, 7 },
42949 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x334ac, 0 },
42950 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE", 0x334c0, 0 },
42951 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x334c8, 0 },
42959 		{ "OS4X0", 0, 2 },
42960 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x334cc, 0 },
42964 		{ "OS2X0", 0, 2 },
42965 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x334d0, 0 },
42973 		{ "OS1X0", 0, 2 },
42974 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x334d8, 0 },
42975 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x334dc, 0 },
42976 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x334e0, 0 },
42977 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5", 0x334ec, 0 },
42985 		{ "DATASIGN", 0, 1 },
42986 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x334f0, 0 },
42987 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x334f4, 0 },
42988 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x334f8, 0 },
42991 		{ "AECMD70", 0, 8 },
42992 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x334fc, 0 },
43000 		{ "OBS", 0, 1 },
43001 	{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x33500, 0 },
43013 		{ "T5_TX_RTSEL", 0, 2 },
43014 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x33504, 0 },
43022 		{ "TPSEL", 0, 3 },
43023 	{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x33508, 0 },
43031 		{ "ALOAD", 0, 1 },
43032 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3350c, 0 },
43035 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33510, 0 },
43037 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33514, 0 },
43042 	{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33518, 0 },
43044 		{ "CALSSTP", 0, 6 },
43045 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3351c, 0 },
43047 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x33520, 0 },
43048 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x33524, 0 },
43049 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x33528, 0 },
43050 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT", 0x3352c, 0 },
43051 	{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x33534, 0 },
43052 	{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33538, 0 },
43059 		{ "C1UPDT", 0, 2 },
43060 	{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3353c, 0 },
43064 		{ "C1STAT", 0, 2 },
43065 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33540, 0 },
43066 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33544, 0 },
43067 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33548, 0 },
43068 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3354c, 0 },
43069 	{ "MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33550, 0 },
43071 		{ "ATUNEP", 0, 8 },
43072 	{ "MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33558, 0 },
43074 	{ "MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED", 0x33560, 0 },
43082 		{ "AS4X0", 0, 2 },
43083 	{ "MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED", 0x33564, 0 },
43087 		{ "AS2X0", 0, 2 },
43088 	{ "MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED", 0x33568, 0 },
43096 		{ "AS1X0", 0, 2 },
43097 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3356c, 0 },
43098 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33570, 0 },
43100 		{ "AT4X", 0, 8 },
43101 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33574, 0 },
43102 	{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33578, 0 },
43103 	{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3357c, 0 },
43105 		{ "XWR", 0, 1 },
43106 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33580, 0 },
43107 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33584, 0 },
43108 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33588, 0 },
43109 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3358c, 0 },
43110 	{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3359c, 0 },
43111 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x335a0, 0 },
43117 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x335a4, 0 },
43123 		{ "DCCOEN", 0, 1 },
43124 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x335a8, 0 },
43126 		{ "DCCAAMP", 0, 7 },
43127 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x335ac, 0 },
43128 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE", 0x335c0, 0 },
43129 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x335c8, 0 },
43137 		{ "OS4X0", 0, 2 },
43138 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x335cc, 0 },
43142 		{ "OS2X0", 0, 2 },
43143 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x335d0, 0 },
43151 		{ "OS1X0", 0, 2 },
43152 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x335d8, 0 },
43153 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x335dc, 0 },
43154 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x335e0, 0 },
43155 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5", 0x335ec, 0 },
43163 		{ "DATASIGN", 0, 1 },
43164 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x335f0, 0 },
43165 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x335f4, 0 },
43166 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x335f8, 0 },
43169 		{ "AECMD70", 0, 8 },
43170 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x335fc, 0 },
43178 		{ "OBS", 0, 1 },
43179 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x33900, 0 },
43191 		{ "T5_TX_RTSEL", 0, 2 },
43192 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x33904, 0 },
43200 		{ "TPSEL", 0, 3 },
43201 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x33908, 0 },
43209 		{ "ALOAD", 0, 1 },
43210 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3390c, 0 },
43213 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33910, 0 },
43215 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33914, 0 },
43220 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33918, 0 },
43222 		{ "CALSSTP", 0, 6 },
43223 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3391c, 0 },
43225 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x33920, 0 },
43226 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x33924, 0 },
43227 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x33928, 0 },
43228 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT", 0x3392c, 0 },
43229 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x33934, 0 },
43230 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33938, 0 },
43237 		{ "C1UPDT", 0, 2 },
43238 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3393c, 0 },
43242 		{ "C1STAT", 0, 2 },
43243 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33940, 0 },
43244 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33944, 0 },
43245 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33948, 0 },
43246 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3394c, 0 },
43247 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33950, 0 },
43249 		{ "ATUNEP", 0, 8 },
43250 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33958, 0 },
43252 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED", 0x33960, 0 },
43260 		{ "AS4X0", 0, 2 },
43261 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED", 0x33964, 0 },
43265 		{ "AS2X0", 0, 2 },
43266 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED", 0x33968, 0 },
43274 		{ "AS1X0", 0, 2 },
43275 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3396c, 0 },
43276 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33970, 0 },
43278 		{ "AT4X", 0, 8 },
43279 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33974, 0 },
43280 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33978, 0 },
43281 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3397c, 0 },
43283 		{ "XWR", 0, 1 },
43284 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33980, 0 },
43285 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33984, 0 },
43286 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33988, 0 },
43287 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3398c, 0 },
43288 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3399c, 0 },
43289 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x339a0, 0 },
43295 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x339a4, 0 },
43301 		{ "DCCOEN", 0, 1 },
43302 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x339a8, 0 },
43304 		{ "DCCAAMP", 0, 7 },
43305 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x339ac, 0 },
43306 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE", 0x339c0, 0 },
43307 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x339c8, 0 },
43315 		{ "OS4X0", 0, 2 },
43316 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x339cc, 0 },
43320 		{ "OS2X0", 0, 2 },
43321 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x339d0, 0 },
43329 		{ "OS1X0", 0, 2 },
43330 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x339d8, 0 },
43331 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x339dc, 0 },
43332 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x339e0, 0 },
43333 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5", 0x339ec, 0 },
43341 		{ "DATASIGN", 0, 1 },
43342 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x339f0, 0 },
43343 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x339f4, 0 },
43344 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x339f8, 0 },
43347 		{ "AECMD70", 0, 8 },
43348 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x339fc, 0 },
43356 		{ "OBS", 0, 1 },
43357 	{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x33200, 0 },
43368 		{ "T5_RX_RTSEL", 0, 2 },
43369 	{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x33204, 0 },
43381 		{ "PATSEL", 0, 3 },
43382 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x33208, 0 },
43391 		{ "SSCEN", 0, 1 },
43392 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3320c, 0 },
43399 		{ "PHOFFS", 0, 6 },
43400 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x33210, 0 },
43402 		{ "ROTD", 0, 6 },
43403 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x33214, 0 },
43406 		{ "ROTE", 0, 6 },
43407 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33218, 0 },
43410 		{ "RAOFF", 0, 5 },
43411 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3321c, 0 },
43413 		{ "RDOFF", 0, 5 },
43414 	{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x33220, 0 },
43425 		{ "DFERST", 0, 1 },
43426 	{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x33224, 0 },
43428 		{ "T5BYTE0", 0, 8 },
43429 	{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x33228, 0 },
43436 		{ "T5_RX_ASAMP", 0, 3 },
43437 	{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3322c, 0 },
43441 		{ "VOFFA", 0, 6 },
43442 	{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x33230, 0 },
43450 		{ "T5VGAIN", 0, 7 },
43451 	{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x33234, 0 },
43456 		{ "AMAXT", 0, 7 },
43457 	{ "MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33238, 0 },
43459 		{ "PMOFFTIME", 0, 6 },
43460 	{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1", 0x3323c, 0 },
43463 		{ "IQAMP", 0, 5 },
43464 	{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2", 0x33240, 0 },
43465 	{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33244, 0 },
43472 		{ "DASEL", 0, 3 },
43473 	{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x33248, 0 },
43475 		{ "DACAP", 0, 8 },
43476 	{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN", 0x3324c, 0 },
43478 		{ "DACAM", 0, 8 },
43479 	{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x33250, 0 },
43481 		{ "ADAC1", 0, 8 },
43482 	{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL", 0x33254, 0 },
43488 		{ "FACCPL", 0, 1 },
43489 	{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE", 0x33258, 0 },
43492 		{ "ACCPLBIAS", 0, 8 },
43493 	{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET", 0x3325c, 0 },
43494 	{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33260, 0 },
43496 		{ "H1EX", 0, 6 },
43497 	{ "MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR", 0x33264, 0 },
43500 		{ "UNPKVGA", 0, 2 },
43501 	{ "MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH", 0x33268, 0 },
43510 		{ "CDRANLGSW", 0, 2 },
43511 	{ "MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3326c, 0 },
43513 …{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33270, 0 …
43524 		{ "OAE", 0, 4 },
43525 	{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x33274, 0 },
43530 		{ "ODEC", 0, 4 },
43531 	{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x33278, 0 },
43547 		{ "T5OCCMP", 0, 1 },
43548 	{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3327c, 0 },
43564 		{ "FADAC", 0, 1 },
43565 	{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x33280, 0 },
43581 		{ "FQCC", 0, 1 },
43582 	{ "MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL", 0x33284, 0 },
43587 		{ "LOFCH", 0, 5 },
43588 	{ "MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE", 0x33288, 0 },
43590 		{ "LOFL", 0, 7 },
43591 	{ "MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST", 0x3328c, 0 },
43599 		{ "HSEL", 0, 4 },
43600 	{ "MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST", 0x33290, 0 },
43605 		{ "ACCRD", 0, 8 },
43606 	{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER", 0x33298, 0 },
43614 		{ "LCURR", 0, 5 },
43615 	{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3329c, 0 },
43621 		{ "SDLVL", 0, 5 },
43622 	{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x332a0, 0 },
43631 		{ "RX_LINKANLGSW", 0, 7 },
43632 	{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x332a4, 0 },
43636 		{ "INTDAC", 0, 6 },
43637 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x332a8, 0 },
43641 		{ "MINAMP", 0, 5 },
43642 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x332ac, 0 },
43648 		{ "EMEN", 0, 1 },
43649 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x332b0, 0 },
43655 		{ "EMCEN", 0, 1 },
43656 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x332b4, 0 },
43659 		{ "APDF", 0, 12 },
43660 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x332b8, 0 },
43661 	{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3", 0x332bc, 0 },
43677 		{ "FPRBSOFF", 0, 1 },
43678 	{ "MAC_PORT_RX_LINKA_DFE_TAP_CONTROL", 0x332c0, 0 },
43679 	{ "MAC_PORT_RX_LINKA_DFE_TAP", 0x332c4, 0 },
43680 	{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2", 0x332e4, 0 },
43688 		{ "QCCCMP", 0, 1 },
43689 	{ "MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x332e8, 0 },
43692 		{ "CSVAL", 0, 3 },
43693 	{ "MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL", 0x332ec, 0 },
43702 		{ "DCDAMP", 0, 6 },
43703 	{ "MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL", 0x332f0, 0 },
43709 		{ "DCDAMP", 0, 6 },
43710 	{ "MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL", 0x332f4, 0 },
43718 		{ "QCDAMP", 0, 6 },
43719 	{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x332f8, 0 },
43726 		{ "ACJZNT", 0, 1 },
43727 	{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x332fc, 0 },
43738 		{ "MTHOLD", 0, 1 },
43739 	{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x33300, 0 },
43750 		{ "T5_RX_RTSEL", 0, 2 },
43751 	{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x33304, 0 },
43763 		{ "PATSEL", 0, 3 },
43764 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x33308, 0 },
43773 		{ "SSCEN", 0, 1 },
43774 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3330c, 0 },
43781 		{ "PHOFFS", 0, 6 },
43782 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x33310, 0 },
43784 		{ "ROTD", 0, 6 },
43785 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x33314, 0 },
43788 		{ "ROTE", 0, 6 },
43789 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33318, 0 },
43792 		{ "RAOFF", 0, 5 },
43793 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3331c, 0 },
43795 		{ "RDOFF", 0, 5 },
43796 	{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x33320, 0 },
43807 		{ "DFERST", 0, 1 },
43808 	{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x33324, 0 },
43810 		{ "T5BYTE0", 0, 8 },
43811 	{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x33328, 0 },
43818 		{ "T5_RX_ASAMP", 0, 3 },
43819 	{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3332c, 0 },
43823 		{ "VOFFA", 0, 6 },
43824 	{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x33330, 0 },
43832 		{ "T5VGAIN", 0, 7 },
43833 	{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x33334, 0 },
43838 		{ "AMAXT", 0, 7 },
43839 	{ "MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33338, 0 },
43841 		{ "PMOFFTIME", 0, 6 },
43842 	{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1", 0x3333c, 0 },
43845 		{ "IQAMP", 0, 5 },
43846 	{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2", 0x33340, 0 },
43847 	{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33344, 0 },
43854 		{ "DASEL", 0, 3 },
43855 	{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x33348, 0 },
43857 		{ "DACAP", 0, 8 },
43858 	{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN", 0x3334c, 0 },
43860 		{ "DACAM", 0, 8 },
43861 	{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x33350, 0 },
43863 		{ "ADAC1", 0, 8 },
43864 	{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL", 0x33354, 0 },
43870 		{ "FACCPL", 0, 1 },
43871 	{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE", 0x33358, 0 },
43874 		{ "ACCPLBIAS", 0, 8 },
43875 	{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET", 0x3335c, 0 },
43876 	{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33360, 0 },
43878 		{ "H1EX", 0, 6 },
43879 	{ "MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR", 0x33364, 0 },
43882 		{ "UNPKVGA", 0, 2 },
43883 	{ "MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH", 0x33368, 0 },
43892 		{ "CDRANLGSW", 0, 2 },
43893 	{ "MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3336c, 0 },
43895 …{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33370, 0 …
43906 		{ "OAE", 0, 4 },
43907 	{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x33374, 0 },
43912 		{ "ODEC", 0, 4 },
43913 	{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x33378, 0 },
43929 		{ "T5OCCMP", 0, 1 },
43930 	{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3337c, 0 },
43946 		{ "FADAC", 0, 1 },
43947 	{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x33380, 0 },
43963 		{ "FQCC", 0, 1 },
43964 	{ "MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL", 0x33384, 0 },
43969 		{ "LOFCH", 0, 5 },
43970 	{ "MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE", 0x33388, 0 },
43972 		{ "LOFL", 0, 7 },
43973 	{ "MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST", 0x3338c, 0 },
43981 		{ "HSEL", 0, 4 },
43982 	{ "MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST", 0x33390, 0 },
43987 		{ "ACCRD", 0, 8 },
43988 	{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER", 0x33398, 0 },
43996 		{ "LCURR", 0, 5 },
43997 	{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3339c, 0 },
44003 		{ "SDLVL", 0, 5 },
44004 	{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x333a0, 0 },
44013 		{ "RX_LINKANLGSW", 0, 7 },
44014 	{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x333a4, 0 },
44018 		{ "INTDAC", 0, 6 },
44019 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x333a8, 0 },
44023 		{ "MINAMP", 0, 5 },
44024 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x333ac, 0 },
44030 		{ "EMEN", 0, 1 },
44031 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x333b0, 0 },
44037 		{ "EMCEN", 0, 1 },
44038 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x333b4, 0 },
44041 		{ "APDF", 0, 12 },
44042 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x333b8, 0 },
44043 	{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3", 0x333bc, 0 },
44059 		{ "FPRBSOFF", 0, 1 },
44060 	{ "MAC_PORT_RX_LINKB_DFE_TAP_CONTROL", 0x333c0, 0 },
44061 	{ "MAC_PORT_RX_LINKB_DFE_TAP", 0x333c4, 0 },
44062 	{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2", 0x333e4, 0 },
44070 		{ "QCCCMP", 0, 1 },
44071 	{ "MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x333e8, 0 },
44074 		{ "CSVAL", 0, 3 },
44075 	{ "MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL", 0x333ec, 0 },
44084 		{ "DCDAMP", 0, 6 },
44085 	{ "MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL", 0x333f0, 0 },
44091 		{ "DCDAMP", 0, 6 },
44092 	{ "MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL", 0x333f4, 0 },
44100 		{ "QCDAMP", 0, 6 },
44101 	{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x333f8, 0 },
44108 		{ "ACJZNT", 0, 1 },
44109 	{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x333fc, 0 },
44120 		{ "MTHOLD", 0, 1 },
44121 	{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x33600, 0 },
44132 		{ "T5_RX_RTSEL", 0, 2 },
44133 	{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x33604, 0 },
44145 		{ "PATSEL", 0, 3 },
44146 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x33608, 0 },
44155 		{ "SSCEN", 0, 1 },
44156 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3360c, 0 },
44163 		{ "PHOFFS", 0, 6 },
44164 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x33610, 0 },
44166 		{ "ROTD", 0, 6 },
44167 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x33614, 0 },
44170 		{ "ROTE", 0, 6 },
44171 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33618, 0 },
44174 		{ "RAOFF", 0, 5 },
44175 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3361c, 0 },
44177 		{ "RDOFF", 0, 5 },
44178 	{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x33620, 0 },
44189 		{ "DFERST", 0, 1 },
44190 	{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x33624, 0 },
44192 		{ "T5BYTE0", 0, 8 },
44193 	{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x33628, 0 },
44200 		{ "T5_RX_ASAMP", 0, 3 },
44201 	{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3362c, 0 },
44205 		{ "VOFFA", 0, 6 },
44206 	{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x33630, 0 },
44214 		{ "T5VGAIN", 0, 7 },
44215 	{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x33634, 0 },
44220 		{ "AMAXT", 0, 7 },
44221 	{ "MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33638, 0 },
44223 		{ "PMOFFTIME", 0, 6 },
44224 	{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1", 0x3363c, 0 },
44227 		{ "IQAMP", 0, 5 },
44228 	{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2", 0x33640, 0 },
44229 	{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33644, 0 },
44236 		{ "DASEL", 0, 3 },
44237 	{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x33648, 0 },
44239 		{ "DACAP", 0, 8 },
44240 	{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN", 0x3364c, 0 },
44242 		{ "DACAM", 0, 8 },
44243 	{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x33650, 0 },
44245 		{ "ADAC1", 0, 8 },
44246 	{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL", 0x33654, 0 },
44252 		{ "FACCPL", 0, 1 },
44253 	{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE", 0x33658, 0 },
44256 		{ "ACCPLBIAS", 0, 8 },
44257 	{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET", 0x3365c, 0 },
44258 	{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33660, 0 },
44260 		{ "H1EX", 0, 6 },
44261 	{ "MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR", 0x33664, 0 },
44264 		{ "UNPKVGA", 0, 2 },
44265 	{ "MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH", 0x33668, 0 },
44274 		{ "CDRANLGSW", 0, 2 },
44275 	{ "MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3366c, 0 },
44277 …{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33670, 0 …
44288 		{ "OAE", 0, 4 },
44289 	{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x33674, 0 },
44294 		{ "ODEC", 0, 4 },
44295 	{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x33678, 0 },
44311 		{ "T5OCCMP", 0, 1 },
44312 	{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3367c, 0 },
44328 		{ "FADAC", 0, 1 },
44329 	{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x33680, 0 },
44345 		{ "FQCC", 0, 1 },
44346 	{ "MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL", 0x33684, 0 },
44351 		{ "LOFCH", 0, 5 },
44352 	{ "MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE", 0x33688, 0 },
44354 		{ "LOFL", 0, 7 },
44355 	{ "MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST", 0x3368c, 0 },
44363 		{ "HSEL", 0, 4 },
44364 	{ "MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST", 0x33690, 0 },
44369 		{ "ACCRD", 0, 8 },
44370 	{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER", 0x33698, 0 },
44378 		{ "LCURR", 0, 5 },
44379 	{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3369c, 0 },
44385 		{ "SDLVL", 0, 5 },
44386 	{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x336a0, 0 },
44395 		{ "RX_LINKANLGSW", 0, 7 },
44396 	{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x336a4, 0 },
44400 		{ "INTDAC", 0, 6 },
44401 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x336a8, 0 },
44405 		{ "MINAMP", 0, 5 },
44406 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x336ac, 0 },
44412 		{ "EMEN", 0, 1 },
44413 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x336b0, 0 },
44419 		{ "EMCEN", 0, 1 },
44420 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x336b4, 0 },
44423 		{ "APDF", 0, 12 },
44424 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x336b8, 0 },
44425 	{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3", 0x336bc, 0 },
44441 		{ "FPRBSOFF", 0, 1 },
44442 	{ "MAC_PORT_RX_LINKC_DFE_TAP_CONTROL", 0x336c0, 0 },
44443 	{ "MAC_PORT_RX_LINKC_DFE_TAP", 0x336c4, 0 },
44444 	{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2", 0x336e4, 0 },
44452 		{ "QCCCMP", 0, 1 },
44453 	{ "MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x336e8, 0 },
44456 		{ "CSVAL", 0, 3 },
44457 	{ "MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL", 0x336ec, 0 },
44466 		{ "DCDAMP", 0, 6 },
44467 	{ "MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL", 0x336f0, 0 },
44473 		{ "DCDAMP", 0, 6 },
44474 	{ "MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL", 0x336f4, 0 },
44482 		{ "QCDAMP", 0, 6 },
44483 	{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x336f8, 0 },
44490 		{ "ACJZNT", 0, 1 },
44491 	{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x336fc, 0 },
44502 		{ "MTHOLD", 0, 1 },
44503 	{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x33700, 0 },
44514 		{ "T5_RX_RTSEL", 0, 2 },
44515 	{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x33704, 0 },
44527 		{ "PATSEL", 0, 3 },
44528 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x33708, 0 },
44537 		{ "SSCEN", 0, 1 },
44538 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3370c, 0 },
44545 		{ "PHOFFS", 0, 6 },
44546 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x33710, 0 },
44548 		{ "ROTD", 0, 6 },
44549 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x33714, 0 },
44552 		{ "ROTE", 0, 6 },
44553 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33718, 0 },
44556 		{ "RAOFF", 0, 5 },
44557 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3371c, 0 },
44559 		{ "RDOFF", 0, 5 },
44560 	{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x33720, 0 },
44571 		{ "DFERST", 0, 1 },
44572 	{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x33724, 0 },
44574 		{ "T5BYTE0", 0, 8 },
44575 	{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x33728, 0 },
44582 		{ "T5_RX_ASAMP", 0, 3 },
44583 	{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3372c, 0 },
44587 		{ "VOFFA", 0, 6 },
44588 	{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x33730, 0 },
44596 		{ "T5VGAIN", 0, 7 },
44597 	{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x33734, 0 },
44602 		{ "AMAXT", 0, 7 },
44603 	{ "MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33738, 0 },
44605 		{ "PMOFFTIME", 0, 6 },
44606 	{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1", 0x3373c, 0 },
44609 		{ "IQAMP", 0, 5 },
44610 	{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2", 0x33740, 0 },
44611 	{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33744, 0 },
44618 		{ "DASEL", 0, 3 },
44619 	{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x33748, 0 },
44621 		{ "DACAP", 0, 8 },
44622 	{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN", 0x3374c, 0 },
44624 		{ "DACAM", 0, 8 },
44625 	{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x33750, 0 },
44627 		{ "ADAC1", 0, 8 },
44628 	{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL", 0x33754, 0 },
44634 		{ "FACCPL", 0, 1 },
44635 	{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE", 0x33758, 0 },
44638 		{ "ACCPLBIAS", 0, 8 },
44639 	{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET", 0x3375c, 0 },
44640 	{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33760, 0 },
44642 		{ "H1EX", 0, 6 },
44643 	{ "MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR", 0x33764, 0 },
44646 		{ "UNPKVGA", 0, 2 },
44647 	{ "MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH", 0x33768, 0 },
44656 		{ "CDRANLGSW", 0, 2 },
44657 	{ "MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3376c, 0 },
44659 …{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33770, 0 …
44670 		{ "OAE", 0, 4 },
44671 	{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x33774, 0 },
44676 		{ "ODEC", 0, 4 },
44677 	{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x33778, 0 },
44693 		{ "T5OCCMP", 0, 1 },
44694 	{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3377c, 0 },
44710 		{ "FADAC", 0, 1 },
44711 	{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x33780, 0 },
44727 		{ "FQCC", 0, 1 },
44728 	{ "MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL", 0x33784, 0 },
44733 		{ "LOFCH", 0, 5 },
44734 	{ "MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE", 0x33788, 0 },
44736 		{ "LOFL", 0, 7 },
44737 	{ "MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST", 0x3378c, 0 },
44745 		{ "HSEL", 0, 4 },
44746 	{ "MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST", 0x33790, 0 },
44751 		{ "ACCRD", 0, 8 },
44752 	{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER", 0x33798, 0 },
44760 		{ "LCURR", 0, 5 },
44761 	{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3379c, 0 },
44767 		{ "SDLVL", 0, 5 },
44768 	{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x337a0, 0 },
44777 		{ "RX_LINKANLGSW", 0, 7 },
44778 	{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x337a4, 0 },
44782 		{ "INTDAC", 0, 6 },
44783 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x337a8, 0 },
44787 		{ "MINAMP", 0, 5 },
44788 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x337ac, 0 },
44794 		{ "EMEN", 0, 1 },
44795 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x337b0, 0 },
44801 		{ "EMCEN", 0, 1 },
44802 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x337b4, 0 },
44805 		{ "APDF", 0, 12 },
44806 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x337b8, 0 },
44807 	{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3", 0x337bc, 0 },
44823 		{ "FPRBSOFF", 0, 1 },
44824 	{ "MAC_PORT_RX_LINKD_DFE_TAP_CONTROL", 0x337c0, 0 },
44825 	{ "MAC_PORT_RX_LINKD_DFE_TAP", 0x337c4, 0 },
44826 	{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2", 0x337e4, 0 },
44834 		{ "QCCCMP", 0, 1 },
44835 	{ "MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x337e8, 0 },
44838 		{ "CSVAL", 0, 3 },
44839 	{ "MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL", 0x337ec, 0 },
44848 		{ "DCDAMP", 0, 6 },
44849 	{ "MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL", 0x337f0, 0 },
44855 		{ "DCDAMP", 0, 6 },
44856 	{ "MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL", 0x337f4, 0 },
44864 		{ "QCDAMP", 0, 6 },
44865 	{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x337f8, 0 },
44872 		{ "ACJZNT", 0, 1 },
44873 	{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x337fc, 0 },
44884 		{ "MTHOLD", 0, 1 },
44885 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x33a00, 0 },
44896 		{ "T5_RX_RTSEL", 0, 2 },
44897 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x33a04, 0 },
44909 		{ "PATSEL", 0, 3 },
44910 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x33a08, 0 },
44919 		{ "SSCEN", 0, 1 },
44920 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x33a0c, 0 },
44927 		{ "PHOFFS", 0, 6 },
44928 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x33a10, 0 },
44930 		{ "ROTD", 0, 6 },
44931 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x33a14, 0 },
44934 		{ "ROTE", 0, 6 },
44935 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33a18, 0 },
44938 		{ "RAOFF", 0, 5 },
44939 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x33a1c, 0 },
44941 		{ "RDOFF", 0, 5 },
44942 	{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x33a20, 0 },
44953 		{ "DFERST", 0, 1 },
44954 	{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x33a24, 0 },
44956 		{ "T5BYTE0", 0, 8 },
44957 	{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x33a28, 0 },
44964 		{ "T5_RX_ASAMP", 0, 3 },
44965 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x33a2c, 0 },
44969 		{ "VOFFA", 0, 6 },
44970 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x33a30, 0 },
44978 		{ "T5VGAIN", 0, 7 },
44979 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x33a34, 0 },
44984 		{ "AMAXT", 0, 7 },
44985 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33a38, 0 },
44987 		{ "PMOFFTIME", 0, 6 },
44988 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1", 0x33a3c, 0 },
44991 		{ "IQAMP", 0, 5 },
44992 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2", 0x33a40, 0 },
44993 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33a44, 0 },
45000 		{ "DASEL", 0, 3 },
45001 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x33a48, 0 },
45003 		{ "DACAP", 0, 8 },
45004 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN", 0x33a4c, 0 },
45006 		{ "DACAM", 0, 8 },
45007 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x33a50, 0 },
45009 		{ "ADAC1", 0, 8 },
45010 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL", 0x33a54, 0 },
45016 		{ "FACCPL", 0, 1 },
45017 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE", 0x33a58, 0 },
45020 		{ "ACCPLBIAS", 0, 8 },
45021 	{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET", 0x33a5c, 0 },
45022 	{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33a60, 0 },
45024 		{ "H1EX", 0, 6 },
45025 	{ "MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR", 0x33a64, 0 },
45028 		{ "UNPKVGA", 0, 2 },
45029 	{ "MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH", 0x33a68, 0 },
45038 		{ "CDRANLGSW", 0, 2 },
45039 	{ "MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x33a6c, 0 },
45041 …C_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33a70, 0 },
45052 		{ "OAE", 0, 4 },
45053 	{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x33a74, 0 },
45058 		{ "ODEC", 0, 4 },
45059 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x33a78, 0 },
45075 		{ "T5OCCMP", 0, 1 },
45076 	{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x33a7c, 0 },
45092 		{ "FADAC", 0, 1 },
45093 	{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x33a80, 0 },
45109 		{ "FQCC", 0, 1 },
45110 	{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL", 0x33a84, 0 },
45115 		{ "LOFCH", 0, 5 },
45116 	{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE", 0x33a88, 0 },
45118 		{ "LOFL", 0, 7 },
45119 	{ "MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST", 0x33a8c, 0 },
45127 		{ "HSEL", 0, 4 },
45128 	{ "MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST", 0x33a90, 0 },
45133 		{ "ACCRD", 0, 8 },
45134 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER", 0x33a98, 0 },
45142 		{ "LCURR", 0, 5 },
45143 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x33a9c, 0 },
45149 		{ "SDLVL", 0, 5 },
45150 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x33aa0, 0 },
45159 		{ "RX_LINKANLGSW", 0, 7 },
45160 	{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x33aa4, 0 },
45164 		{ "INTDAC", 0, 6 },
45165 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x33aa8, 0 },
45169 		{ "MINAMP", 0, 5 },
45170 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x33aac, 0 },
45176 		{ "EMEN", 0, 1 },
45177 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x33ab0, 0 },
45183 		{ "EMCEN", 0, 1 },
45184 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x33ab4, 0 },
45187 		{ "APDF", 0, 12 },
45188 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x33ab8, 0 },
45189 	{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3", 0x33abc, 0 },
45205 		{ "FPRBSOFF", 0, 1 },
45206 	{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL", 0x33ac0, 0 },
45207 	{ "MAC_PORT_RX_LINK_BCST_DFE_TAP", 0x33ac4, 0 },
45208 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2", 0x33ae4, 0 },
45216 		{ "QCCCMP", 0, 1 },
45217 	{ "MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x33ae8, 0 },
45220 		{ "CSVAL", 0, 3 },
45221 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL", 0x33aec, 0 },
45230 		{ "DCDAMP", 0, 6 },
45231 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL", 0x33af0, 0 },
45237 		{ "DCDAMP", 0, 6 },
45238 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL", 0x33af4, 0 },
45246 		{ "QCDAMP", 0, 6 },
45247 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x33af8, 0 },
45254 		{ "ACJZNT", 0, 1 },
45255 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x33afc, 0 },
45266 		{ "MTHOLD", 0, 1 },
45267 	{ "MAC_PORT_CFG", 0x34800, 0 },
45292 		{ "Port_Sel", 0, 1 },
45293 	{ "MAC_PORT_RESET_CTRL", 0x34804, 0 },
45325 		{ "HSS_Reset", 0, 1 },
45326 	{ "MAC_PORT_LED_CFG", 0x34808, 0 },
45336 		{ "Led0_Polarity_Inv", 0, 1 },
45337 	{ "MAC_PORT_LED_COUNTHI", 0x3480c, 0 },
45338 	{ "MAC_PORT_LED_COUNTLO", 0x34810, 0 },
45339 	{ "MAC_PORT_CFG3", 0x34814, 0 },
45354 		{ "HSSC16C20SEL", 0, 4 },
45355 	{ "MAC_PORT_CFG2", 0x34818, 0 },
45364 		{ "T5_AEC_PMA_RX_READY", 0, 4 },
45365 	{ "MAC_PORT_PKT_COUNT", 0x3481c, 0 },
45369 		{ "rx_eop_count", 0, 8 },
45370 	{ "MAC_PORT_CFG4", 0x34820, 0 },
45378 		{ "AEC0_TX_WIDTH", 0, 2 },
45379 	{ "MAC_PORT_MAGIC_MACID_LO", 0x34824, 0 },
45380 	{ "MAC_PORT_MAGIC_MACID_HI", 0x34828, 0 },
45381 	{ "MAC_PORT_MTIP_RESET_CTRL", 0x3482c, 0 },
45413 		{ "xgmii_clk_reset", 0, 1 },
45414 	{ "MAC_PORT_MTIP_GATE_CTRL", 0x34830, 0 },
45446 		{ "an_clk_enable", 0, 1 },
45447 	{ "MAC_PORT_LINK_STATUS", 0x34834, 0 },
45455 		{ "linkdn", 0, 1 },
45456 	{ "MAC_PORT_AEC_ADD_CTL_STAT_0", 0x34838, 0 },
45464 		{ "AEC_SYS_LANE_SELECT_O", 0, 2 },
45465 	{ "MAC_PORT_AEC_ADD_CTL_STAT_1", 0x3483c, 0 },
45473 		{ "AEC_RX_LANE_ID_O", 0, 2 },
45474 	{ "MAC_PORT_AEC_XGMII_TIMER_LO_40G", 0x34840, 0 },
45475 	{ "MAC_PORT_AEC_XGMII_TIMER_HI_40G", 0x34844, 0 },
45476 	{ "MAC_PORT_AEC_XGMII_TIMER_LO_100G", 0x34848, 0 },
45477 	{ "MAC_PORT_AEC_XGMII_TIMER_HI_100G", 0x3484c, 0 },
45478 	{ "MAC_PORT_AEC_DEBUG_LO_0", 0x34850, 0 },
45494 		{ "REG_MAN_DEC_REQ", 0, 1 },
45495 	{ "MAC_PORT_AEC_DEBUG_HI_0", 0x34854, 0 },
45500 		{ "LCK_FSM_CUR_STATE", 0, 3 },
45501 	{ "MAC_PORT_AEC_DEBUG_LO_1", 0x34858, 0 },
45517 		{ "REG_MAN_DEC_REQ", 0, 1 },
45518 	{ "MAC_PORT_AEC_DEBUG_HI_1", 0x3485c, 0 },
45523 		{ "LCK_FSM_CUR_STATE", 0, 3 },
45524 	{ "MAC_PORT_AEC_DEBUG_LO_2", 0x34860, 0 },
45540 		{ "REG_MAN_DEC_REQ", 0, 1 },
45541 	{ "MAC_PORT_AEC_DEBUG_HI_2", 0x34864, 0 },
45546 		{ "LCK_FSM_CUR_STATE", 0, 3 },
45547 	{ "MAC_PORT_AEC_DEBUG_LO_3", 0x34868, 0 },
45563 		{ "REG_MAN_DEC_REQ", 0, 1 },
45564 	{ "MAC_PORT_AEC_DEBUG_HI_3", 0x3486c, 0 },
45569 		{ "LCK_FSM_CUR_STATE", 0, 3 },
45570 	{ "MAC_PORT_MAC_DEBUG_RO", 0x34870, 0 },
45583 		{ "mac1g10g_tx_underflow", 0, 1 },
45584 	{ "MAC_PORT_MAC_CTRL_RW", 0x34874, 0 },
45594 		{ "mac1g_loop_bck", 0, 1 },
45595 	{ "MAC_PORT_PCS_DEBUG0_RO", 0x34878, 0 },
45614 		{ "sgmii_sg_speed", 0, 2 },
45615 	{ "MAC_PORT_PCS_CTRL_RW", 0x3487c, 0 },
45626 		{ "sgmii_tx_lane_thresh", 0, 4 },
45627 	{ "MAC_PORT_PCS_DEBUG1_RO", 0x34880, 0 },
45630 		{ "pcs100g_block_lock", 0, 20 },
45631 	{ "MAC_PORT_PERR_INT_EN_100G", 0x34884, 0 },
45661 		{ "Perr_rx0_pcs100g", 0, 1 },
45662 	{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x34888, 0 },
45692 		{ "Perr_rx0_pcs100g", 0, 1 },
45693 	{ "MAC_PORT_PERR_ENABLE_100G", 0x3488c, 0 },
45723 		{ "Perr_rx0_pcs100g", 0, 1 },
45724 	{ "MAC_PORT_MAC_STAT_DEBUG", 0x34890, 0 },
45725 	{ "MAC_PORT_MAC_25G_50G_AM0", 0x34894, 0 },
45726 	{ "MAC_PORT_MAC_25G_50G_AM1", 0x34898, 0 },
45727 	{ "MAC_PORT_MAC_25G_50G_AM2", 0x3489c, 0 },
45728 	{ "MAC_PORT_MAC_25G_50G_AM3", 0x348a0, 0 },
45729 	{ "MAC_PORT_MAC_AN_STATE_STATUS", 0x348a4, 0 },
45730 	{ "MAC_PORT_EPIO_DATA0", 0x348c0, 0 },
45731 	{ "MAC_PORT_EPIO_DATA1", 0x348c4, 0 },
45732 	{ "MAC_PORT_EPIO_DATA2", 0x348c8, 0 },
45733 	{ "MAC_PORT_EPIO_DATA3", 0x348cc, 0 },
45734 	{ "MAC_PORT_EPIO_OP", 0x348d0, 0 },
45737 		{ "Address", 0, 8 },
45738 	{ "MAC_PORT_WOL_STATUS", 0x348d4, 0 },
45743 		{ "MatchedFilter", 0, 3 },
45744 	{ "MAC_PORT_INT_EN", 0x348d8, 0 },
45767 		{ "RxFifo_prty_err", 0, 1 },
45768 	{ "MAC_PORT_INT_CAUSE", 0x348dc, 0 },
45791 		{ "RxFifo_prty_err", 0, 1 },
45792 	{ "MAC_PORT_PERR_INT_EN", 0x348e0, 0 },
45824 		{ "Perr_tx_pcs1g", 0, 1 },
45825 	{ "MAC_PORT_PERR_INT_CAUSE", 0x348e4, 0 },
45857 		{ "Perr_tx_pcs1g", 0, 1 },
45858 	{ "MAC_PORT_PERR_ENABLE", 0x348e8, 0 },
45890 		{ "Perr_tx_pcs1g", 0, 1 },
45891 	{ "MAC_PORT_PERR_INJECT", 0x348ec, 0 },
45893 		{ "InjectDataErr", 0, 1 },
45894 	{ "MAC_PORT_HSS_CFG0", 0x348f0, 0 },
45920 	{ "MAC_PORT_HSS_CFG1", 0x348f4, 0 },
45944 		{ "TXDREFRESH", 0, 1 },
45945 	{ "MAC_PORT_HSS_CFG2", 0x348f8, 0 },
45977 		{ "RXAPHSUPIN", 0, 1 },
45978 	{ "MAC_PORT_HSS_CFG3", 0x348fc, 0 },
45982 		{ "HSSPLLCONFIGA", 0, 8 },
45983 	{ "MAC_PORT_HSS_CFG4", 0x34900, 0 },
45989 		{ "HSSDIVSELB", 0, 9 },
45990 	{ "MAC_PORT_HSS_STATUS", 0x34904, 0 },
46010 		{ "HSSPRTREADYA", 0, 1 },
46011 	{ "MAC_PORT_HSS_EEE_STATUS", 0x34908, 0 },
46027 		{ "TXDREFRESH_STATUS", 0, 1 },
46028 	{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3490c, 0 },
46029 	{ "MAC_PORT_HSS_PL_CTL", 0x34910, 0 },
46032 		{ "IPW", 0, 8 },
46033 	{ "MAC_PORT_RUNT_FRAME", 0x34914, 0 },
46035 		{ "runt", 0, 16 },
46036 	{ "MAC_PORT_EEE_STATUS", 0x34918, 0 },
46044 		{ "pma_tx_quiet", 0, 1 },
46045 	{ "MAC_PORT_CGEN", 0x3491c, 0 },
46054 		{ "sd0_CGEN", 0, 1 },
46055 	{ "MAC_PORT_CGEN_MTIP", 0x34920, 0 },
46067 		{ "PCSSEG0_CGEN", 0, 1 },
46068 	{ "MAC_PORT_TX_TS_ID", 0x34924, 0 },
46069 	{ "MAC_PORT_TX_TS_VAL_LO", 0x34928, 0 },
46070 	{ "MAC_PORT_TX_TS_VAL_HI", 0x3492c, 0 },
46071 	{ "MAC_PORT_EEE_CTL", 0x34930, 0 },
46074 		{ "En", 0, 1 },
46075 	{ "MAC_PORT_EEE_TX_CTL", 0x34934, 0 },
46082 		{ "EEE_TX_RESET", 0, 1 },
46083 	{ "MAC_PORT_EEE_RX_CTL", 0x34938, 0 },
46088 		{ "EEE_RX_RESET", 0, 1 },
46089 	{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3493c, 0 },
46090 	{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x34940, 0 },
46091 	{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x34944, 0 },
46092 	{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x34948, 0 },
46093 	{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3494c, 0 },
46094 	{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x34950, 0 },
46095 	{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x34954, 0 },
46096 	{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x34958, 0 },
46097 	{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3495c, 0 },
46098 	{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x34960, 0 },
46099 	{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x34964, 0 },
46100 	{ "MAC_PORT_EEE_WF_COUNT", 0x34968, 0 },
46102 		{ "wake_cnt", 0, 16 },
46103 	{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3496c, 0 },
46104 	{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x34970, 0 },
46105 	{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x34974, 0 },
46106 	{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x34978, 0 },
46107 	{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3497c, 0 },
46108 	{ "MAC_PORT_PTP_TIMER_WR_HI", 0x34980, 0 },
46109 	{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x34984, 0 },
46110 	{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x34988, 0 },
46111 	{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3498c, 0 },
46112 	{ "MAC_PORT_PTP_SUM_LO", 0x34990, 0 },
46113 	{ "MAC_PORT_PTP_SUM_HI", 0x34994, 0 },
46114 	{ "MAC_PORT_PTP_TIMER_INCR0", 0x34998, 0 },
46116 		{ "X", 0, 16 },
46117 	{ "MAC_PORT_PTP_TIMER_INCR1", 0x3499c, 0 },
46119 		{ "X_TICK", 0, 16 },
46120 	{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x349a0, 0 },
46121 	{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x349a4, 0 },
46123 		{ "A", 0, 16 },
46124 	{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x349a8, 0 },
46125 	{ "MAC_PORT_PTP_CFG", 0x349ac, 0 },
46133 		{ "Q", 0, 8 },
46134 	{ "MAC_PORT_PTP_PPS", 0x349b0, 0 },
46135 	{ "MAC_PORT_PTP_SINGLE_ALARM", 0x349b4, 0 },
46136 	{ "MAC_PORT_PTP_PERIODIC_ALARM", 0x349b8, 0 },
46137 	{ "MAC_PORT_PTP_STATUS", 0x349bc, 0 },
46138 	{ "MAC_PORT_MTIP_REVISION", 0x34a00, 0 },
46141 		{ "REV", 0, 8 },
46142 	{ "MAC_PORT_MTIP_SCRATCH", 0x34a04, 0 },
46143 	{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x34a08, 0 },
46165 		{ "TX_ENA", 0, 1 },
46166 	{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x34a0c, 0 },
46167 	{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x34a10, 0 },
46168 	{ "MAC_PORT_MTIP_FRM_LENGTH", 0x34a14, 0 },
46169 	{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x34a1c, 0 },
46171 		{ "EMPTY", 0, 16 },
46172 	{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x34a20, 0 },
46174 		{ "EMPTY", 0, 16 },
46175 	{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x34a24, 0 },
46177 		{ "AlmstEmpty", 0, 16 },
46178 	{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x34a28, 0 },
46180 		{ "AlmstEmpty", 0, 16 },
46181 	{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x34a2c, 0 },
46183 		{ "ADDR", 0, 6 },
46184 	{ "MAC_PORT_MTIP_MAC_STATUS", 0x34a40, 0 },
46188 		{ "RX_LOC_FAULT", 0, 1 },
46189 	{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x34a44, 0 },
46190 	{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x34a48, 0 },
46191 	{ "MAC_PORT_MTIP_INIT_CREDIT", 0x34a4c, 0 },
46192 	{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x34a50, 0 },
46193 	{ "MAC_PORT_RX_PAUSE_STATUS", 0x34a74, 0 },
46194 	{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x34a7c, 0 },
46195 	{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x34a80, 0 },
46196 	{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x34a84, 0 },
46197 	{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x34a88, 0 },
46198 	{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x34a8c, 0 },
46199 	{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x34a90, 0 },
46200 	{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x34a94, 0 },
46201 	{ "MAC_PORT_AALIGNMENTERRORS", 0x34a98, 0 },
46202 	{ "MAC_PORT_AALIGNMENTERRORSHI", 0x34a9c, 0 },
46203 	{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x34aa0, 0 },
46204 	{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x34aa4, 0 },
46205 	{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x34aa8, 0 },
46206 	{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x34aac, 0 },
46207 	{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x34ab0, 0 },
46208 	{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x34ab4, 0 },
46209 	{ "MAC_PORT_AINRANGELENGTHERRORS", 0x34ab8, 0 },
46210 	{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x34abc, 0 },
46211 	{ "MAC_PORT_VLANTRANSMITTEDOK", 0x34ac0, 0 },
46212 	{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x34ac4, 0 },
46213 	{ "MAC_PORT_VLANRECEIVEDOK", 0x34ac8, 0 },
46214 	{ "MAC_PORT_VLANRECEIVEDOKHI", 0x34acc, 0 },
46215 	{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x34ad0, 0 },
46216 	{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x34ad4, 0 },
46217 	{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x34ad8, 0 },
46218 	{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x34adc, 0 },
46219 	{ "MAC_PORT_IFINUCASTPKTS", 0x34ae0, 0 },
46220 	{ "MAC_PORT_IFINUCASTPKTSHI", 0x34ae4, 0 },
46221 	{ "MAC_PORT_IFINMULTICASTPKTS", 0x34ae8, 0 },
46222 	{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x34aec, 0 },
46223 	{ "MAC_PORT_IFINBROADCASTPKTS", 0x34af0, 0 },
46224 	{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x34af4, 0 },
46225 	{ "MAC_PORT_IFOUTERRORS", 0x34af8, 0 },
46226 	{ "MAC_PORT_IFOUTERRORSHI", 0x34afc, 0 },
46227 	{ "MAC_PORT_IFOUTUCASTPKTS", 0x34b08, 0 },
46228 	{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x34b0c, 0 },
46229 	{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x34b10, 0 },
46230 	{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x34b14, 0 },
46231 	{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x34b18, 0 },
46232 	{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x34b1c, 0 },
46233 	{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x34b20, 0 },
46234 	{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x34b24, 0 },
46235 	{ "MAC_PORT_ETHERSTATSOCTETS", 0x34b28, 0 },
46236 	{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x34b2c, 0 },
46237 	{ "MAC_PORT_ETHERSTATSPKTS", 0x34b30, 0 },
46238 	{ "MAC_PORT_ETHERSTATSPKTSHI", 0x34b34, 0 },
46239 	{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x34b38, 0 },
46240 	{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x34b3c, 0 },
46241 	{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x34b40, 0 },
46242 	{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x34b44, 0 },
46243 	{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x34b48, 0 },
46244 	{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x34b4c, 0 },
46245 	{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x34b50, 0 },
46246 	{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x34b54, 0 },
46247 	{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x34b58, 0 },
46248 	{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x34b5c, 0 },
46249 	{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x34b60, 0 },
46250 	{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34b64, 0 },
46251 	{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x34b68, 0 },
46252 	{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34b6c, 0 },
46253 	{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x34b70, 0 },
46254 	{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x34b74, 0 },
46255 	{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x34b78, 0 },
46256 	{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x34b7c, 0 },
46257 	{ "MAC_PORT_ETHERSTATSJABBERS", 0x34b80, 0 },
46258 	{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x34b84, 0 },
46259 	{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x34b88, 0 },
46260 	{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x34b8c, 0 },
46261 	{ "MAC_PORT_IFINERRORS", 0x34b90, 0 },
46262 	{ "MAC_PORT_IFINERRORSHI", 0x34b94, 0 },
46263 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x34b98, 0 },
46264 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x34b9c, 0 },
46265 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x34ba0, 0 },
46266 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x34ba4, 0 },
46267 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x34ba8, 0 },
46268 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x34bac, 0 },
46269 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x34bb0, 0 },
46270 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x34bb4, 0 },
46271 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x34bb8, 0 },
46272 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x34bbc, 0 },
46273 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x34bc0, 0 },
46274 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x34bc4, 0 },
46275 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x34bc8, 0 },
46276 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x34bcc, 0 },
46277 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x34bd0, 0 },
46278 	{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x34bd4, 0 },
46279 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x34bd8, 0 },
46280 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x34bdc, 0 },
46281 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x34be0, 0 },
46282 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x34be4, 0 },
46283 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x34be8, 0 },
46284 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x34bec, 0 },
46285 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x34bf0, 0 },
46286 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x34bf4, 0 },
46287 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x34bf8, 0 },
46288 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x34bfc, 0 },
46289 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x34c00, 0 },
46290 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x34c04, 0 },
46291 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x34c08, 0 },
46292 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x34c0c, 0 },
46293 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x34c10, 0 },
46294 	{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x34c14, 0 },
46295 	{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x34c18, 0 },
46296 	{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x34c1c, 0 },
46297 	{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x34c20, 0 },
46298 	{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x34c24, 0 },
46299 	{ "MAC_PORT_MTIP_1G10G_REVISION", 0x34d00, 0 },
46302 		{ "REV", 0, 8 },
46303 	{ "MAC_PORT_MTIP_1G10G_SCRATCH", 0x34d04, 0 },
46304 	{ "MAC_PORT_MTIP_1G10G_COMMAND_CONFIG", 0x34d08, 0 },
46329 		{ "TX_ENAMAC", 0, 1 },
46330 	{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_0", 0x34d0c, 0 },
46331 	{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_1", 0x34d10, 0 },
46332 	{ "MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU", 0x34d14, 0 },
46334 		{ "FRM_LEN_SET", 0, 16 },
46335 	{ "MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS", 0x34d1c, 0 },
46337 		{ "AVAIL", 0, 16 },
46338 	{ "MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS", 0x34d20, 0 },
46340 		{ "AVAIL", 0, 16 },
46341 	{ "MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E", 0x34d24, 0 },
46343 		{ "AlmostEmpty", 0, 16 },
46344 	{ "MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E", 0x34d28, 0 },
46346 		{ "AlmostEmpty", 0, 16 },
46347 	{ "MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD", 0x34d2c, 0 },
46348 	{ "MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS", 0x34d30, 0 },
46354 		{ "MDIO_Busy", 0, 1 },
46355 	{ "MAC_PORT_MTIP_1G10G_MDIO_COMMAND", 0x34d34, 0 },
46359 		{ "Device_Reg_Addr", 0, 5 },
46360 	{ "MAC_PORT_MTIP_1G10G_MDIO_DATA", 0x34d38, 0 },
46361 	{ "MAC_PORT_MTIP_1G10G_MDIO_REGADDR", 0x34d3c, 0 },
46362 	{ "MAC_PORT_MTIP_1G10G_STATUS", 0x34d40, 0 },
46370 		{ "RX_LOC_FAULT", 0, 1 },
46371 	{ "MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH", 0x34d44, 0 },
46372 	{ "MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER", 0x34d48, 0 },
46373 	{ "MAC_PORT_MTIP_1G10G_INIT_CREDIT", 0x34d4c, 0 },
46374 	{ "MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA", 0x34d54, 0 },
46376 		{ "CL0_PAUSE_QUANTA", 0, 16 },
46377 	{ "MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA", 0x34d58, 0 },
46379 		{ "CL2_PAUSE_QUANTA", 0, 16 },
46380 	{ "MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA", 0x34d5c, 0 },
46382 		{ "CL4_PAUSE_QUANTA", 0, 16 },
46383 	{ "MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA", 0x34d60, 0 },
46385 		{ "CL6_PAUSE_QUANTA", 0, 16 },
46386 	{ "MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH", 0x34d64, 0 },
46388 		{ "CL0_QUANTA_THRESH", 0, 16 },
46389 	{ "MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH", 0x34d68, 0 },
46391 		{ "CL2_QUANTA_THRESH", 0, 16 },
46392 	{ "MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH", 0x34d6c, 0 },
46394 		{ "CL4_QUANTA_THRESH", 0, 16 },
46395 	{ "MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH", 0x34d70, 0 },
46397 		{ "CL6_QUANTA_THRESH", 0, 16 },
46398 	{ "MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS", 0x34d74, 0 },
46399 	{ "MAC_PORT_MTIP_1G10G_TS_TIMESTAMP", 0x34d7c, 0 },
46400 	{ "MAC_PORT_MTIP_1G10G_STATN_CONFIG", 0x34de0, 0 },
46403 		{ "SATURATE", 0, 1 },
46404 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS", 0x34e00, 0 },
46405 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI", 0x34e04, 0 },
46406 	{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOK", 0x34e08, 0 },
46407 	{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI", 0x34e0c, 0 },
46408 	{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS", 0x34e10, 0 },
46409 	{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI", 0x34e14, 0 },
46410 	{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES", 0x34e18, 0 },
46411 	{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI", 0x34e1c, 0 },
46412 	{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOK", 0x34e20, 0 },
46413 	{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI", 0x34e24, 0 },
46414 	{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORS", 0x34e28, 0 },
46415 	{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI", 0x34e2c, 0 },
46416 	{ "MAC_PORT_MTIP_1G10G_RX_VLANOK", 0x34e30, 0 },
46417 	{ "MAC_PORT_MTIP_1G10G_RX_VLANOKHI", 0x34e34, 0 },
46418 	{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORS", 0x34e38, 0 },
46419 	{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI", 0x34e3c, 0 },
46420 	{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS", 0x34e40, 0 },
46421 	{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI", 0x34e44, 0 },
46422 	{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS", 0x34e48, 0 },
46423 	{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI", 0x34e4c, 0 },
46424 	{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS", 0x34e50, 0 },
46425 	{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI", 0x34e54, 0 },
46426 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS", 0x34e58, 0 },
46427 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI", 0x34e5c, 0 },
46428 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS", 0x34e60, 0 },
46429 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI", 0x34e64, 0 },
46430 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS", 0x34e68, 0 },
46431 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI", 0x34e6c, 0 },
46432 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS", 0x34e70, 0 },
46433 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI", 0x34e74, 0 },
46434 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS", 0x34e78, 0 },
46435 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI", 0x34e7c, 0 },
46436 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS", 0x34e80, 0 },
46437 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI", 0x34e84, 0 },
46438 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS", 0x34e88, 0 },
46439 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI", 0x34e8c, 0 },
46440 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS", 0x34e90, 0 },
46441 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34e94, 0 },
46442 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS", 0x34e98, 0 },
46443 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34e9c, 0 },
46444 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX", 0x34ea0, 0 },
46445 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI", 0x34ea4, 0 },
46446 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS", 0x34ea8, 0 },
46447 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI", 0x34eac, 0 },
46448 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS", 0x34eb0, 0 },
46449 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI", 0x34eb4, 0 },
46450 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS", 0x34eb8, 0 },
46451 	{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI", 0x34ebc, 0 },
46452 	{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED", 0x34ec0, 0 },
46453 	{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI", 0x34ec4, 0 },
46454 	{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG", 0x34ec8, 0 },
46455 	{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI", 0x34ecc, 0 },
46456 	{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS", 0x34ed0, 0 },
46457 	{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI", 0x34ed4, 0 },
46458 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS", 0x34f00, 0 },
46459 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI", 0x34f04, 0 },
46460 	{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOK", 0x34f08, 0 },
46461 	{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI", 0x34f0c, 0 },
46462 	{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS", 0x34f10, 0 },
46463 	{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI", 0x34f14, 0 },
46464 	{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES", 0x34f18, 0 },
46465 	{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI", 0x34f1c, 0 },
46466 	{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOK", 0x34f20, 0 },
46467 	{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI", 0x34f24, 0 },
46468 	{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORS", 0x34f28, 0 },
46469 	{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI", 0x34f2c, 0 },
46470 	{ "MAC_PORT_MTIP_1G10G_TX_VLANOK", 0x34f30, 0 },
46471 	{ "MAC_PORT_MTIP_1G10G_TX_VLANOKHI", 0x34f34, 0 },
46472 	{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS", 0x34f38, 0 },
46473 	{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI", 0x34f3c, 0 },
46474 	{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS", 0x34f40, 0 },
46475 	{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI", 0x34f44, 0 },
46476 	{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS", 0x34f48, 0 },
46477 	{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI", 0x34f4c, 0 },
46478 	{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS", 0x34f50, 0 },
46479 	{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI", 0x34f54, 0 },
46480 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS", 0x34f58, 0 },
46481 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI", 0x34f5c, 0 },
46482 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS", 0x34f60, 0 },
46483 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI", 0x34f64, 0 },
46484 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS", 0x34f68, 0 },
46485 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI", 0x34f6c, 0 },
46486 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS", 0x34f70, 0 },
46487 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI", 0x34f74, 0 },
46488 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS", 0x34f78, 0 },
46489 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI", 0x34f7c, 0 },
46490 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS", 0x34f80, 0 },
46491 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI", 0x34f84, 0 },
46492 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS", 0x34f88, 0 },
46493 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI", 0x34f8c, 0 },
46494 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS", 0x34f90, 0 },
46495 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34f94, 0 },
46496 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS", 0x34f98, 0 },
46497 	{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34f9c, 0 },
46498 	{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU", 0x34fa0, 0 },
46499 	{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI", 0x34fa4, 0 },
46500 	{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES", 0x34fc0, 0 },
46501 	{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI", 0x34fc4, 0 },
46502 	{ "MAC_PORT_MTIP_1G10G_IF_MODE", 0x35000, 0 },
46504 		{ "IF_MODE", 0, 2 },
46505 	{ "MAC_PORT_MTIP_1G10G_IF_STATUS", 0x35004, 0 },
46506 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0", 0x35080, 0 },
46507 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI", 0x35084, 0 },
46508 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1", 0x35088, 0 },
46509 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI", 0x3508c, 0 },
46510 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2", 0x35090, 0 },
46511 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI", 0x35094, 0 },
46512 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3", 0x35098, 0 },
46513 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI", 0x3509c, 0 },
46514 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4", 0x350a0, 0 },
46515 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI", 0x350a4, 0 },
46516 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5", 0x350a8, 0 },
46517 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI", 0x350ac, 0 },
46518 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6", 0x350b0, 0 },
46519 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI", 0x350b4, 0 },
46520 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7", 0x350b8, 0 },
46521 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI", 0x350bc, 0 },
46522 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0", 0x350c0, 0 },
46523 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI", 0x350c4, 0 },
46524 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1", 0x350c8, 0 },
46525 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI", 0x350cc, 0 },
46526 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2", 0x350d0, 0 },
46527 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI", 0x350d4, 0 },
46528 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3", 0x350d8, 0 },
46529 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI", 0x350dc, 0 },
46530 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4", 0x350e0, 0 },
46531 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI", 0x350e4, 0 },
46532 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5", 0x350e8, 0 },
46533 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI", 0x350ec, 0 },
46534 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6", 0x350f0, 0 },
46535 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI", 0x350f4, 0 },
46536 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7", 0x350f8, 0 },
46537 	{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI", 0x350fc, 0 },
46538 	{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x35200, 0 },
46549 	{ "MAC_PORT_MTIP_SGMII_STATUS", 0x35204, 0 },
46563 		{ "ExtdCapability", 0, 1 },
46564 	{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x35208, 0 },
46565 	{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3520c, 0 },
46566 	{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x35210, 0 },
46575 	{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x35214, 0 },
46580 	{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x35218, 0 },
46583 	{ "MAC_PORT_MTIP_SGMII_NP_TX", 0x3521c, 0 },
46584 	{ "MAC_PORT_MTIP_SGMII_LP_NP_RX", 0x35220, 0 },
46585 	{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3523c, 0 },
46586 	{ "MAC_PORT_MTIP_SGMII_SCRATCH", 0x35240, 0 },
46587 	{ "MAC_PORT_MTIP_SGMII_REV", 0x35244, 0 },
46590 		{ "REV", 0, 8 },
46591 	{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x35248, 0 },
46592 	{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3524c, 0 },
46593 	{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x35250, 0 },
46597 		{ "SGMII_ENA", 0, 1 },
46598 	{ "MAC_PORT_MTIP_SGMII_DECODE_ERROR", 0x35254, 0 },
46599 	{ "MAC_PORT_MTIP_KR_PCS_CONTROL_1", 0x35300, 0 },
46606 	{ "MAC_PORT_MTIP_KR_PCS_STATUS_1", 0x35304, 0 },
46614 	{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1", 0x35308, 0 },
46615 	{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2", 0x3530c, 0 },
46616 	{ "MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY", 0x35310, 0 },
46617 	{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO", 0x35314, 0 },
46624 		{ "Clause_22_Reg_Present", 0, 1 },
46625 	{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI", 0x35318, 0 },
46632 		{ "Clause_22_Reg_Present", 0, 1 },
46633 	{ "MAC_PORT_MTIP_KR_PCS_CONTROL_2", 0x3531c, 0 },
46634 	{ "MAC_PORT_MTIP_KR_PCS_STATUS_2", 0x35320, 0 },
46640 		{ "10GBASE_R_Capable", 0, 1 },
46641 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO", 0x35338, 0 },
46642 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI", 0x3533c, 0 },
46643 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1", 0x35380, 0 },
46648 		{ "10GBASE_R_PCS_Block_Lock", 0, 1 },
46649 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2", 0x35384, 0 },
46653 		{ "ErrBlkCnt", 0, 8 },
46654 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0", 0x35388, 0 },
46655 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1", 0x3538c, 0 },
46656 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2", 0x35390, 0 },
46657 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3", 0x35394, 0 },
46658 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0", 0x35398, 0 },
46659 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1", 0x3539c, 0 },
46660 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2", 0x353a0, 0 },
46661 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3", 0x353a4, 0 },
46662 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL", 0x353a8, 0 },
46669 		{ "Data_Pattern_Select", 0, 1 },
46670 	{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER", 0x353ac, 0 },
46671 	{ "MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS", 0x353b4, 0 },
46673 		{ "Receive_FIFO_Fault", 0, 1 },
46674 	{ "MAC_PORT_MTIP_KR4_CONTROL_1", 0x35400, 0 },
46681 	{ "MAC_PORT_MTIP_KR4_STATUS_1", 0x35404, 0 },
46685 	{ "MAC_PORT_MTIP_KR4_DEVICE_ID0", 0x35408, 0 },
46686 	{ "MAC_PORT_MTIP_KR4_DEVICE_ID1", 0x3540c, 0 },
46688 	{ "MAC_PORT_MTIP_KR4_SPEED_ABILITY", 0x35410, 0 },
46692 		{ "10G_capable", 0, 1 },
46693 	{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1", 0x35414, 0 },
46700 		{ "Clause_22_reg", 0, 1 },
46701 	{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2", 0x35418, 0 },
46705 	{ "MAC_PORT_MTIP_KR4_CONTROL_2", 0x3541c, 0 },
46706 	{ "MAC_PORT_MTIP_KR4_STATUS_2", 0x35420, 0 },
46715 		{ "10GBase_R_capable", 0, 1 },
46716 	{ "MAC_PORT_MTIP_KR4_PKG_ID0", 0x35438, 0 },
46717 	{ "MAC_PORT_MTIP_KR4_PKG_ID1", 0x3543c, 0 },
46718 	{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_1", 0x35480, 0 },
46721 		{ "Block_lock", 0, 1 },
46722 	{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_2", 0x35484, 0 },
46726 		{ "Err_bl_cnt", 0, 8 },
46727 	{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL", 0x354a8, 0 },
46730 	{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT", 0x354ac, 0 },
46731 	{ "MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT", 0x354b0, 0 },
46732 	{ "MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT", 0x354b4, 0 },
46734 		{ "ERR_BLK_CNTR", 0, 14 },
46735 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1", 0x354c8, 0 },
46740 		{ "LANE_0_BLK_LCK", 0, 1 },
46741 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2", 0x354cc, 0 },
46742 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3", 0x354d0, 0 },
46746 		{ "LANE_0_ALIGN_MRKR_LCK", 0, 1 },
46747 	{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4", 0x354d4, 0 },
46748 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0", 0x35720, 0 },
46749 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1", 0x35724, 0 },
46750 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2", 0x35728, 0 },
46751 	{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3", 0x3572c, 0 },
46752 	{ "MAC_PORT_MTIP_KR4_LANE_0_MAPPING", 0x35a40, 0 },
46753 	{ "MAC_PORT_MTIP_KR4_LANE_1_MAPPING", 0x35a44, 0 },
46754 	{ "MAC_PORT_MTIP_KR4_LANE_2_MAPPING", 0x35a48, 0 },
46755 	{ "MAC_PORT_MTIP_KR4_LANE_3_MAPPING", 0x35a4c, 0 },
46756 	{ "MAC_PORT_MTIP_KR4_SCRATCH", 0x35af0, 0 },
46757 	{ "MAC_PORT_MTIP_KR4_CORE_REVISION", 0x35af4, 0 },
46758 	{ "MAC_PORT_MTIP_KR4_VL_INTVL", 0x35af8, 0 },
46759 	{ "MAC_PORT_MTIP_KR4_TX_LANE_THRESH", 0x35afc, 0 },
46760 	{ "MAC_PORT_MTIP_CR4_CONTROL_1", 0x35b00, 0 },
46767 	{ "MAC_PORT_MTIP_CR4_STATUS_1", 0x35b04, 0 },
46771 	{ "MAC_PORT_MTIP_CR4_DEVICE_ID0", 0x35b08, 0 },
46772 	{ "MAC_PORT_MTIP_CR4_DEVICE_ID1", 0x35b0c, 0 },
46773 	{ "MAC_PORT_MTIP_CR4_SPEED_ABILITY", 0x35b10, 0 },
46777 		{ "10G_capable", 0, 1 },
46778 	{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1", 0x35b14, 0 },
46785 		{ "Clause22reg_present", 0, 1 },
46786 	{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2", 0x35b18, 0 },
46790 	{ "MAC_PORT_MTIP_CR4_CONTROL_2", 0x35b1c, 0 },
46791 	{ "MAC_PORT_MTIP_CR4_STATUS_2", 0x35b20, 0 },
46800 		{ "10GBase_R_capable", 0, 1 },
46801 	{ "MAC_PORT_MTIP_CR4_PKG_ID0", 0x35b38, 0 },
46802 	{ "MAC_PORT_MTIP_CR4_PKG_ID1", 0x35b3c, 0 },
46803 	{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_1", 0x35b80, 0 },
46806 		{ "Block_Lock", 0, 1 },
46807 	{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_2", 0x35b84, 0 },
46811 		{ "Errored_blocks_cntr", 0, 8 },
46812 	{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL", 0x35ba8, 0 },
46814 	{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT", 0x35bac, 0 },
46815 	{ "MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT", 0x35bb0, 0 },
46816 	{ "MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT", 0x35bb4, 0 },
46818 		{ "ERR_BLKS_CNTR", 0, 14 },
46819 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1", 0x35bc8, 0 },
46828 		{ "Lane_0_blck_lck", 0, 1 },
46829 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2", 0x35bcc, 0 },
46841 		{ "Lane_8_blck_lck", 0, 1 },
46842 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3", 0x35bd0, 0 },
46850 		{ "Lane0_algn_mrkr_lck", 0, 1 },
46851 	{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4", 0x35bd4, 0 },
46863 		{ "Lane8_algn_mrkr_lck", 0, 1 },
46864 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0", 0x35e20, 0 },
46865 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1", 0x35e24, 0 },
46866 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2", 0x35e28, 0 },
46867 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3", 0x35e2c, 0 },
46868 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4", 0x35e30, 0 },
46869 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5", 0x35e34, 0 },
46870 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6", 0x35e38, 0 },
46871 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7", 0x35e3c, 0 },
46872 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8", 0x35e40, 0 },
46873 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9", 0x35e44, 0 },
46874 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10", 0x35e48, 0 },
46875 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11", 0x35e4c, 0 },
46876 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12", 0x35e50, 0 },
46877 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13", 0x35e54, 0 },
46878 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14", 0x35e58, 0 },
46879 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15", 0x35e5c, 0 },
46880 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16", 0x35e60, 0 },
46881 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17", 0x35e64, 0 },
46882 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18", 0x35e68, 0 },
46883 	{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19", 0x35e6c, 0 },
46884 	{ "MAC_PORT_MTIP_CR4_LANE_0_MAPPING", 0x36140, 0 },
46885 	{ "MAC_PORT_MTIP_CR4_LANE_1_MAPPING", 0x36144, 0 },
46886 	{ "MAC_PORT_MTIP_CR4_LANE_2_MAPPING", 0x36148, 0 },
46887 	{ "MAC_PORT_MTIP_CR4_LANE_3_MAPPING", 0x3614c, 0 },
46888 	{ "MAC_PORT_MTIP_CR4_LANE_4_MAPPING", 0x36150, 0 },
46889 	{ "MAC_PORT_MTIP_CR4_LANE_5_MAPPING", 0x36154, 0 },
46890 	{ "MAC_PORT_MTIP_CR4_LANE_6_MAPPING", 0x36158, 0 },
46891 	{ "MAC_PORT_MTIP_CR4_LANE_7_MAPPING", 0x3615c, 0 },
46892 	{ "MAC_PORT_MTIP_CR4_LANE_8_MAPPING", 0x36160, 0 },
46893 	{ "MAC_PORT_MTIP_CR4_LANE_9_MAPPING", 0x36164, 0 },
46894 	{ "MAC_PORT_MTIP_CR4_LANE_10_MAPPING", 0x36168, 0 },
46895 	{ "MAC_PORT_MTIP_CR4_LANE_11_MAPPING", 0x3616c, 0 },
46896 	{ "MAC_PORT_MTIP_CR4_LANE_12_MAPPING", 0x36170, 0 },
46897 	{ "MAC_PORT_MTIP_CR4_LANE_13_MAPPING", 0x36174, 0 },
46898 	{ "MAC_PORT_MTIP_CR4_LANE_14_MAPPING", 0x36178, 0 },
46899 	{ "MAC_PORT_MTIP_CR4_LANE_15_MAPPING", 0x3617c, 0 },
46900 	{ "MAC_PORT_MTIP_CR4_LANE_16_MAPPING", 0x36180, 0 },
46901 	{ "MAC_PORT_MTIP_CR4_LANE_17_MAPPING", 0x36184, 0 },
46902 	{ "MAC_PORT_MTIP_CR4_LANE_18_MAPPING", 0x36188, 0 },
46903 	{ "MAC_PORT_MTIP_CR4_LANE_19_MAPPING", 0x3618c, 0 },
46904 	{ "MAC_PORT_MTIP_CR4_SCRATCH", 0x361f0, 0 },
46905 	{ "MAC_PORT_MTIP_CR4_CORE_REVISION", 0x361f4, 0 },
46906 	{ "MAC_PORT_MTIP_RS_FEC_CONTROL", 0x36200, 0 },
46908 		{ "RS_FEC_Bypass_Correction", 0, 1 },
46909 	{ "MAC_PORT_MTIP_RS_FEC_STATUS", 0x36204, 0 },
46914 		{ "RS_FEC_bypass_correction_ability", 0, 1 },
46915 	{ "MAC_PORT_MTIP_RS_FEC_CCW_LO", 0x36208, 0 },
46916 	{ "MAC_PORT_MTIP_RS_FEC_CCW_HI", 0x3620c, 0 },
46917 	{ "MAC_PORT_MTIP_RS_FEC_NCCW_LO", 0x36210, 0 },
46918 	{ "MAC_PORT_MTIP_RS_FEC_NCCW_HI", 0x36214, 0 },
46919 	{ "MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI", 0x36218, 0 },
46920 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO", 0x36228, 0 },
46921 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI", 0x3622c, 0 },
46922 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO", 0x36230, 0 },
46923 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI", 0x36234, 0 },
46924 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO", 0x36238, 0 },
46925 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI", 0x3623c, 0 },
46926 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO", 0x36240, 0 },
46927 	{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI", 0x36244, 0 },
46928 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL", 0x36400, 0 },
46931 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1", 0x36404, 0 },
46940 		{ "amps_lock", 0, 4 },
46941 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2", 0x36408, 0 },
46942 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION", 0x3640c, 0 },
46943 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY", 0x36410, 0 },
46944 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS", 0x36414, 0 },
46945 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN", 0x36418, 0 },
46946 	{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER", 0x3641c, 0 },
46947 	{ "MAC_PORT_MTIP_FEC_ABILITY", 0x36618, 0 },
46949 		{ "BASE_R_FEC_Ability", 0, 1 },
46950 	{ "MAC_PORT_FEC_CONTROL", 0x3661c, 0 },
46952 		{ "fec_en", 0, 1 },
46953 	{ "MAC_PORT_FEC_STATUS", 0x36620, 0 },
46955 		{ "FEC_LOCKED", 0, 1 },
46956 	{ "MAC_PORT_MTIP_FEC0_CERR_CNT_0", 0x36624, 0 },
46957 	{ "MAC_PORT_MTIP_FEC0_CERR_CNT_1", 0x36628, 0 },
46958 	{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_0", 0x3662c, 0 },
46959 	{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_1", 0x36630, 0 },
46960 	{ "MAC_PORT_MTIP_FEC_STATUS1", 0x36664, 0 },
46962 		{ "FEC_LOCKED", 0, 1 },
46963 	{ "MAC_PORT_MTIP_FEC1_CERR_CNT_0", 0x36668, 0 },
46964 	{ "MAC_PORT_MTIP_FEC1_CERR_CNT_1", 0x3666c, 0 },
46965 	{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_0", 0x36670, 0 },
46966 	{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_1", 0x36674, 0 },
46967 	{ "MAC_PORT_MTIP_FEC_STATUS2", 0x366a8, 0 },
46969 		{ "FEC_LOCKED", 0, 1 },
46970 	{ "MAC_PORT_MTIP_FEC2_CERR_CNT_0", 0x366ac, 0 },
46971 	{ "MAC_PORT_MTIP_FEC2_CERR_CNT_1", 0x366b0, 0 },
46972 	{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_0", 0x366b4, 0 },
46973 	{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_1", 0x366b8, 0 },
46974 	{ "MAC_PORT_MTIP_FEC_STATUS3", 0x366ec, 0 },
46976 		{ "FEC_LOCKED", 0, 1 },
46977 	{ "MAC_PORT_MTIP_FEC3_CERR_CNT_0", 0x366f0, 0 },
46978 	{ "MAC_PORT_MTIP_FEC3_CERR_CNT_1", 0x366f4, 0 },
46979 	{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_0", 0x366f8, 0 },
46980 	{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_1", 0x366fc, 0 },
46981 	{ "MAC_PORT_BEAN_CTL", 0x36c00, 0 },
46986 	{ "MAC_PORT_BEAN_STATUS", 0x36c04, 0 },
46994 		{ "LP_BEAN_ABILITY", 0, 1 },
46995 	{ "MAC_PORT_BEAN_ABILITY_0", 0x36c08, 0 },
47001 		{ "SELECTOR", 0, 5 },
47002 	{ "MAC_PORT_BEAN_ABILITY_1", 0x36c0c, 0 },
47004 		{ "TX_NONCE", 0, 5 },
47005 	{ "MAC_PORT_BEAN_ABILITY_2", 0x36c10, 0 },
47007 		{ "TECH_ABILITY_2", 0, 14 },
47008 	{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x36c14, 0 },
47014 		{ "SELECTOR", 0, 5 },
47015 	{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x36c18, 0 },
47017 		{ "TX_NONCE", 0, 5 },
47018 	{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x36c1c, 0 },
47020 		{ "TECH_ABILITY_2", 0, 14 },
47021 	{ "MAC_PORT_BEAN_MS_COUNT", 0x36c20, 0 },
47022 	{ "MAC_PORT_BEAN_XNP_0", 0x36c24, 0 },
47028 		{ "MU", 0, 11 },
47029 	{ "MAC_PORT_BEAN_XNP_1", 0x36c28, 0 },
47030 	{ "MAC_PORT_BEAN_XNP_2", 0x36c2c, 0 },
47031 	{ "MAC_PORT_LP_BEAN_XNP_0", 0x36c30, 0 },
47037 		{ "MU", 0, 11 },
47038 	{ "MAC_PORT_LP_BEAN_XNP_1", 0x36c34, 0 },
47039 	{ "MAC_PORT_LP_BEAN_XNP_2", 0x36c38, 0 },
47040 	{ "MAC_PORT_BEAN_ETH_STATUS", 0x36c3c, 0 },
47051 	{ "MAC_PORT_AE_RX_COEF_REQ", 0x36a00, 0 },
47057 		{ "T5_RXREQ_C0", 0, 2 },
47058 	{ "MAC_PORT_AE_RX_COEF_STAT", 0x36a04, 0 },
47066 		{ "T5_AE0_RXSTAT_C0", 0, 2 },
47067 	{ "MAC_PORT_AE_TX_COEF_REQ", 0x36a08, 0 },
47074 		{ "T5_TXREQ_C0", 0, 2 },
47075 	{ "MAC_PORT_AE_TX_COEF_STAT", 0x36a0c, 0 },
47080 		{ "T5_TXSTAT_C0", 0, 2 },
47081 	{ "MAC_PORT_AE_REG_MODE", 0x36a10, 0 },
47094 		{ "STICKY_MODE", 0, 1 },
47095 	{ "MAC_PORT_AE_PRBS_CTL", 0x36a14, 0 },
47102 		{ "PRBS_GEN_OFF", 0, 1 },
47103 	{ "MAC_PORT_AE_FSM_CTL", 0x36a18, 0 },
47115 		{ "FSM_TR_EN", 0, 1 },
47116 	{ "MAC_PORT_AE_FSM_STATE", 0x36a1c, 0 },
47121 		{ "TFSM_STATE", 0, 3 },
47122 	{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x36a20, 0 },
47128 		{ "T5_RXREQ_C0", 0, 2 },
47129 	{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x36a24, 0 },
47137 		{ "T5_AE1_RXSTAT_C0", 0, 2 },
47138 	{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x36a28, 0 },
47145 		{ "T5_TXREQ_C0", 0, 2 },
47146 	{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x36a2c, 0 },
47151 		{ "T5_TXSTAT_C0", 0, 2 },
47152 	{ "MAC_PORT_AE_REG_MODE_1", 0x36a30, 0 },
47165 		{ "STICKY_MODE", 0, 1 },
47166 	{ "MAC_PORT_AE_PRBS_CTL_1", 0x36a34, 0 },
47173 		{ "PRBS_GEN_OFF", 0, 1 },
47174 	{ "MAC_PORT_AE_FSM_CTL_1", 0x36a38, 0 },
47186 		{ "FSM_TR_EN", 0, 1 },
47187 	{ "MAC_PORT_AE_FSM_STATE_1", 0x36a3c, 0 },
47192 		{ "TFSM_STATE", 0, 3 },
47193 	{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x36a40, 0 },
47199 		{ "T5_RXREQ_C0", 0, 2 },
47200 	{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x36a44, 0 },
47208 		{ "T5_AE2_RXSTAT_C0", 0, 2 },
47209 	{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x36a48, 0 },
47216 		{ "T5_TXREQ_C0", 0, 2 },
47217 	{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x36a4c, 0 },
47222 		{ "T5_TXSTAT_C0", 0, 2 },
47223 	{ "MAC_PORT_AE_REG_MODE_2", 0x36a50, 0 },
47236 		{ "STICKY_MODE", 0, 1 },
47237 	{ "MAC_PORT_AE_PRBS_CTL_2", 0x36a54, 0 },
47244 		{ "PRBS_GEN_OFF", 0, 1 },
47245 	{ "MAC_PORT_AE_FSM_CTL_2", 0x36a58, 0 },
47257 		{ "FSM_TR_EN", 0, 1 },
47258 	{ "MAC_PORT_AE_FSM_STATE_2", 0x36a5c, 0 },
47263 		{ "TFSM_STATE", 0, 3 },
47264 	{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x36a60, 0 },
47270 		{ "T5_RXREQ_C0", 0, 2 },
47271 	{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x36a64, 0 },
47279 		{ "T5_AE3_RXSTAT_C0", 0, 2 },
47280 	{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x36a68, 0 },
47287 		{ "T5_TXREQ_C0", 0, 2 },
47288 	{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x36a6c, 0 },
47293 		{ "T5_TXSTAT_C0", 0, 2 },
47294 	{ "MAC_PORT_AE_REG_MODE_3", 0x36a70, 0 },
47307 		{ "STICKY_MODE", 0, 1 },
47308 	{ "MAC_PORT_AE_PRBS_CTL_3", 0x36a74, 0 },
47315 		{ "PRBS_GEN_OFF", 0, 1 },
47316 	{ "MAC_PORT_AE_FSM_CTL_3", 0x36a78, 0 },
47328 		{ "FSM_TR_EN", 0, 1 },
47329 	{ "MAC_PORT_AE_FSM_STATE_3", 0x36a7c, 0 },
47334 		{ "TFSM_STATE", 0, 3 },
47335 	{ "MAC_PORT_AE_TX_DIS", 0x36a80, 0 },
47336 	{ "MAC_PORT_AE_KR_CTRL", 0x36a84, 0 },
47338 		{ "Restart_Training", 0, 1 },
47339 	{ "MAC_PORT_AE_RX_SIGDET", 0x36a88, 0 },
47340 	{ "MAC_PORT_AE_KR_STATUS", 0x36a8c, 0 },
47344 		{ "RX_Trained", 0, 1 },
47345 	{ "MAC_PORT_AE_TX_DIS_1", 0x36a90, 0 },
47346 	{ "MAC_PORT_AE_KR_CTRL_1", 0x36a94, 0 },
47348 		{ "Restart_Training", 0, 1 },
47349 	{ "MAC_PORT_AE_RX_SIGDET_1", 0x36a98, 0 },
47350 	{ "MAC_PORT_AE_KR_STATUS_1", 0x36a9c, 0 },
47354 		{ "RX_Trained", 0, 1 },
47355 	{ "MAC_PORT_AE_TX_DIS_2", 0x36aa0, 0 },
47356 	{ "MAC_PORT_AE_KR_CTRL_2", 0x36aa4, 0 },
47358 		{ "Restart_Training", 0, 1 },
47359 	{ "MAC_PORT_AE_RX_SIGDET_2", 0x36aa8, 0 },
47360 	{ "MAC_PORT_AE_KR_STATUS_2", 0x36aac, 0 },
47364 		{ "RX_Trained", 0, 1 },
47365 	{ "MAC_PORT_AE_TX_DIS_3", 0x36ab0, 0 },
47366 	{ "MAC_PORT_AE_KR_CTRL_3", 0x36ab4, 0 },
47368 		{ "Restart_Training", 0, 1 },
47369 	{ "MAC_PORT_AE_RX_SIGDET_3", 0x36ab8, 0 },
47370 	{ "MAC_PORT_AE_KR_STATUS_3", 0x36abc, 0 },
47374 		{ "RX_Trained", 0, 1 },
47375 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x36b00, 0 },
47382 		{ "H1TEQ_GOAL", 0, 3 },
47383 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x36b04, 0 },
47391 		{ "AMIN_TH", 0, 4 },
47392 	{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x36b08, 0 },
47395 		{ "TOG_LIM", 0, 4 },
47396 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x36b0c, 0 },
47402 	{ "MAC_PORT_AET_STATUS_0", 0x36b10, 0 },
47405 		{ "CTRL_STATE", 0, 4 },
47406 	{ "MAC_PORT_AET_STATUS_20", 0x36b14, 0 },
47407 	{ "MAC_PORT_AET_LIMITS0", 0x36b18, 0 },
47408 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x36b20, 0 },
47415 		{ "H1TEQ_GOAL", 0, 3 },
47416 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x36b24, 0 },
47424 		{ "AMIN_TH", 0, 4 },
47425 	{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x36b28, 0 },
47428 		{ "TOG_LIM", 0, 4 },
47429 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x36b2c, 0 },
47435 	{ "MAC_PORT_AET_STATUS_1", 0x36b30, 0 },
47438 		{ "CTRL_STATE", 0, 4 },
47439 	{ "MAC_PORT_AET_STATUS_21", 0x36b34, 0 },
47440 	{ "MAC_PORT_AET_LIMITS1", 0x36b38, 0 },
47441 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x36b40, 0 },
47448 		{ "H1TEQ_GOAL", 0, 3 },
47449 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x36b44, 0 },
47457 		{ "AMIN_TH", 0, 4 },
47458 	{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x36b48, 0 },
47461 		{ "TOG_LIM", 0, 4 },
47462 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x36b4c, 0 },
47468 	{ "MAC_PORT_AET_STATUS_2", 0x36b50, 0 },
47471 		{ "CTRL_STATE", 0, 4 },
47472 	{ "MAC_PORT_AET_STATUS_22", 0x36b54, 0 },
47473 	{ "MAC_PORT_AET_LIMITS2", 0x36b58, 0 },
47474 	{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x36b60, 0 },
47481 		{ "H1TEQ_GOAL", 0, 3 },
47482 	{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x36b64, 0 },
47490 		{ "AMIN_TH", 0, 4 },
47491 	{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x36b68, 0 },
47494 		{ "TOG_LIM", 0, 4 },
47495 	{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x36b6c, 0 },
47501 	{ "MAC_PORT_AET_STATUS_3", 0x36b70, 0 },
47504 		{ "CTRL_STATE", 0, 4 },
47505 	{ "MAC_PORT_AET_STATUS_23", 0x36b74, 0 },
47506 	{ "MAC_PORT_AET_LIMITS3", 0x36b78, 0 },
47507 	{ "MAC_PORT_ANALOG_TEST_MUX", 0x37814, 0 },
47508 	{ "MAC_PORT_PLLREFSEL_CONTROL", 0x37854, 0 },
47509 	{ "MAC_PORT_REFISINK_CONTROL", 0x37858, 0 },
47510 	{ "MAC_PORT_REFISRC_CONTROL", 0x3785c, 0 },
47511 	{ "MAC_PORT_REFVREG_CONTROL", 0x37860, 0 },
47512 	{ "MAC_PORT_VBGENDOC_CONTROL", 0x37864, 0 },
47514 		{ "VBGENDOC", 0, 2 },
47515 	{ "MAC_PORT_VREFTUNE_CONTROL", 0x37868, 0 },
47516 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL", 0x37880, 0 },
47520 		{ "RCAL_RESET", 0, 1 },
47521 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1", 0x37884, 0 },
47525 		{ "RCALCOMP", 0, 1 },
47526 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2", 0x37888, 0 },
47527 	{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3", 0x3788c, 0 },
47528 	{ "MAC_PORT_INEQUALITY_CONTROL_AND_RESULT", 0x378c0, 0 },
47534 		{ "INEQ", 0, 1 },
47535 	{ "MAC_PORT_INEQUALITY_LOW_LIMIT", 0x378c4, 0 },
47536 	{ "MAC_PORT_INEQUALITY_LOW_LIMIT_MASK", 0x378c8, 0 },
47537 	{ "MAC_PORT_INEQUALITY_HIGH_LIMIT", 0x378cc, 0 },
47538 	{ "MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK", 0x378d0, 0 },
47539 	{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x378e8, 0 },
47543 		{ "HSSACJAC", 0, 1 },
47544 	{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x378ec, 0 },
47551 		{ "MACROTEST", 0, 1 },
47552 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x37b00, 0 },
47553 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x37b04, 0 },
47557 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x37b08, 0 },
47558 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x37b0c, 0 },
47562 	{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x37b10, 0 },
47565 		{ "CCLD", 0, 1 },
47566 	{ "MAC_PORT_PLLA_POWER_CONTROL", 0x37b24, 0 },
47568 		{ "NPWRENA", 0, 1 },
47569 	{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x37b28, 0 },
47570 	{ "MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL", 0x37b38, 0 },
47571 	{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x37b3c, 0 },
47573 		{ "PCKSEL", 0, 3 },
47574 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x37b40, 0 },
47577 		{ "EMIS", 0, 1 },
47578 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x37b44, 0 },
47579 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x37b48, 0 },
47580 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x37b4c, 0 },
47581 	{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x37b50, 0 },
47582 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x37bf0, 0 },
47584 		{ "REFDIV", 0, 4 },
47585 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x37bf4, 0 },
47591 		{ "DIVSEL8", 0, 1 },
47592 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x37bf8, 0 },
47593 	{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x37bfc, 0 },
47594 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x37c00, 0 },
47595 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x37c04, 0 },
47599 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x37c08, 0 },
47600 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x37c0c, 0 },
47604 	{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x37c10, 0 },
47607 		{ "CCLD", 0, 1 },
47608 	{ "MAC_PORT_PLLB_POWER_CONTROL", 0x37c24, 0 },
47610 		{ "NPWRENA", 0, 1 },
47611 	{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x37c28, 0 },
47612 	{ "MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL", 0x37c38, 0 },
47613 	{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x37c3c, 0 },
47615 		{ "PCKSEL", 0, 3 },
47616 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x37c40, 0 },
47619 		{ "EMIS", 0, 1 },
47620 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x37c44, 0 },
47621 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x37c48, 0 },
47622 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x37c4c, 0 },
47623 	{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x37c50, 0 },
47624 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x37cf0, 0 },
47626 		{ "REFDIV", 0, 4 },
47627 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x37cf4, 0 },
47633 		{ "DIVSEL8", 0, 1 },
47634 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x37cf8, 0 },
47635 	{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x37cfc, 0 },
47636 	{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x37000, 0 },
47648 		{ "T5_TX_RTSEL", 0, 2 },
47649 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x37004, 0 },
47657 		{ "TPSEL", 0, 3 },
47658 	{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x37008, 0 },
47666 		{ "ALOAD", 0, 1 },
47667 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3700c, 0 },
47670 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37010, 0 },
47672 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37014, 0 },
47677 	{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37018, 0 },
47679 		{ "CALSSTP", 0, 6 },
47680 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3701c, 0 },
47682 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x37020, 0 },
47683 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x37024, 0 },
47684 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x37028, 0 },
47685 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT", 0x3702c, 0 },
47686 	{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x37034, 0 },
47687 	{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37038, 0 },
47694 		{ "C1UPDT", 0, 2 },
47695 	{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3703c, 0 },
47699 		{ "C1STAT", 0, 2 },
47700 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37040, 0 },
47701 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37044, 0 },
47702 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37048, 0 },
47703 	{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3704c, 0 },
47704 	{ "MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37050, 0 },
47706 		{ "ATUNEP", 0, 8 },
47707 	{ "MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37058, 0 },
47709 	{ "MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED", 0x37060, 0 },
47717 		{ "AS4X0", 0, 2 },
47718 	{ "MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED", 0x37064, 0 },
47722 		{ "AS2X0", 0, 2 },
47723 	{ "MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED", 0x37068, 0 },
47731 		{ "AS1X0", 0, 2 },
47732 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3706c, 0 },
47733 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37070, 0 },
47735 		{ "AT4X", 0, 8 },
47736 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37074, 0 },
47737 	{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37078, 0 },
47738 	{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3707c, 0 },
47740 		{ "XWR", 0, 1 },
47741 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37080, 0 },
47742 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37084, 0 },
47743 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37088, 0 },
47744 	{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3708c, 0 },
47745 	{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3709c, 0 },
47746 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x370a0, 0 },
47752 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x370a4, 0 },
47758 		{ "DCCOEN", 0, 1 },
47759 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x370a8, 0 },
47761 		{ "DCCAAMP", 0, 7 },
47762 	{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x370ac, 0 },
47763 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE", 0x370c0, 0 },
47764 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x370c8, 0 },
47772 		{ "OS4X0", 0, 2 },
47773 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x370cc, 0 },
47777 		{ "OS2X0", 0, 2 },
47778 	{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x370d0, 0 },
47786 		{ "OS1X0", 0, 2 },
47787 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x370d8, 0 },
47788 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x370dc, 0 },
47789 	{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x370e0, 0 },
47790 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5", 0x370ec, 0 },
47798 		{ "DATASIGN", 0, 1 },
47799 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x370f0, 0 },
47800 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x370f4, 0 },
47801 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x370f8, 0 },
47804 		{ "AECMD70", 0, 8 },
47805 	{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x370fc, 0 },
47813 		{ "OBS", 0, 1 },
47814 	{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x37100, 0 },
47826 		{ "T5_TX_RTSEL", 0, 2 },
47827 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x37104, 0 },
47835 		{ "TPSEL", 0, 3 },
47836 	{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x37108, 0 },
47844 		{ "ALOAD", 0, 1 },
47845 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3710c, 0 },
47848 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37110, 0 },
47850 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37114, 0 },
47855 	{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37118, 0 },
47857 		{ "CALSSTP", 0, 6 },
47858 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3711c, 0 },
47860 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x37120, 0 },
47861 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x37124, 0 },
47862 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x37128, 0 },
47863 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT", 0x3712c, 0 },
47864 	{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x37134, 0 },
47865 	{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37138, 0 },
47872 		{ "C1UPDT", 0, 2 },
47873 	{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3713c, 0 },
47877 		{ "C1STAT", 0, 2 },
47878 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37140, 0 },
47879 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37144, 0 },
47880 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37148, 0 },
47881 	{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3714c, 0 },
47882 	{ "MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37150, 0 },
47884 		{ "ATUNEP", 0, 8 },
47885 	{ "MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37158, 0 },
47887 	{ "MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED", 0x37160, 0 },
47895 		{ "AS4X0", 0, 2 },
47896 	{ "MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED", 0x37164, 0 },
47900 		{ "AS2X0", 0, 2 },
47901 	{ "MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED", 0x37168, 0 },
47909 		{ "AS1X0", 0, 2 },
47910 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3716c, 0 },
47911 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37170, 0 },
47913 		{ "AT4X", 0, 8 },
47914 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37174, 0 },
47915 	{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37178, 0 },
47916 	{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3717c, 0 },
47918 		{ "XWR", 0, 1 },
47919 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37180, 0 },
47920 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37184, 0 },
47921 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37188, 0 },
47922 	{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3718c, 0 },
47923 	{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3719c, 0 },
47924 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x371a0, 0 },
47930 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x371a4, 0 },
47936 		{ "DCCOEN", 0, 1 },
47937 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x371a8, 0 },
47939 		{ "DCCAAMP", 0, 7 },
47940 	{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x371ac, 0 },
47941 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE", 0x371c0, 0 },
47942 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x371c8, 0 },
47950 		{ "OS4X0", 0, 2 },
47951 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x371cc, 0 },
47955 		{ "OS2X0", 0, 2 },
47956 	{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x371d0, 0 },
47964 		{ "OS1X0", 0, 2 },
47965 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x371d8, 0 },
47966 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x371dc, 0 },
47967 	{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x371e0, 0 },
47968 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5", 0x371ec, 0 },
47976 		{ "DATASIGN", 0, 1 },
47977 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x371f0, 0 },
47978 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x371f4, 0 },
47979 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x371f8, 0 },
47982 		{ "AECMD70", 0, 8 },
47983 	{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x371fc, 0 },
47991 		{ "OBS", 0, 1 },
47992 	{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x37400, 0 },
48004 		{ "T5_TX_RTSEL", 0, 2 },
48005 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x37404, 0 },
48013 		{ "TPSEL", 0, 3 },
48014 	{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x37408, 0 },
48022 		{ "ALOAD", 0, 1 },
48023 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3740c, 0 },
48026 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37410, 0 },
48028 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37414, 0 },
48033 	{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37418, 0 },
48035 		{ "CALSSTP", 0, 6 },
48036 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3741c, 0 },
48038 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x37420, 0 },
48039 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x37424, 0 },
48040 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x37428, 0 },
48041 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT", 0x3742c, 0 },
48042 	{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x37434, 0 },
48043 	{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37438, 0 },
48050 		{ "C1UPDT", 0, 2 },
48051 	{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3743c, 0 },
48055 		{ "C1STAT", 0, 2 },
48056 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37440, 0 },
48057 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37444, 0 },
48058 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37448, 0 },
48059 	{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3744c, 0 },
48060 	{ "MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37450, 0 },
48062 		{ "ATUNEP", 0, 8 },
48063 	{ "MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37458, 0 },
48065 	{ "MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED", 0x37460, 0 },
48073 		{ "AS4X0", 0, 2 },
48074 	{ "MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED", 0x37464, 0 },
48078 		{ "AS2X0", 0, 2 },
48079 	{ "MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED", 0x37468, 0 },
48087 		{ "AS1X0", 0, 2 },
48088 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3746c, 0 },
48089 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37470, 0 },
48091 		{ "AT4X", 0, 8 },
48092 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37474, 0 },
48093 	{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37478, 0 },
48094 	{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3747c, 0 },
48096 		{ "XWR", 0, 1 },
48097 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37480, 0 },
48098 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37484, 0 },
48099 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37488, 0 },
48100 	{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3748c, 0 },
48101 	{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3749c, 0 },
48102 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x374a0, 0 },
48108 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x374a4, 0 },
48114 		{ "DCCOEN", 0, 1 },
48115 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x374a8, 0 },
48117 		{ "DCCAAMP", 0, 7 },
48118 	{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x374ac, 0 },
48119 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE", 0x374c0, 0 },
48120 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x374c8, 0 },
48128 		{ "OS4X0", 0, 2 },
48129 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x374cc, 0 },
48133 		{ "OS2X0", 0, 2 },
48134 	{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x374d0, 0 },
48142 		{ "OS1X0", 0, 2 },
48143 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x374d8, 0 },
48144 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x374dc, 0 },
48145 	{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x374e0, 0 },
48146 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5", 0x374ec, 0 },
48154 		{ "DATASIGN", 0, 1 },
48155 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x374f0, 0 },
48156 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x374f4, 0 },
48157 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x374f8, 0 },
48160 		{ "AECMD70", 0, 8 },
48161 	{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x374fc, 0 },
48169 		{ "OBS", 0, 1 },
48170 	{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x37500, 0 },
48182 		{ "T5_TX_RTSEL", 0, 2 },
48183 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x37504, 0 },
48191 		{ "TPSEL", 0, 3 },
48192 	{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x37508, 0 },
48200 		{ "ALOAD", 0, 1 },
48201 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3750c, 0 },
48204 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37510, 0 },
48206 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37514, 0 },
48211 	{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37518, 0 },
48213 		{ "CALSSTP", 0, 6 },
48214 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3751c, 0 },
48216 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x37520, 0 },
48217 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x37524, 0 },
48218 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x37528, 0 },
48219 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT", 0x3752c, 0 },
48220 	{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x37534, 0 },
48221 	{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37538, 0 },
48228 		{ "C1UPDT", 0, 2 },
48229 	{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3753c, 0 },
48233 		{ "C1STAT", 0, 2 },
48234 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37540, 0 },
48235 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37544, 0 },
48236 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37548, 0 },
48237 	{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3754c, 0 },
48238 	{ "MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37550, 0 },
48240 		{ "ATUNEP", 0, 8 },
48241 	{ "MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37558, 0 },
48243 	{ "MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED", 0x37560, 0 },
48251 		{ "AS4X0", 0, 2 },
48252 	{ "MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED", 0x37564, 0 },
48256 		{ "AS2X0", 0, 2 },
48257 	{ "MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED", 0x37568, 0 },
48265 		{ "AS1X0", 0, 2 },
48266 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3756c, 0 },
48267 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37570, 0 },
48269 		{ "AT4X", 0, 8 },
48270 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37574, 0 },
48271 	{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37578, 0 },
48272 	{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3757c, 0 },
48274 		{ "XWR", 0, 1 },
48275 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37580, 0 },
48276 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37584, 0 },
48277 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37588, 0 },
48278 	{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3758c, 0 },
48279 	{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3759c, 0 },
48280 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x375a0, 0 },
48286 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x375a4, 0 },
48292 		{ "DCCOEN", 0, 1 },
48293 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x375a8, 0 },
48295 		{ "DCCAAMP", 0, 7 },
48296 	{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x375ac, 0 },
48297 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE", 0x375c0, 0 },
48298 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x375c8, 0 },
48306 		{ "OS4X0", 0, 2 },
48307 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x375cc, 0 },
48311 		{ "OS2X0", 0, 2 },
48312 	{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x375d0, 0 },
48320 		{ "OS1X0", 0, 2 },
48321 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x375d8, 0 },
48322 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x375dc, 0 },
48323 	{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x375e0, 0 },
48324 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5", 0x375ec, 0 },
48332 		{ "DATASIGN", 0, 1 },
48333 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x375f0, 0 },
48334 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x375f4, 0 },
48335 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x375f8, 0 },
48338 		{ "AECMD70", 0, 8 },
48339 	{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x375fc, 0 },
48347 		{ "OBS", 0, 1 },
48348 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x37900, 0 },
48360 		{ "T5_TX_RTSEL", 0, 2 },
48361 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x37904, 0 },
48369 		{ "TPSEL", 0, 3 },
48370 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x37908, 0 },
48378 		{ "ALOAD", 0, 1 },
48379 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3790c, 0 },
48382 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37910, 0 },
48384 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37914, 0 },
48389 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37918, 0 },
48391 		{ "CALSSTP", 0, 6 },
48392 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3791c, 0 },
48394 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x37920, 0 },
48395 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x37924, 0 },
48396 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x37928, 0 },
48397 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT", 0x3792c, 0 },
48398 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x37934, 0 },
48399 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37938, 0 },
48406 		{ "C1UPDT", 0, 2 },
48407 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3793c, 0 },
48411 		{ "C1STAT", 0, 2 },
48412 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37940, 0 },
48413 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37944, 0 },
48414 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37948, 0 },
48415 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3794c, 0 },
48416 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37950, 0 },
48418 		{ "ATUNEP", 0, 8 },
48419 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37958, 0 },
48421 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED", 0x37960, 0 },
48429 		{ "AS4X0", 0, 2 },
48430 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED", 0x37964, 0 },
48434 		{ "AS2X0", 0, 2 },
48435 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED", 0x37968, 0 },
48443 		{ "AS1X0", 0, 2 },
48444 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3796c, 0 },
48445 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37970, 0 },
48447 		{ "AT4X", 0, 8 },
48448 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37974, 0 },
48449 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37978, 0 },
48450 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3797c, 0 },
48452 		{ "XWR", 0, 1 },
48453 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37980, 0 },
48454 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37984, 0 },
48455 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37988, 0 },
48456 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3798c, 0 },
48457 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3799c, 0 },
48458 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x379a0, 0 },
48464 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x379a4, 0 },
48470 		{ "DCCOEN", 0, 1 },
48471 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x379a8, 0 },
48473 		{ "DCCAAMP", 0, 7 },
48474 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x379ac, 0 },
48475 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE", 0x379c0, 0 },
48476 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x379c8, 0 },
48484 		{ "OS4X0", 0, 2 },
48485 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x379cc, 0 },
48489 		{ "OS2X0", 0, 2 },
48490 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x379d0, 0 },
48498 		{ "OS1X0", 0, 2 },
48499 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x379d8, 0 },
48500 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x379dc, 0 },
48501 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x379e0, 0 },
48502 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5", 0x379ec, 0 },
48510 		{ "DATASIGN", 0, 1 },
48511 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x379f0, 0 },
48512 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x379f4, 0 },
48513 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x379f8, 0 },
48516 		{ "AECMD70", 0, 8 },
48517 	{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x379fc, 0 },
48525 		{ "OBS", 0, 1 },
48526 	{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x37200, 0 },
48537 		{ "T5_RX_RTSEL", 0, 2 },
48538 	{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x37204, 0 },
48550 		{ "PATSEL", 0, 3 },
48551 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x37208, 0 },
48560 		{ "SSCEN", 0, 1 },
48561 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3720c, 0 },
48568 		{ "PHOFFS", 0, 6 },
48569 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x37210, 0 },
48571 		{ "ROTD", 0, 6 },
48572 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x37214, 0 },
48575 		{ "ROTE", 0, 6 },
48576 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37218, 0 },
48579 		{ "RAOFF", 0, 5 },
48580 	{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3721c, 0 },
48582 		{ "RDOFF", 0, 5 },
48583 	{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x37220, 0 },
48594 		{ "DFERST", 0, 1 },
48595 	{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x37224, 0 },
48597 		{ "T5BYTE0", 0, 8 },
48598 	{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x37228, 0 },
48605 		{ "T5_RX_ASAMP", 0, 3 },
48606 	{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3722c, 0 },
48610 		{ "VOFFA", 0, 6 },
48611 	{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x37230, 0 },
48619 		{ "T5VGAIN", 0, 7 },
48620 	{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x37234, 0 },
48625 		{ "AMAXT", 0, 7 },
48626 	{ "MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37238, 0 },
48628 		{ "PMOFFTIME", 0, 6 },
48629 	{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1", 0x3723c, 0 },
48632 		{ "IQAMP", 0, 5 },
48633 	{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2", 0x37240, 0 },
48634 	{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37244, 0 },
48641 		{ "DASEL", 0, 3 },
48642 	{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x37248, 0 },
48644 		{ "DACAP", 0, 8 },
48645 	{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN", 0x3724c, 0 },
48647 		{ "DACAM", 0, 8 },
48648 	{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x37250, 0 },
48650 		{ "ADAC1", 0, 8 },
48651 	{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL", 0x37254, 0 },
48657 		{ "FACCPL", 0, 1 },
48658 	{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE", 0x37258, 0 },
48661 		{ "ACCPLBIAS", 0, 8 },
48662 	{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET", 0x3725c, 0 },
48663 	{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37260, 0 },
48665 		{ "H1EX", 0, 6 },
48666 	{ "MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR", 0x37264, 0 },
48669 		{ "UNPKVGA", 0, 2 },
48670 	{ "MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH", 0x37268, 0 },
48679 		{ "CDRANLGSW", 0, 2 },
48680 	{ "MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3726c, 0 },
48682 …{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37270, 0 …
48693 		{ "OAE", 0, 4 },
48694 	{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x37274, 0 },
48699 		{ "ODEC", 0, 4 },
48700 	{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x37278, 0 },
48716 		{ "T5OCCMP", 0, 1 },
48717 	{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3727c, 0 },
48733 		{ "FADAC", 0, 1 },
48734 	{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x37280, 0 },
48750 		{ "FQCC", 0, 1 },
48751 	{ "MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL", 0x37284, 0 },
48756 		{ "LOFCH", 0, 5 },
48757 	{ "MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE", 0x37288, 0 },
48759 		{ "LOFL", 0, 7 },
48760 	{ "MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST", 0x3728c, 0 },
48768 		{ "HSEL", 0, 4 },
48769 	{ "MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST", 0x37290, 0 },
48774 		{ "ACCRD", 0, 8 },
48775 	{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER", 0x37298, 0 },
48783 		{ "LCURR", 0, 5 },
48784 	{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3729c, 0 },
48790 		{ "SDLVL", 0, 5 },
48791 	{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x372a0, 0 },
48800 		{ "RX_LINKANLGSW", 0, 7 },
48801 	{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x372a4, 0 },
48805 		{ "INTDAC", 0, 6 },
48806 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x372a8, 0 },
48810 		{ "MINAMP", 0, 5 },
48811 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x372ac, 0 },
48817 		{ "EMEN", 0, 1 },
48818 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x372b0, 0 },
48824 		{ "EMCEN", 0, 1 },
48825 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x372b4, 0 },
48828 		{ "APDF", 0, 12 },
48829 	{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x372b8, 0 },
48830 	{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3", 0x372bc, 0 },
48846 		{ "FPRBSOFF", 0, 1 },
48847 	{ "MAC_PORT_RX_LINKA_DFE_TAP_CONTROL", 0x372c0, 0 },
48848 	{ "MAC_PORT_RX_LINKA_DFE_TAP", 0x372c4, 0 },
48849 	{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2", 0x372e4, 0 },
48857 		{ "QCCCMP", 0, 1 },
48858 	{ "MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x372e8, 0 },
48861 		{ "CSVAL", 0, 3 },
48862 	{ "MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL", 0x372ec, 0 },
48871 		{ "DCDAMP", 0, 6 },
48872 	{ "MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL", 0x372f0, 0 },
48878 		{ "DCDAMP", 0, 6 },
48879 	{ "MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL", 0x372f4, 0 },
48887 		{ "QCDAMP", 0, 6 },
48888 	{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x372f8, 0 },
48895 		{ "ACJZNT", 0, 1 },
48896 	{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x372fc, 0 },
48907 		{ "MTHOLD", 0, 1 },
48908 	{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x37300, 0 },
48919 		{ "T5_RX_RTSEL", 0, 2 },
48920 	{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x37304, 0 },
48932 		{ "PATSEL", 0, 3 },
48933 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x37308, 0 },
48942 		{ "SSCEN", 0, 1 },
48943 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3730c, 0 },
48950 		{ "PHOFFS", 0, 6 },
48951 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x37310, 0 },
48953 		{ "ROTD", 0, 6 },
48954 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x37314, 0 },
48957 		{ "ROTE", 0, 6 },
48958 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37318, 0 },
48961 		{ "RAOFF", 0, 5 },
48962 	{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3731c, 0 },
48964 		{ "RDOFF", 0, 5 },
48965 	{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x37320, 0 },
48976 		{ "DFERST", 0, 1 },
48977 	{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x37324, 0 },
48979 		{ "T5BYTE0", 0, 8 },
48980 	{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x37328, 0 },
48987 		{ "T5_RX_ASAMP", 0, 3 },
48988 	{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3732c, 0 },
48992 		{ "VOFFA", 0, 6 },
48993 	{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x37330, 0 },
49001 		{ "T5VGAIN", 0, 7 },
49002 	{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x37334, 0 },
49007 		{ "AMAXT", 0, 7 },
49008 	{ "MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37338, 0 },
49010 		{ "PMOFFTIME", 0, 6 },
49011 	{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1", 0x3733c, 0 },
49014 		{ "IQAMP", 0, 5 },
49015 	{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2", 0x37340, 0 },
49016 	{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37344, 0 },
49023 		{ "DASEL", 0, 3 },
49024 	{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x37348, 0 },
49026 		{ "DACAP", 0, 8 },
49027 	{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN", 0x3734c, 0 },
49029 		{ "DACAM", 0, 8 },
49030 	{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x37350, 0 },
49032 		{ "ADAC1", 0, 8 },
49033 	{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL", 0x37354, 0 },
49039 		{ "FACCPL", 0, 1 },
49040 	{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE", 0x37358, 0 },
49043 		{ "ACCPLBIAS", 0, 8 },
49044 	{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET", 0x3735c, 0 },
49045 	{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37360, 0 },
49047 		{ "H1EX", 0, 6 },
49048 	{ "MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR", 0x37364, 0 },
49051 		{ "UNPKVGA", 0, 2 },
49052 	{ "MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH", 0x37368, 0 },
49061 		{ "CDRANLGSW", 0, 2 },
49062 	{ "MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3736c, 0 },
49064 …{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37370, 0 …
49075 		{ "OAE", 0, 4 },
49076 	{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x37374, 0 },
49081 		{ "ODEC", 0, 4 },
49082 	{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x37378, 0 },
49098 		{ "T5OCCMP", 0, 1 },
49099 	{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3737c, 0 },
49115 		{ "FADAC", 0, 1 },
49116 	{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x37380, 0 },
49132 		{ "FQCC", 0, 1 },
49133 	{ "MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL", 0x37384, 0 },
49138 		{ "LOFCH", 0, 5 },
49139 	{ "MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE", 0x37388, 0 },
49141 		{ "LOFL", 0, 7 },
49142 	{ "MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST", 0x3738c, 0 },
49150 		{ "HSEL", 0, 4 },
49151 	{ "MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST", 0x37390, 0 },
49156 		{ "ACCRD", 0, 8 },
49157 	{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER", 0x37398, 0 },
49165 		{ "LCURR", 0, 5 },
49166 	{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3739c, 0 },
49172 		{ "SDLVL", 0, 5 },
49173 	{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x373a0, 0 },
49182 		{ "RX_LINKANLGSW", 0, 7 },
49183 	{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x373a4, 0 },
49187 		{ "INTDAC", 0, 6 },
49188 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x373a8, 0 },
49192 		{ "MINAMP", 0, 5 },
49193 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x373ac, 0 },
49199 		{ "EMEN", 0, 1 },
49200 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x373b0, 0 },
49206 		{ "EMCEN", 0, 1 },
49207 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x373b4, 0 },
49210 		{ "APDF", 0, 12 },
49211 	{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x373b8, 0 },
49212 	{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3", 0x373bc, 0 },
49228 		{ "FPRBSOFF", 0, 1 },
49229 	{ "MAC_PORT_RX_LINKB_DFE_TAP_CONTROL", 0x373c0, 0 },
49230 	{ "MAC_PORT_RX_LINKB_DFE_TAP", 0x373c4, 0 },
49231 	{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2", 0x373e4, 0 },
49239 		{ "QCCCMP", 0, 1 },
49240 	{ "MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x373e8, 0 },
49243 		{ "CSVAL", 0, 3 },
49244 	{ "MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL", 0x373ec, 0 },
49253 		{ "DCDAMP", 0, 6 },
49254 	{ "MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL", 0x373f0, 0 },
49260 		{ "DCDAMP", 0, 6 },
49261 	{ "MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL", 0x373f4, 0 },
49269 		{ "QCDAMP", 0, 6 },
49270 	{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x373f8, 0 },
49277 		{ "ACJZNT", 0, 1 },
49278 	{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x373fc, 0 },
49289 		{ "MTHOLD", 0, 1 },
49290 	{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x37600, 0 },
49301 		{ "T5_RX_RTSEL", 0, 2 },
49302 	{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x37604, 0 },
49314 		{ "PATSEL", 0, 3 },
49315 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x37608, 0 },
49324 		{ "SSCEN", 0, 1 },
49325 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3760c, 0 },
49332 		{ "PHOFFS", 0, 6 },
49333 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x37610, 0 },
49335 		{ "ROTD", 0, 6 },
49336 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x37614, 0 },
49339 		{ "ROTE", 0, 6 },
49340 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37618, 0 },
49343 		{ "RAOFF", 0, 5 },
49344 	{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3761c, 0 },
49346 		{ "RDOFF", 0, 5 },
49347 	{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x37620, 0 },
49358 		{ "DFERST", 0, 1 },
49359 	{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x37624, 0 },
49361 		{ "T5BYTE0", 0, 8 },
49362 	{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x37628, 0 },
49369 		{ "T5_RX_ASAMP", 0, 3 },
49370 	{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3762c, 0 },
49374 		{ "VOFFA", 0, 6 },
49375 	{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x37630, 0 },
49383 		{ "T5VGAIN", 0, 7 },
49384 	{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x37634, 0 },
49389 		{ "AMAXT", 0, 7 },
49390 	{ "MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37638, 0 },
49392 		{ "PMOFFTIME", 0, 6 },
49393 	{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1", 0x3763c, 0 },
49396 		{ "IQAMP", 0, 5 },
49397 	{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2", 0x37640, 0 },
49398 	{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37644, 0 },
49405 		{ "DASEL", 0, 3 },
49406 	{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x37648, 0 },
49408 		{ "DACAP", 0, 8 },
49409 	{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN", 0x3764c, 0 },
49411 		{ "DACAM", 0, 8 },
49412 	{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x37650, 0 },
49414 		{ "ADAC1", 0, 8 },
49415 	{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL", 0x37654, 0 },
49421 		{ "FACCPL", 0, 1 },
49422 	{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE", 0x37658, 0 },
49425 		{ "ACCPLBIAS", 0, 8 },
49426 	{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET", 0x3765c, 0 },
49427 	{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37660, 0 },
49429 		{ "H1EX", 0, 6 },
49430 	{ "MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR", 0x37664, 0 },
49433 		{ "UNPKVGA", 0, 2 },
49434 	{ "MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH", 0x37668, 0 },
49443 		{ "CDRANLGSW", 0, 2 },
49444 	{ "MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3766c, 0 },
49446 …{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37670, 0 …
49457 		{ "OAE", 0, 4 },
49458 	{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x37674, 0 },
49463 		{ "ODEC", 0, 4 },
49464 	{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x37678, 0 },
49480 		{ "T5OCCMP", 0, 1 },
49481 	{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3767c, 0 },
49497 		{ "FADAC", 0, 1 },
49498 	{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x37680, 0 },
49514 		{ "FQCC", 0, 1 },
49515 	{ "MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL", 0x37684, 0 },
49520 		{ "LOFCH", 0, 5 },
49521 	{ "MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE", 0x37688, 0 },
49523 		{ "LOFL", 0, 7 },
49524 	{ "MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST", 0x3768c, 0 },
49532 		{ "HSEL", 0, 4 },
49533 	{ "MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST", 0x37690, 0 },
49538 		{ "ACCRD", 0, 8 },
49539 	{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER", 0x37698, 0 },
49547 		{ "LCURR", 0, 5 },
49548 	{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3769c, 0 },
49554 		{ "SDLVL", 0, 5 },
49555 	{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x376a0, 0 },
49564 		{ "RX_LINKANLGSW", 0, 7 },
49565 	{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x376a4, 0 },
49569 		{ "INTDAC", 0, 6 },
49570 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x376a8, 0 },
49574 		{ "MINAMP", 0, 5 },
49575 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x376ac, 0 },
49581 		{ "EMEN", 0, 1 },
49582 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x376b0, 0 },
49588 		{ "EMCEN", 0, 1 },
49589 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x376b4, 0 },
49592 		{ "APDF", 0, 12 },
49593 	{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x376b8, 0 },
49594 	{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3", 0x376bc, 0 },
49610 		{ "FPRBSOFF", 0, 1 },
49611 	{ "MAC_PORT_RX_LINKC_DFE_TAP_CONTROL", 0x376c0, 0 },
49612 	{ "MAC_PORT_RX_LINKC_DFE_TAP", 0x376c4, 0 },
49613 	{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2", 0x376e4, 0 },
49621 		{ "QCCCMP", 0, 1 },
49622 	{ "MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x376e8, 0 },
49625 		{ "CSVAL", 0, 3 },
49626 	{ "MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL", 0x376ec, 0 },
49635 		{ "DCDAMP", 0, 6 },
49636 	{ "MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL", 0x376f0, 0 },
49642 		{ "DCDAMP", 0, 6 },
49643 	{ "MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL", 0x376f4, 0 },
49651 		{ "QCDAMP", 0, 6 },
49652 	{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x376f8, 0 },
49659 		{ "ACJZNT", 0, 1 },
49660 	{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x376fc, 0 },
49671 		{ "MTHOLD", 0, 1 },
49672 	{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x37700, 0 },
49683 		{ "T5_RX_RTSEL", 0, 2 },
49684 	{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x37704, 0 },
49696 		{ "PATSEL", 0, 3 },
49697 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x37708, 0 },
49706 		{ "SSCEN", 0, 1 },
49707 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3770c, 0 },
49714 		{ "PHOFFS", 0, 6 },
49715 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x37710, 0 },
49717 		{ "ROTD", 0, 6 },
49718 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x37714, 0 },
49721 		{ "ROTE", 0, 6 },
49722 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37718, 0 },
49725 		{ "RAOFF", 0, 5 },
49726 	{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3771c, 0 },
49728 		{ "RDOFF", 0, 5 },
49729 	{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x37720, 0 },
49740 		{ "DFERST", 0, 1 },
49741 	{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x37724, 0 },
49743 		{ "T5BYTE0", 0, 8 },
49744 	{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x37728, 0 },
49751 		{ "T5_RX_ASAMP", 0, 3 },
49752 	{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3772c, 0 },
49756 		{ "VOFFA", 0, 6 },
49757 	{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x37730, 0 },
49765 		{ "T5VGAIN", 0, 7 },
49766 	{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x37734, 0 },
49771 		{ "AMAXT", 0, 7 },
49772 	{ "MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37738, 0 },
49774 		{ "PMOFFTIME", 0, 6 },
49775 	{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1", 0x3773c, 0 },
49778 		{ "IQAMP", 0, 5 },
49779 	{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2", 0x37740, 0 },
49780 	{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37744, 0 },
49787 		{ "DASEL", 0, 3 },
49788 	{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x37748, 0 },
49790 		{ "DACAP", 0, 8 },
49791 	{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN", 0x3774c, 0 },
49793 		{ "DACAM", 0, 8 },
49794 	{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x37750, 0 },
49796 		{ "ADAC1", 0, 8 },
49797 	{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL", 0x37754, 0 },
49803 		{ "FACCPL", 0, 1 },
49804 	{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE", 0x37758, 0 },
49807 		{ "ACCPLBIAS", 0, 8 },
49808 	{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET", 0x3775c, 0 },
49809 	{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37760, 0 },
49811 		{ "H1EX", 0, 6 },
49812 	{ "MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR", 0x37764, 0 },
49815 		{ "UNPKVGA", 0, 2 },
49816 	{ "MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH", 0x37768, 0 },
49825 		{ "CDRANLGSW", 0, 2 },
49826 	{ "MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3776c, 0 },
49828 …{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37770, 0 …
49839 		{ "OAE", 0, 4 },
49840 	{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x37774, 0 },
49845 		{ "ODEC", 0, 4 },
49846 	{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x37778, 0 },
49862 		{ "T5OCCMP", 0, 1 },
49863 	{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3777c, 0 },
49879 		{ "FADAC", 0, 1 },
49880 	{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x37780, 0 },
49896 		{ "FQCC", 0, 1 },
49897 	{ "MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL", 0x37784, 0 },
49902 		{ "LOFCH", 0, 5 },
49903 	{ "MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE", 0x37788, 0 },
49905 		{ "LOFL", 0, 7 },
49906 	{ "MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST", 0x3778c, 0 },
49914 		{ "HSEL", 0, 4 },
49915 	{ "MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST", 0x37790, 0 },
49920 		{ "ACCRD", 0, 8 },
49921 	{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER", 0x37798, 0 },
49929 		{ "LCURR", 0, 5 },
49930 	{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3779c, 0 },
49936 		{ "SDLVL", 0, 5 },
49937 	{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x377a0, 0 },
49946 		{ "RX_LINKANLGSW", 0, 7 },
49947 	{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x377a4, 0 },
49951 		{ "INTDAC", 0, 6 },
49952 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x377a8, 0 },
49956 		{ "MINAMP", 0, 5 },
49957 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x377ac, 0 },
49963 		{ "EMEN", 0, 1 },
49964 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x377b0, 0 },
49970 		{ "EMCEN", 0, 1 },
49971 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x377b4, 0 },
49974 		{ "APDF", 0, 12 },
49975 	{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x377b8, 0 },
49976 	{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3", 0x377bc, 0 },
49992 		{ "FPRBSOFF", 0, 1 },
49993 	{ "MAC_PORT_RX_LINKD_DFE_TAP_CONTROL", 0x377c0, 0 },
49994 	{ "MAC_PORT_RX_LINKD_DFE_TAP", 0x377c4, 0 },
49995 	{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2", 0x377e4, 0 },
50003 		{ "QCCCMP", 0, 1 },
50004 	{ "MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x377e8, 0 },
50007 		{ "CSVAL", 0, 3 },
50008 	{ "MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL", 0x377ec, 0 },
50017 		{ "DCDAMP", 0, 6 },
50018 	{ "MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL", 0x377f0, 0 },
50024 		{ "DCDAMP", 0, 6 },
50025 	{ "MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL", 0x377f4, 0 },
50033 		{ "QCDAMP", 0, 6 },
50034 	{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x377f8, 0 },
50041 		{ "ACJZNT", 0, 1 },
50042 	{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x377fc, 0 },
50053 		{ "MTHOLD", 0, 1 },
50054 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x37a00, 0 },
50065 		{ "T5_RX_RTSEL", 0, 2 },
50066 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x37a04, 0 },
50078 		{ "PATSEL", 0, 3 },
50079 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x37a08, 0 },
50088 		{ "SSCEN", 0, 1 },
50089 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x37a0c, 0 },
50096 		{ "PHOFFS", 0, 6 },
50097 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x37a10, 0 },
50099 		{ "ROTD", 0, 6 },
50100 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x37a14, 0 },
50103 		{ "ROTE", 0, 6 },
50104 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37a18, 0 },
50107 		{ "RAOFF", 0, 5 },
50108 	{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x37a1c, 0 },
50110 		{ "RDOFF", 0, 5 },
50111 	{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x37a20, 0 },
50122 		{ "DFERST", 0, 1 },
50123 	{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x37a24, 0 },
50125 		{ "T5BYTE0", 0, 8 },
50126 	{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x37a28, 0 },
50133 		{ "T5_RX_ASAMP", 0, 3 },
50134 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x37a2c, 0 },
50138 		{ "VOFFA", 0, 6 },
50139 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x37a30, 0 },
50147 		{ "T5VGAIN", 0, 7 },
50148 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x37a34, 0 },
50153 		{ "AMAXT", 0, 7 },
50154 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37a38, 0 },
50156 		{ "PMOFFTIME", 0, 6 },
50157 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1", 0x37a3c, 0 },
50160 		{ "IQAMP", 0, 5 },
50161 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2", 0x37a40, 0 },
50162 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37a44, 0 },
50169 		{ "DASEL", 0, 3 },
50170 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x37a48, 0 },
50172 		{ "DACAP", 0, 8 },
50173 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN", 0x37a4c, 0 },
50175 		{ "DACAM", 0, 8 },
50176 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x37a50, 0 },
50178 		{ "ADAC1", 0, 8 },
50179 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL", 0x37a54, 0 },
50185 		{ "FACCPL", 0, 1 },
50186 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE", 0x37a58, 0 },
50189 		{ "ACCPLBIAS", 0, 8 },
50190 	{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET", 0x37a5c, 0 },
50191 	{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37a60, 0 },
50193 		{ "H1EX", 0, 6 },
50194 	{ "MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR", 0x37a64, 0 },
50197 		{ "UNPKVGA", 0, 2 },
50198 	{ "MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH", 0x37a68, 0 },
50207 		{ "CDRANLGSW", 0, 2 },
50208 	{ "MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x37a6c, 0 },
50210 …C_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37a70, 0 },
50221 		{ "OAE", 0, 4 },
50222 	{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x37a74, 0 },
50227 		{ "ODEC", 0, 4 },
50228 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x37a78, 0 },
50244 		{ "T5OCCMP", 0, 1 },
50245 	{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x37a7c, 0 },
50261 		{ "FADAC", 0, 1 },
50262 	{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x37a80, 0 },
50278 		{ "FQCC", 0, 1 },
50279 	{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL", 0x37a84, 0 },
50284 		{ "LOFCH", 0, 5 },
50285 	{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE", 0x37a88, 0 },
50287 		{ "LOFL", 0, 7 },
50288 	{ "MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST", 0x37a8c, 0 },
50296 		{ "HSEL", 0, 4 },
50297 	{ "MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST", 0x37a90, 0 },
50302 		{ "ACCRD", 0, 8 },
50303 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER", 0x37a98, 0 },
50311 		{ "LCURR", 0, 5 },
50312 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x37a9c, 0 },
50318 		{ "SDLVL", 0, 5 },
50319 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x37aa0, 0 },
50328 		{ "RX_LINKANLGSW", 0, 7 },
50329 	{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x37aa4, 0 },
50333 		{ "INTDAC", 0, 6 },
50334 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x37aa8, 0 },
50338 		{ "MINAMP", 0, 5 },
50339 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x37aac, 0 },
50345 		{ "EMEN", 0, 1 },
50346 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x37ab0, 0 },
50352 		{ "EMCEN", 0, 1 },
50353 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x37ab4, 0 },
50356 		{ "APDF", 0, 12 },
50357 	{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x37ab8, 0 },
50358 	{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3", 0x37abc, 0 },
50374 		{ "FPRBSOFF", 0, 1 },
50375 	{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL", 0x37ac0, 0 },
50376 	{ "MAC_PORT_RX_LINK_BCST_DFE_TAP", 0x37ac4, 0 },
50377 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2", 0x37ae4, 0 },
50385 		{ "QCCCMP", 0, 1 },
50386 	{ "MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x37ae8, 0 },
50389 		{ "CSVAL", 0, 3 },
50390 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL", 0x37aec, 0 },
50399 		{ "DCDAMP", 0, 6 },
50400 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL", 0x37af0, 0 },
50406 		{ "DCDAMP", 0, 6 },
50407 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL", 0x37af4, 0 },
50415 		{ "QCDAMP", 0, 6 },
50416 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x37af8, 0 },
50423 		{ "ACJZNT", 0, 1 },
50424 	{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x37afc, 0 },
50435 		{ "MTHOLD", 0, 1 },
50440 	{ "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x47000, 0 },
50442 	{ "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x47004, 0 },
50444 	{ "MC_DDRPHY_PC_RANK_PAIR0", 0x47008, 0 },
50452 		{ "RANK_PAIR1_SEC_V", 0, 1 },
50453 	{ "MC_DDRPHY_PC_RANK_PAIR1", 0x4700c, 0 },
50461 		{ "RANK_PAIR3_SEC_V", 0, 1 },
50462 	{ "MC_DDRPHY_PC_BASE_CNTR0", 0x47010, 0 },
50463 	{ "MC_DDRPHY_PC_RELOAD_VALUE0", 0x47014, 0 },
50465 		{ "PERIODIC_RELOAD_VALUE0", 0, 15 },
50466 	{ "MC_DDRPHY_PC_BASE_CNTR1", 0x47018, 0 },
50467 	{ "MC_DDRPHY_PC_CAL_TIMER", 0x4701c, 0 },
50468 	{ "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x47020, 0 },
50469 	{ "MC_DDRPHY_PC_ZCAL_TIMER", 0x47024, 0 },
50470 	{ "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x47028, 0 },
50471 	{ "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4702c, 0 },
50482 	{ "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4703c, 0 },
50486 	{ "MC_DDRPHY_PC_CONFIG0", 0x47030, 0 },
50495 	{ "MC_DDRPHY_PC_CONFIG1", 0x47034, 0 },
50503 	{ "MC_DDRPHY_PC_RESETS", 0x47038, 0 },
50506 	{ "MC_DDRPHY_PC_ERROR_STATUS0", 0x47048, 0 },
50513 	{ "MC_DDRPHY_PC_ERROR_MASK0", 0x4704c, 0 },
50520 	{ "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x47050, 0 },
50525 	{ "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x47054, 0 },
50532 		{ "ANALOG_PD_DIV", 0, 2 },
50533 	{ "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x47058, 0 },
50546 		{ "ENA_RANK_PAIR", 0, 4 },
50547 	{ "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4705c, 0 },
50551 		{ "REFRESH_INTERVAL", 0, 7 },
50552 	{ "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x47060, 0 },
50564 		{ "ERROR_RANK_PAIR", 0, 4 },
50565 	{ "MC_DDRPHY_PC_INIT_CAL_MASK", 0x47068, 0 },
50577 	{ "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x47064, 0 },
50580 	{ "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4706c, 0 },
50583 	{ "MC_DDRPHY_PC_MR0_PRI_RP", 0x47070, 0 },
50584 	{ "MC_DDRPHY_PC_MR1_PRI_RP", 0x47074, 0 },
50585 	{ "MC_DDRPHY_PC_MR2_PRI_RP", 0x47078, 0 },
50586 	{ "MC_DDRPHY_PC_MR3_PRI_RP", 0x4707c, 0 },
50587 	{ "MC_DDRPHY_PC_MR0_SEC_RP", 0x47080, 0 },
50588 	{ "MC_DDRPHY_PC_MR1_SEC_RP", 0x47084, 0 },
50589 	{ "MC_DDRPHY_PC_MR2_SEC_RP", 0x47088, 0 },
50590 	{ "MC_DDRPHY_PC_MR3_SEC_RP", 0x4708c, 0 },
50591 	{ "MC_DDRPHY_PC_RANK_GROUP", 0x47044, 0 },
50606 		{ "ADDR_MIRROR_BG0_BG1", 0, 1 },
50607 	{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45800, 0 },
50609 		{ "BIT_ENABLE_12_15", 0, 4 },
50610 	{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45804, 0 },
50619 	{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x45810, 0 },
50621 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50622 	{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x45814, 0 },
50624 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50625 	{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x45818, 0 },
50627 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50628 	{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x4581c, 0 },
50630 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50631 	{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x45820, 0 },
50633 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50634 	{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x45824, 0 },
50636 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50637 	{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x45828, 0 },
50639 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50640 	{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x4582c, 0 },
50642 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50643 	{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45830, 0 },
50651 		{ "ADR_TEST_CHECK_EN", 0, 1 },
50652 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45840, 0 },
50655 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45844, 0 },
50658 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45848, 0 },
50661 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4584c, 0 },
50664 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45850, 0 },
50667 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45854, 0 },
50670 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45858, 0 },
50673 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4585c, 0 },
50676 	{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45880, 0 },
50684 		{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
50685 	{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45884, 0 },
50693 		{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
50694 	{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45860, 0 },
50695 	{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x458a0, 0 },
50696 	{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x458a4, 0 },
50697 	{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45868, 0 },
50701 		{ "SLEW_CTL3", 0, 4 },
50702 	{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x458a8, 0 },
50710 		{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
50711 	{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x458ac, 0 },
50719 		{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
50720 	{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x458b0, 0 },
50722 		{ "ADR_LANE_12_15_PD", 0, 4 },
50723 	{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45a00, 0 },
50725 		{ "BIT_ENABLE_12_15", 0, 4 },
50726 	{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45a04, 0 },
50735 	{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x45a10, 0 },
50737 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50738 	{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x45a14, 0 },
50740 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50741 	{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x45a18, 0 },
50743 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50744 	{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x45a1c, 0 },
50746 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50747 	{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x45a20, 0 },
50749 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50750 	{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x45a24, 0 },
50752 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50753 	{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x45a28, 0 },
50755 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50756 	{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x45a2c, 0 },
50758 		{ "ADR_DELAY_BITS9_15", 0, 7 },
50759 	{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45a30, 0 },
50767 		{ "ADR_TEST_CHECK_EN", 0, 1 },
50768 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45a40, 0 },
50771 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45a44, 0 },
50774 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45a48, 0 },
50777 	{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x45a4c, 0 },
50780 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45a50, 0 },
50783 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45a54, 0 },
50786 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45a58, 0 },
50789 	{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x45a5c, 0 },
50792 	{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45a80, 0 },
50800 		{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
50801 	{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45a84, 0 },
50809 		{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
50810 	{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45a60, 0 },
50811 	{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x45aa0, 0 },
50812 	{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x45aa4, 0 },
50813 	{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45a68, 0 },
50817 		{ "SLEW_CTL3", 0, 4 },
50818 	{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x45aa8, 0 },
50826 		{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
50827 	{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x45aac, 0 },
50835 		{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
50836 	{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x45ab0, 0 },
50838 		{ "ADR_LANE_12_15_PD", 0, 4 },
50839 	{ "MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0", 0x460c0, 0 },
50844 		{ "PLL_PLLXTR_0_1", 0, 2 },
50845 	{ "MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1", 0x460c4, 0 },
50853 		{ "ANALOG_WRAPON", 0, 1 },
50854 	{ "MC_DDRPHY_AD32S_SYSCLK_CNTL_PR", 0x460c8, 0 },
50863 		{ "CE0DLTVCC", 0, 2 },
50864 	{ "MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x460cc, 0 },
50866 	{ "MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO", 0x460d0, 0 },
50872 		{ "SLEW_CNTL", 0, 4 },
50873 	{ "MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL", 0x460d4, 0 },
50881 		{ "ATEST1CTL3", 0, 1 },
50882 	{ "MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0", 0x460d8, 0 },
50883 	{ "MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1", 0x460dc, 0 },
50884 	{ "MC_DDRPHY_AD32S_POWERDOWN_1", 0x460e0, 0 },
50892 		{ "DVCC_REG_PD", 0, 1 },
50893 	{ "MC_DDRPHY_AD32S_SLEW_CAL_CNTL", 0x460e4, 0 },
50898 		{ "SLEW_TARGET_PR_OFFSET", 0, 5 },
50899 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44000, 0 },
50900 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44004, 0 },
50909 		{ "MRS_CMD_DATA_N3", 0, 1 },
50910 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x441f0, 0 },
50911 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x441f4, 0 },
50913 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44008, 0 },
50914 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4400c, 0 },
50923 		{ "ATEST_MUX_CTL3", 0, 1 },
50924 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44010, 0 },
50939 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44014, 0 },
50955 		{ "QUAD3_CLK18_BIT15", 0, 1 },
50956 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x441f8, 0 },
50960 		{ "DQ_WR_OFFSET_N3", 0, 4 },
50961 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44018, 0 },
50967 		{ "READ_CENTERING_MODE", 0, 2 },
50968 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4401c, 0 },
50977 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x441cc, 0 },
50980 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4417c, 0 },
50982 		{ "PASS_FAIL_VALUE", 0, 8 },
50983 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44178, 0 },
50998 		{ "QUAD0_CAVEAT", 0, 1 },
50999 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44058, 0 },
51007 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4407c, 0 },
51008 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x441d0, 0 },
51010 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x440c0, 0 },
51012 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
51013 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x440c4, 0 },
51015 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
51016 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44024, 0 },
51024 		{ "RDCLK_SELECT3", 0, 2 },
51025 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44170, 0 },
51027 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
51028 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44174, 0 },
51030 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
51031 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x440e0, 0 },
51033 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x440e4, 0 },
51035 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x440e8, 0 },
51037 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x440ec, 0 },
51039 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x440f0, 0 },
51041 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x440f4, 0 },
51043 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x440f8, 0 },
51045 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x440fc, 0 },
51047 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44100, 0 },
51049 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44104, 0 },
51051 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44108, 0 },
51053 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4410c, 0 },
51055 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44110, 0 },
51057 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44114, 0 },
51059 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44118, 0 },
51061 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4411c, 0 },
51063 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44120, 0 },
51065 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44124, 0 },
51067 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44128, 0 },
51069 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4412c, 0 },
51071 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44130, 0 },
51073 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44134, 0 },
51075 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44138, 0 },
51077 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4413c, 0 },
51079 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44140, 0 },
51082 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44144, 0 },
51085 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44148, 0 },
51088 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4414c, 0 },
51091 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44150, 0 },
51094 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44154, 0 },
51097 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44158, 0 },
51100 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4415c, 0 },
51103 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44160, 0 },
51106 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44164, 0 },
51109 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44168, 0 },
51112 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4416c, 0 },
51115 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44030, 0 },
51117 		{ "OFFSET_BITS9_15", 0, 7 },
51118 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44034, 0 },
51120 		{ "OFFSET_BITS9_15", 0, 7 },
51121 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x441c0, 0 },
51123 		{ "REFERENCE_BITS9_15", 0, 7 },
51124 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x441c4, 0 },
51126 		{ "REFERENCE_BITS9_15", 0, 7 },
51127 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x441c8, 0 },
51129 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44180, 0 },
51131 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51132 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44184, 0 },
51134 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51135 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44188, 0 },
51137 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51138 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4418c, 0 },
51140 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51141 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44190, 0 },
51143 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51144 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44194, 0 },
51146 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51147 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44198, 0 },
51149 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51150 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4419c, 0 },
51152 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51153 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x441a0, 0 },
51155 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51156 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x441a4, 0 },
51158 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51159 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x441a8, 0 },
51161 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51162 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x441ac, 0 },
51164 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51165 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44028, 0 },
51167 		{ "MAX_DQS_DRIFT", 0, 6 },
51168 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44038, 0 },
51169 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4403c, 0 },
51171 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44040, 0 },
51172 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44044, 0 },
51174 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4404c, 0 },
51178 		{ "DQS_GATE_DELAY_N3", 0, 3 },
51179 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44050, 0 },
51195 		{ "MIN_EYE", 0, 1 },
51196 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44054, 0 },
51212 		{ "MIN_EYE_MASK", 0, 1 },
51213 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4405c, 0 },
51222 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44060, 0 },
51230 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44064, 0 },
51232 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44068, 0 },
51234 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4406c, 0 },
51246 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44070, 0 },
51260 		{ "ADVANCE_PR_VALUE", 0, 1 },
51261 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x441d8, 0 },
51266 		{ "PLL_PLLXTR_0_1", 0, 2 },
51267 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x441dc, 0 },
51278 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x441e0, 0 },
51281 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x441e8, 0 },
51284 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x441e4, 0 },
51287 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x441ec, 0 },
51290 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x441d4, 0 },
51294 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44074, 0 },
51298 		{ "DP18_DFT_ERROR", 0, 6 },
51299 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44020, 0 },
51305 		{ "DIGITAL_EYE_VALUE", 0, 8 },
51306 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x440c8, 0 },
51314 		{ "MEMINTD07_POS", 0, 2 },
51315 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x440cc, 0 },
51323 		{ "MEMINTD15_POS", 0, 2 },
51324 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x440d0, 0 },
51332 		{ "MEMINTD23_POS", 0, 2 },
51333 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44078, 0 },
51335 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
51336 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x440d4, 0 },
51340 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
51341 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x440d8, 0 },
51349 		{ "MAX_DQS_ITER", 0, 1 },
51350 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x441b4, 0 },
51352 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
51353 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x441b8, 0 },
51355 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x440dc, 0 },
51357 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4402c, 0 },
51361 		{ "WR_DEBUG_SEL", 0, 3 },
51362 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x441fc, 0 },
51373 		{ "VCC_REG_PD", 0, 1 },
51374 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44048, 0 },
51377 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x441bc, 0 },
51381 		{ "QUAD3_PWR_CTL", 0, 4 },
51382 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44200, 0 },
51383 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44204, 0 },
51392 		{ "MRS_CMD_DATA_N3", 0, 1 },
51393 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x443f0, 0 },
51394 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x443f4, 0 },
51396 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44208, 0 },
51397 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4420c, 0 },
51406 		{ "ATEST_MUX_CTL3", 0, 1 },
51407 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44210, 0 },
51422 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44214, 0 },
51438 		{ "QUAD3_CLK18_BIT15", 0, 1 },
51439 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x443f8, 0 },
51443 		{ "DQ_WR_OFFSET_N3", 0, 4 },
51444 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44218, 0 },
51450 		{ "READ_CENTERING_MODE", 0, 2 },
51451 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4421c, 0 },
51460 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x443cc, 0 },
51463 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4437c, 0 },
51465 		{ "PASS_FAIL_VALUE", 0, 8 },
51466 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44378, 0 },
51481 		{ "QUAD0_CAVEAT", 0, 1 },
51482 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44258, 0 },
51490 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4427c, 0 },
51491 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x443d0, 0 },
51493 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x442c0, 0 },
51495 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
51496 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x442c4, 0 },
51498 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
51499 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44224, 0 },
51507 		{ "RDCLK_SELECT3", 0, 2 },
51508 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44370, 0 },
51510 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
51511 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44374, 0 },
51513 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
51514 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x442e0, 0 },
51516 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x442e4, 0 },
51518 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x442e8, 0 },
51520 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x442ec, 0 },
51522 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x442f0, 0 },
51524 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x442f4, 0 },
51526 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x442f8, 0 },
51528 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x442fc, 0 },
51530 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44300, 0 },
51532 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44304, 0 },
51534 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44308, 0 },
51536 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4430c, 0 },
51538 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44310, 0 },
51540 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44314, 0 },
51542 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44318, 0 },
51544 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4431c, 0 },
51546 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44320, 0 },
51548 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44324, 0 },
51550 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44328, 0 },
51552 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4432c, 0 },
51554 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44330, 0 },
51556 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44334, 0 },
51558 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44338, 0 },
51560 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4433c, 0 },
51562 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44340, 0 },
51565 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44344, 0 },
51568 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44348, 0 },
51571 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4434c, 0 },
51574 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44350, 0 },
51577 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44354, 0 },
51580 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44358, 0 },
51583 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4435c, 0 },
51586 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44360, 0 },
51589 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44364, 0 },
51592 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44368, 0 },
51595 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4436c, 0 },
51598 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44230, 0 },
51600 		{ "OFFSET_BITS9_15", 0, 7 },
51601 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44234, 0 },
51603 		{ "OFFSET_BITS9_15", 0, 7 },
51604 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x443c0, 0 },
51606 		{ "REFERENCE_BITS9_15", 0, 7 },
51607 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x443c4, 0 },
51609 		{ "REFERENCE_BITS9_15", 0, 7 },
51610 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x443c8, 0 },
51612 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44380, 0 },
51614 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51615 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44384, 0 },
51617 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51618 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44388, 0 },
51620 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51621 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4438c, 0 },
51623 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51624 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44390, 0 },
51626 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51627 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44394, 0 },
51629 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51630 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44398, 0 },
51632 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51633 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4439c, 0 },
51635 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51636 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x443a0, 0 },
51638 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51639 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x443a4, 0 },
51641 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51642 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x443a8, 0 },
51644 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51645 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x443ac, 0 },
51647 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
51648 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44228, 0 },
51650 		{ "MAX_DQS_DRIFT", 0, 6 },
51651 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44238, 0 },
51652 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4423c, 0 },
51654 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44240, 0 },
51655 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44244, 0 },
51657 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4424c, 0 },
51661 		{ "DQS_GATE_DELAY_N3", 0, 3 },
51662 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44250, 0 },
51678 		{ "MIN_EYE", 0, 1 },
51679 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44254, 0 },
51695 		{ "MIN_EYE_MASK", 0, 1 },
51696 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4425c, 0 },
51705 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44260, 0 },
51713 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44264, 0 },
51715 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44268, 0 },
51717 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4426c, 0 },
51729 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44270, 0 },
51743 		{ "ADVANCE_PR_VALUE", 0, 1 },
51744 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x443d8, 0 },
51749 		{ "PLL_PLLXTR_0_1", 0, 2 },
51750 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x443dc, 0 },
51761 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x443e0, 0 },
51764 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x443e8, 0 },
51767 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x443e4, 0 },
51770 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x443ec, 0 },
51773 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x443d4, 0 },
51777 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44274, 0 },
51781 		{ "DP18_DFT_ERROR", 0, 6 },
51782 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44220, 0 },
51788 		{ "DIGITAL_EYE_VALUE", 0, 8 },
51789 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x442c8, 0 },
51797 		{ "MEMINTD07_POS", 0, 2 },
51798 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x442cc, 0 },
51806 		{ "MEMINTD15_POS", 0, 2 },
51807 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x442d0, 0 },
51815 		{ "MEMINTD23_POS", 0, 2 },
51816 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44278, 0 },
51818 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
51819 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x442d4, 0 },
51823 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
51824 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x442d8, 0 },
51832 		{ "MAX_DQS_ITER", 0, 1 },
51833 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x443b4, 0 },
51835 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
51836 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x443b8, 0 },
51838 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x442dc, 0 },
51840 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4422c, 0 },
51844 		{ "WR_DEBUG_SEL", 0, 3 },
51845 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x443fc, 0 },
51856 		{ "VCC_REG_PD", 0, 1 },
51857 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44248, 0 },
51860 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x443bc, 0 },
51864 		{ "QUAD3_PWR_CTL", 0, 4 },
51865 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44400, 0 },
51866 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44404, 0 },
51875 		{ "MRS_CMD_DATA_N3", 0, 1 },
51876 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x445f0, 0 },
51877 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x445f4, 0 },
51879 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44408, 0 },
51880 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4440c, 0 },
51889 		{ "ATEST_MUX_CTL3", 0, 1 },
51890 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44410, 0 },
51905 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44414, 0 },
51921 		{ "QUAD3_CLK18_BIT15", 0, 1 },
51922 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x445f8, 0 },
51926 		{ "DQ_WR_OFFSET_N3", 0, 4 },
51927 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44418, 0 },
51933 		{ "READ_CENTERING_MODE", 0, 2 },
51934 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4441c, 0 },
51943 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x445cc, 0 },
51946 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4457c, 0 },
51948 		{ "PASS_FAIL_VALUE", 0, 8 },
51949 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44578, 0 },
51964 		{ "QUAD0_CAVEAT", 0, 1 },
51965 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44458, 0 },
51973 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4447c, 0 },
51974 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x445d0, 0 },
51976 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x444c0, 0 },
51978 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
51979 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x444c4, 0 },
51981 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
51982 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44424, 0 },
51990 		{ "RDCLK_SELECT3", 0, 2 },
51991 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44570, 0 },
51993 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
51994 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44574, 0 },
51996 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
51997 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x444e0, 0 },
51999 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x444e4, 0 },
52001 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x444e8, 0 },
52003 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x444ec, 0 },
52005 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x444f0, 0 },
52007 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x444f4, 0 },
52009 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x444f8, 0 },
52011 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x444fc, 0 },
52013 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44500, 0 },
52015 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44504, 0 },
52017 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44508, 0 },
52019 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4450c, 0 },
52021 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44510, 0 },
52023 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44514, 0 },
52025 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44518, 0 },
52027 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4451c, 0 },
52029 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44520, 0 },
52031 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44524, 0 },
52033 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44528, 0 },
52035 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4452c, 0 },
52037 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44530, 0 },
52039 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44534, 0 },
52041 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44538, 0 },
52043 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4453c, 0 },
52045 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44540, 0 },
52048 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44544, 0 },
52051 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44548, 0 },
52054 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4454c, 0 },
52057 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44550, 0 },
52060 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44554, 0 },
52063 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44558, 0 },
52066 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4455c, 0 },
52069 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44560, 0 },
52072 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44564, 0 },
52075 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44568, 0 },
52078 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4456c, 0 },
52081 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44430, 0 },
52083 		{ "OFFSET_BITS9_15", 0, 7 },
52084 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44434, 0 },
52086 		{ "OFFSET_BITS9_15", 0, 7 },
52087 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x445c0, 0 },
52089 		{ "REFERENCE_BITS9_15", 0, 7 },
52090 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x445c4, 0 },
52092 		{ "REFERENCE_BITS9_15", 0, 7 },
52093 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x445c8, 0 },
52095 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44580, 0 },
52097 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52098 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44584, 0 },
52100 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52101 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44588, 0 },
52103 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52104 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4458c, 0 },
52106 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52107 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44590, 0 },
52109 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52110 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44594, 0 },
52112 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52113 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44598, 0 },
52115 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52116 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4459c, 0 },
52118 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52119 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x445a0, 0 },
52121 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52122 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x445a4, 0 },
52124 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52125 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x445a8, 0 },
52127 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52128 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x445ac, 0 },
52130 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52131 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44428, 0 },
52133 		{ "MAX_DQS_DRIFT", 0, 6 },
52134 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44438, 0 },
52135 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4443c, 0 },
52137 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44440, 0 },
52138 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44444, 0 },
52140 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4444c, 0 },
52144 		{ "DQS_GATE_DELAY_N3", 0, 3 },
52145 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44450, 0 },
52161 		{ "MIN_EYE", 0, 1 },
52162 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44454, 0 },
52178 		{ "MIN_EYE_MASK", 0, 1 },
52179 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4445c, 0 },
52188 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44460, 0 },
52196 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44464, 0 },
52198 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44468, 0 },
52200 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4446c, 0 },
52212 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44470, 0 },
52226 		{ "ADVANCE_PR_VALUE", 0, 1 },
52227 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x445d8, 0 },
52232 		{ "PLL_PLLXTR_0_1", 0, 2 },
52233 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x445dc, 0 },
52244 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x445e0, 0 },
52247 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x445e8, 0 },
52250 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x445e4, 0 },
52253 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x445ec, 0 },
52256 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x445d4, 0 },
52260 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44474, 0 },
52264 		{ "DP18_DFT_ERROR", 0, 6 },
52265 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44420, 0 },
52271 		{ "DIGITAL_EYE_VALUE", 0, 8 },
52272 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x444c8, 0 },
52280 		{ "MEMINTD07_POS", 0, 2 },
52281 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x444cc, 0 },
52289 		{ "MEMINTD15_POS", 0, 2 },
52290 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x444d0, 0 },
52298 		{ "MEMINTD23_POS", 0, 2 },
52299 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44478, 0 },
52301 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
52302 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x444d4, 0 },
52306 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
52307 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x444d8, 0 },
52315 		{ "MAX_DQS_ITER", 0, 1 },
52316 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x445b4, 0 },
52318 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
52319 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x445b8, 0 },
52321 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x444dc, 0 },
52323 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4442c, 0 },
52327 		{ "WR_DEBUG_SEL", 0, 3 },
52328 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x445fc, 0 },
52339 		{ "VCC_REG_PD", 0, 1 },
52340 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44448, 0 },
52343 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x445bc, 0 },
52347 		{ "QUAD3_PWR_CTL", 0, 4 },
52348 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44600, 0 },
52349 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44604, 0 },
52358 		{ "MRS_CMD_DATA_N3", 0, 1 },
52359 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x447f0, 0 },
52360 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x447f4, 0 },
52362 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44608, 0 },
52363 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4460c, 0 },
52372 		{ "ATEST_MUX_CTL3", 0, 1 },
52373 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44610, 0 },
52388 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44614, 0 },
52404 		{ "QUAD3_CLK18_BIT15", 0, 1 },
52405 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x447f8, 0 },
52409 		{ "DQ_WR_OFFSET_N3", 0, 4 },
52410 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44618, 0 },
52416 		{ "READ_CENTERING_MODE", 0, 2 },
52417 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4461c, 0 },
52426 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x447cc, 0 },
52429 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4477c, 0 },
52431 		{ "PASS_FAIL_VALUE", 0, 8 },
52432 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44778, 0 },
52447 		{ "QUAD0_CAVEAT", 0, 1 },
52448 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44658, 0 },
52456 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4467c, 0 },
52457 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x447d0, 0 },
52459 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x446c0, 0 },
52461 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
52462 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x446c4, 0 },
52464 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
52465 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44624, 0 },
52473 		{ "RDCLK_SELECT3", 0, 2 },
52474 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44770, 0 },
52476 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
52477 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44774, 0 },
52479 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
52480 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x446e0, 0 },
52482 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x446e4, 0 },
52484 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x446e8, 0 },
52486 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x446ec, 0 },
52488 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x446f0, 0 },
52490 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x446f4, 0 },
52492 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x446f8, 0 },
52494 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x446fc, 0 },
52496 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44700, 0 },
52498 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44704, 0 },
52500 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44708, 0 },
52502 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4470c, 0 },
52504 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44710, 0 },
52506 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44714, 0 },
52508 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44718, 0 },
52510 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4471c, 0 },
52512 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44720, 0 },
52514 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44724, 0 },
52516 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44728, 0 },
52518 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4472c, 0 },
52520 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44730, 0 },
52522 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44734, 0 },
52524 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44738, 0 },
52526 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4473c, 0 },
52528 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44740, 0 },
52531 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44744, 0 },
52534 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44748, 0 },
52537 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4474c, 0 },
52540 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44750, 0 },
52543 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44754, 0 },
52546 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44758, 0 },
52549 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4475c, 0 },
52552 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44760, 0 },
52555 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44764, 0 },
52558 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44768, 0 },
52561 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4476c, 0 },
52564 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44630, 0 },
52566 		{ "OFFSET_BITS9_15", 0, 7 },
52567 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44634, 0 },
52569 		{ "OFFSET_BITS9_15", 0, 7 },
52570 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x447c0, 0 },
52572 		{ "REFERENCE_BITS9_15", 0, 7 },
52573 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x447c4, 0 },
52575 		{ "REFERENCE_BITS9_15", 0, 7 },
52576 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x447c8, 0 },
52578 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44780, 0 },
52580 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52581 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44784, 0 },
52583 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52584 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44788, 0 },
52586 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52587 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4478c, 0 },
52589 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52590 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44790, 0 },
52592 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52593 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44794, 0 },
52595 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52596 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44798, 0 },
52598 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52599 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4479c, 0 },
52601 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52602 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x447a0, 0 },
52604 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52605 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x447a4, 0 },
52607 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52608 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x447a8, 0 },
52610 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52611 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x447ac, 0 },
52613 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
52614 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44628, 0 },
52616 		{ "MAX_DQS_DRIFT", 0, 6 },
52617 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44638, 0 },
52618 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4463c, 0 },
52620 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44640, 0 },
52621 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44644, 0 },
52623 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4464c, 0 },
52627 		{ "DQS_GATE_DELAY_N3", 0, 3 },
52628 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44650, 0 },
52644 		{ "MIN_EYE", 0, 1 },
52645 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44654, 0 },
52661 		{ "MIN_EYE_MASK", 0, 1 },
52662 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4465c, 0 },
52671 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44660, 0 },
52679 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44664, 0 },
52681 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44668, 0 },
52683 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4466c, 0 },
52695 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44670, 0 },
52709 		{ "ADVANCE_PR_VALUE", 0, 1 },
52710 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x447d8, 0 },
52715 		{ "PLL_PLLXTR_0_1", 0, 2 },
52716 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x447dc, 0 },
52727 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x447e0, 0 },
52730 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x447e8, 0 },
52733 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x447e4, 0 },
52736 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x447ec, 0 },
52739 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x447d4, 0 },
52743 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44674, 0 },
52747 		{ "DP18_DFT_ERROR", 0, 6 },
52748 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44620, 0 },
52754 		{ "DIGITAL_EYE_VALUE", 0, 8 },
52755 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x446c8, 0 },
52763 		{ "MEMINTD07_POS", 0, 2 },
52764 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x446cc, 0 },
52772 		{ "MEMINTD15_POS", 0, 2 },
52773 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x446d0, 0 },
52781 		{ "MEMINTD23_POS", 0, 2 },
52782 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44678, 0 },
52784 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
52785 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x446d4, 0 },
52789 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
52790 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x446d8, 0 },
52798 		{ "MAX_DQS_ITER", 0, 1 },
52799 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x447b4, 0 },
52801 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
52802 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x447b8, 0 },
52804 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x446dc, 0 },
52806 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4462c, 0 },
52810 		{ "WR_DEBUG_SEL", 0, 3 },
52811 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x447fc, 0 },
52822 		{ "VCC_REG_PD", 0, 1 },
52823 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44648, 0 },
52826 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x447bc, 0 },
52830 		{ "QUAD3_PWR_CTL", 0, 4 },
52831 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44800, 0 },
52832 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44804, 0 },
52841 		{ "MRS_CMD_DATA_N3", 0, 1 },
52842 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x449f0, 0 },
52843 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x449f4, 0 },
52845 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44808, 0 },
52846 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4480c, 0 },
52855 		{ "ATEST_MUX_CTL3", 0, 1 },
52856 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44810, 0 },
52871 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44814, 0 },
52887 		{ "QUAD3_CLK18_BIT15", 0, 1 },
52888 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x449f8, 0 },
52892 		{ "DQ_WR_OFFSET_N3", 0, 4 },
52893 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44818, 0 },
52899 		{ "READ_CENTERING_MODE", 0, 2 },
52900 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4481c, 0 },
52909 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x449cc, 0 },
52912 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4497c, 0 },
52914 		{ "PASS_FAIL_VALUE", 0, 8 },
52915 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44978, 0 },
52930 		{ "QUAD0_CAVEAT", 0, 1 },
52931 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44858, 0 },
52939 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4487c, 0 },
52940 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x449d0, 0 },
52942 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x448c0, 0 },
52944 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
52945 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x448c4, 0 },
52947 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
52948 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44824, 0 },
52956 		{ "RDCLK_SELECT3", 0, 2 },
52957 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44970, 0 },
52959 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
52960 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44974, 0 },
52962 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
52963 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x448e0, 0 },
52965 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x448e4, 0 },
52967 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x448e8, 0 },
52969 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x448ec, 0 },
52971 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x448f0, 0 },
52973 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x448f4, 0 },
52975 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x448f8, 0 },
52977 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x448fc, 0 },
52979 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44900, 0 },
52981 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44904, 0 },
52983 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44908, 0 },
52985 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4490c, 0 },
52987 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44910, 0 },
52989 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44914, 0 },
52991 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44918, 0 },
52993 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4491c, 0 },
52995 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44920, 0 },
52997 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44924, 0 },
52999 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44928, 0 },
53001 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4492c, 0 },
53003 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44930, 0 },
53005 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44934, 0 },
53007 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44938, 0 },
53009 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4493c, 0 },
53011 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44940, 0 },
53014 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44944, 0 },
53017 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44948, 0 },
53020 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4494c, 0 },
53023 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44950, 0 },
53026 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44954, 0 },
53029 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44958, 0 },
53032 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4495c, 0 },
53035 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44960, 0 },
53038 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44964, 0 },
53041 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44968, 0 },
53044 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4496c, 0 },
53047 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44830, 0 },
53049 		{ "OFFSET_BITS9_15", 0, 7 },
53050 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44834, 0 },
53052 		{ "OFFSET_BITS9_15", 0, 7 },
53053 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x449c0, 0 },
53055 		{ "REFERENCE_BITS9_15", 0, 7 },
53056 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x449c4, 0 },
53058 		{ "REFERENCE_BITS9_15", 0, 7 },
53059 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x449c8, 0 },
53061 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44980, 0 },
53063 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53064 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44984, 0 },
53066 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53067 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44988, 0 },
53069 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53070 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4498c, 0 },
53072 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53073 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44990, 0 },
53075 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53076 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44994, 0 },
53078 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53079 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44998, 0 },
53081 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53082 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4499c, 0 },
53084 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53085 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x449a0, 0 },
53087 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53088 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x449a4, 0 },
53090 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53091 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x449a8, 0 },
53093 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53094 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x449ac, 0 },
53096 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53097 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44828, 0 },
53099 		{ "MAX_DQS_DRIFT", 0, 6 },
53100 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44838, 0 },
53101 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4483c, 0 },
53103 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44840, 0 },
53104 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44844, 0 },
53106 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4484c, 0 },
53110 		{ "DQS_GATE_DELAY_N3", 0, 3 },
53111 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44850, 0 },
53127 		{ "MIN_EYE", 0, 1 },
53128 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44854, 0 },
53144 		{ "MIN_EYE_MASK", 0, 1 },
53145 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4485c, 0 },
53154 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44860, 0 },
53162 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44864, 0 },
53164 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44868, 0 },
53166 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4486c, 0 },
53178 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44870, 0 },
53192 		{ "ADVANCE_PR_VALUE", 0, 1 },
53193 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x449d8, 0 },
53198 		{ "PLL_PLLXTR_0_1", 0, 2 },
53199 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x449dc, 0 },
53210 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x449e0, 0 },
53213 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x449e8, 0 },
53216 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x449e4, 0 },
53219 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x449ec, 0 },
53222 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x449d4, 0 },
53226 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44874, 0 },
53230 		{ "DP18_DFT_ERROR", 0, 6 },
53231 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44820, 0 },
53237 		{ "DIGITAL_EYE_VALUE", 0, 8 },
53238 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x448c8, 0 },
53246 		{ "MEMINTD07_POS", 0, 2 },
53247 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x448cc, 0 },
53255 		{ "MEMINTD15_POS", 0, 2 },
53256 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x448d0, 0 },
53264 		{ "MEMINTD23_POS", 0, 2 },
53265 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44878, 0 },
53267 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
53268 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x448d4, 0 },
53272 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
53273 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x448d8, 0 },
53281 		{ "MAX_DQS_ITER", 0, 1 },
53282 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x449b4, 0 },
53284 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
53285 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x449b8, 0 },
53287 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x448dc, 0 },
53289 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4482c, 0 },
53293 		{ "WR_DEBUG_SEL", 0, 3 },
53294 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x449fc, 0 },
53305 		{ "VCC_REG_PD", 0, 1 },
53306 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44848, 0 },
53309 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x449bc, 0 },
53313 		{ "QUAD3_PWR_CTL", 0, 4 },
53314 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44a00, 0 },
53315 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44a04, 0 },
53324 		{ "MRS_CMD_DATA_N3", 0, 1 },
53325 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44bf0, 0 },
53326 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44bf4, 0 },
53328 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44a08, 0 },
53329 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44a0c, 0 },
53338 		{ "ATEST_MUX_CTL3", 0, 1 },
53339 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44a10, 0 },
53354 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44a14, 0 },
53370 		{ "QUAD3_CLK18_BIT15", 0, 1 },
53371 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44bf8, 0 },
53375 		{ "DQ_WR_OFFSET_N3", 0, 4 },
53376 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44a18, 0 },
53382 		{ "READ_CENTERING_MODE", 0, 2 },
53383 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x44a1c, 0 },
53392 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44bcc, 0 },
53395 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44b7c, 0 },
53397 		{ "PASS_FAIL_VALUE", 0, 8 },
53398 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44b78, 0 },
53413 		{ "QUAD0_CAVEAT", 0, 1 },
53414 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44a58, 0 },
53422 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44a7c, 0 },
53423 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x44bd0, 0 },
53425 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44ac0, 0 },
53427 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
53428 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44ac4, 0 },
53430 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
53431 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44a24, 0 },
53439 		{ "RDCLK_SELECT3", 0, 2 },
53440 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44b70, 0 },
53442 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
53443 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44b74, 0 },
53445 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
53446 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ae0, 0 },
53448 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ae4, 0 },
53450 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ae8, 0 },
53452 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44aec, 0 },
53454 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44af0, 0 },
53456 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44af4, 0 },
53458 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44af8, 0 },
53460 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44afc, 0 },
53462 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44b00, 0 },
53464 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44b04, 0 },
53466 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44b08, 0 },
53468 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44b0c, 0 },
53470 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44b10, 0 },
53472 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44b14, 0 },
53474 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44b18, 0 },
53476 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44b1c, 0 },
53478 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44b20, 0 },
53480 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44b24, 0 },
53482 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44b28, 0 },
53484 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44b2c, 0 },
53486 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44b30, 0 },
53488 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44b34, 0 },
53490 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44b38, 0 },
53492 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44b3c, 0 },
53494 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44b40, 0 },
53497 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44b44, 0 },
53500 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44b48, 0 },
53503 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44b4c, 0 },
53506 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44b50, 0 },
53509 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44b54, 0 },
53512 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44b58, 0 },
53515 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44b5c, 0 },
53518 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44b60, 0 },
53521 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44b64, 0 },
53524 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44b68, 0 },
53527 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44b6c, 0 },
53530 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44a30, 0 },
53532 		{ "OFFSET_BITS9_15", 0, 7 },
53533 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44a34, 0 },
53535 		{ "OFFSET_BITS9_15", 0, 7 },
53536 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44bc0, 0 },
53538 		{ "REFERENCE_BITS9_15", 0, 7 },
53539 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44bc4, 0 },
53541 		{ "REFERENCE_BITS9_15", 0, 7 },
53542 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44bc8, 0 },
53544 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44b80, 0 },
53546 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53547 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44b84, 0 },
53549 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53550 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44b88, 0 },
53552 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53553 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44b8c, 0 },
53555 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53556 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44b90, 0 },
53558 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53559 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44b94, 0 },
53561 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53562 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44b98, 0 },
53564 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53565 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44b9c, 0 },
53567 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53568 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44ba0, 0 },
53570 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53571 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44ba4, 0 },
53573 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53574 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44ba8, 0 },
53576 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53577 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44bac, 0 },
53579 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
53580 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44a28, 0 },
53582 		{ "MAX_DQS_DRIFT", 0, 6 },
53583 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44a38, 0 },
53584 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44a3c, 0 },
53586 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44a40, 0 },
53587 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44a44, 0 },
53589 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44a4c, 0 },
53593 		{ "DQS_GATE_DELAY_N3", 0, 3 },
53594 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44a50, 0 },
53610 		{ "MIN_EYE", 0, 1 },
53611 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44a54, 0 },
53627 		{ "MIN_EYE_MASK", 0, 1 },
53628 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44a5c, 0 },
53637 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44a60, 0 },
53645 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44a64, 0 },
53647 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44a68, 0 },
53649 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x44a6c, 0 },
53661 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44a70, 0 },
53675 		{ "ADVANCE_PR_VALUE", 0, 1 },
53676 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44bd8, 0 },
53681 		{ "PLL_PLLXTR_0_1", 0, 2 },
53682 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44bdc, 0 },
53693 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44be0, 0 },
53696 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44be8, 0 },
53699 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44be4, 0 },
53702 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44bec, 0 },
53705 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44bd4, 0 },
53709 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44a74, 0 },
53713 		{ "DP18_DFT_ERROR", 0, 6 },
53714 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44a20, 0 },
53720 		{ "DIGITAL_EYE_VALUE", 0, 8 },
53721 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44ac8, 0 },
53729 		{ "MEMINTD07_POS", 0, 2 },
53730 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44acc, 0 },
53738 		{ "MEMINTD15_POS", 0, 2 },
53739 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44ad0, 0 },
53747 		{ "MEMINTD23_POS", 0, 2 },
53748 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44a78, 0 },
53750 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
53751 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44ad4, 0 },
53755 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
53756 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44ad8, 0 },
53764 		{ "MAX_DQS_ITER", 0, 1 },
53765 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44bb4, 0 },
53767 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
53768 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44bb8, 0 },
53770 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44adc, 0 },
53772 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x44a2c, 0 },
53776 		{ "WR_DEBUG_SEL", 0, 3 },
53777 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x44bfc, 0 },
53788 		{ "VCC_REG_PD", 0, 1 },
53789 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44a48, 0 },
53792 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44bbc, 0 },
53796 		{ "QUAD3_PWR_CTL", 0, 4 },
53797 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44c00, 0 },
53798 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44c04, 0 },
53807 		{ "MRS_CMD_DATA_N3", 0, 1 },
53808 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44df0, 0 },
53809 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44df4, 0 },
53811 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44c08, 0 },
53812 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44c0c, 0 },
53821 		{ "ATEST_MUX_CTL3", 0, 1 },
53822 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44c10, 0 },
53837 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44c14, 0 },
53853 		{ "QUAD3_CLK18_BIT15", 0, 1 },
53854 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44df8, 0 },
53858 		{ "DQ_WR_OFFSET_N3", 0, 4 },
53859 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44c18, 0 },
53865 		{ "READ_CENTERING_MODE", 0, 2 },
53866 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x44c1c, 0 },
53875 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44dcc, 0 },
53878 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44d7c, 0 },
53880 		{ "PASS_FAIL_VALUE", 0, 8 },
53881 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44d78, 0 },
53896 		{ "QUAD0_CAVEAT", 0, 1 },
53897 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44c58, 0 },
53905 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44c7c, 0 },
53906 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x44dd0, 0 },
53908 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44cc0, 0 },
53910 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
53911 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44cc4, 0 },
53913 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
53914 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44c24, 0 },
53922 		{ "RDCLK_SELECT3", 0, 2 },
53923 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44d70, 0 },
53925 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
53926 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44d74, 0 },
53928 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
53929 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ce0, 0 },
53931 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ce4, 0 },
53933 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ce8, 0 },
53935 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44cec, 0 },
53937 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44cf0, 0 },
53939 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44cf4, 0 },
53941 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44cf8, 0 },
53943 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44cfc, 0 },
53945 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44d00, 0 },
53947 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44d04, 0 },
53949 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44d08, 0 },
53951 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44d0c, 0 },
53953 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44d10, 0 },
53955 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44d14, 0 },
53957 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44d18, 0 },
53959 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44d1c, 0 },
53961 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44d20, 0 },
53963 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44d24, 0 },
53965 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44d28, 0 },
53967 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44d2c, 0 },
53969 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44d30, 0 },
53971 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44d34, 0 },
53973 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44d38, 0 },
53975 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44d3c, 0 },
53977 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44d40, 0 },
53980 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44d44, 0 },
53983 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44d48, 0 },
53986 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44d4c, 0 },
53989 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44d50, 0 },
53992 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44d54, 0 },
53995 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44d58, 0 },
53998 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44d5c, 0 },
54001 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44d60, 0 },
54004 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44d64, 0 },
54007 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44d68, 0 },
54010 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44d6c, 0 },
54013 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44c30, 0 },
54015 		{ "OFFSET_BITS9_15", 0, 7 },
54016 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44c34, 0 },
54018 		{ "OFFSET_BITS9_15", 0, 7 },
54019 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44dc0, 0 },
54021 		{ "REFERENCE_BITS9_15", 0, 7 },
54022 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44dc4, 0 },
54024 		{ "REFERENCE_BITS9_15", 0, 7 },
54025 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44dc8, 0 },
54027 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44d80, 0 },
54029 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54030 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44d84, 0 },
54032 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54033 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44d88, 0 },
54035 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54036 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44d8c, 0 },
54038 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54039 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44d90, 0 },
54041 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54042 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44d94, 0 },
54044 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54045 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44d98, 0 },
54047 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54048 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44d9c, 0 },
54050 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54051 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44da0, 0 },
54053 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54054 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44da4, 0 },
54056 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54057 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44da8, 0 },
54059 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54060 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44dac, 0 },
54062 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54063 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44c28, 0 },
54065 		{ "MAX_DQS_DRIFT", 0, 6 },
54066 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44c38, 0 },
54067 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44c3c, 0 },
54069 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44c40, 0 },
54070 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44c44, 0 },
54072 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44c4c, 0 },
54076 		{ "DQS_GATE_DELAY_N3", 0, 3 },
54077 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44c50, 0 },
54093 		{ "MIN_EYE", 0, 1 },
54094 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44c54, 0 },
54110 		{ "MIN_EYE_MASK", 0, 1 },
54111 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44c5c, 0 },
54120 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44c60, 0 },
54128 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44c64, 0 },
54130 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44c68, 0 },
54132 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x44c6c, 0 },
54144 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44c70, 0 },
54158 		{ "ADVANCE_PR_VALUE", 0, 1 },
54159 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44dd8, 0 },
54164 		{ "PLL_PLLXTR_0_1", 0, 2 },
54165 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44ddc, 0 },
54176 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44de0, 0 },
54179 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44de8, 0 },
54182 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44de4, 0 },
54185 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44dec, 0 },
54188 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44dd4, 0 },
54192 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44c74, 0 },
54196 		{ "DP18_DFT_ERROR", 0, 6 },
54197 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44c20, 0 },
54203 		{ "DIGITAL_EYE_VALUE", 0, 8 },
54204 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44cc8, 0 },
54212 		{ "MEMINTD07_POS", 0, 2 },
54213 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44ccc, 0 },
54221 		{ "MEMINTD15_POS", 0, 2 },
54222 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44cd0, 0 },
54230 		{ "MEMINTD23_POS", 0, 2 },
54231 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44c78, 0 },
54233 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
54234 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44cd4, 0 },
54238 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
54239 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44cd8, 0 },
54247 		{ "MAX_DQS_ITER", 0, 1 },
54248 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44db4, 0 },
54250 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
54251 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44db8, 0 },
54253 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44cdc, 0 },
54255 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x44c2c, 0 },
54259 		{ "WR_DEBUG_SEL", 0, 3 },
54260 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x44dfc, 0 },
54271 		{ "VCC_REG_PD", 0, 1 },
54272 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44c48, 0 },
54275 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44dbc, 0 },
54279 		{ "QUAD3_PWR_CTL", 0, 4 },
54280 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44e00, 0 },
54281 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44e04, 0 },
54290 		{ "MRS_CMD_DATA_N3", 0, 1 },
54291 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44ff0, 0 },
54292 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44ff4, 0 },
54294 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44e08, 0 },
54295 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44e0c, 0 },
54304 		{ "ATEST_MUX_CTL3", 0, 1 },
54305 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44e10, 0 },
54320 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44e14, 0 },
54336 		{ "QUAD3_CLK18_BIT15", 0, 1 },
54337 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44ff8, 0 },
54341 		{ "DQ_WR_OFFSET_N3", 0, 4 },
54342 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44e18, 0 },
54348 		{ "READ_CENTERING_MODE", 0, 2 },
54349 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x44e1c, 0 },
54358 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44fcc, 0 },
54361 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44f7c, 0 },
54363 		{ "PASS_FAIL_VALUE", 0, 8 },
54364 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44f78, 0 },
54379 		{ "QUAD0_CAVEAT", 0, 1 },
54380 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44e58, 0 },
54388 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44e7c, 0 },
54389 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x44fd0, 0 },
54391 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44ec0, 0 },
54393 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
54394 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44ec4, 0 },
54396 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
54397 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44e24, 0 },
54405 		{ "RDCLK_SELECT3", 0, 2 },
54406 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44f70, 0 },
54408 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
54409 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44f74, 0 },
54411 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
54412 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ee0, 0 },
54414 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ee4, 0 },
54416 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ee8, 0 },
54418 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44eec, 0 },
54420 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44ef0, 0 },
54422 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44ef4, 0 },
54424 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44ef8, 0 },
54426 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44efc, 0 },
54428 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44f00, 0 },
54430 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44f04, 0 },
54432 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44f08, 0 },
54434 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44f0c, 0 },
54436 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44f10, 0 },
54438 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44f14, 0 },
54440 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44f18, 0 },
54442 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44f1c, 0 },
54444 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44f20, 0 },
54446 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44f24, 0 },
54448 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44f28, 0 },
54450 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44f2c, 0 },
54452 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44f30, 0 },
54454 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44f34, 0 },
54456 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44f38, 0 },
54458 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44f3c, 0 },
54460 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44f40, 0 },
54463 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44f44, 0 },
54466 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44f48, 0 },
54469 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44f4c, 0 },
54472 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44f50, 0 },
54475 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44f54, 0 },
54478 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44f58, 0 },
54481 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44f5c, 0 },
54484 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44f60, 0 },
54487 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44f64, 0 },
54490 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44f68, 0 },
54493 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44f6c, 0 },
54496 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44e30, 0 },
54498 		{ "OFFSET_BITS9_15", 0, 7 },
54499 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44e34, 0 },
54501 		{ "OFFSET_BITS9_15", 0, 7 },
54502 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44fc0, 0 },
54504 		{ "REFERENCE_BITS9_15", 0, 7 },
54505 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44fc4, 0 },
54507 		{ "REFERENCE_BITS9_15", 0, 7 },
54508 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44fc8, 0 },
54510 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44f80, 0 },
54512 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54513 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44f84, 0 },
54515 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54516 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44f88, 0 },
54518 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54519 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44f8c, 0 },
54521 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54522 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44f90, 0 },
54524 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54525 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44f94, 0 },
54527 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54528 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44f98, 0 },
54530 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54531 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44f9c, 0 },
54533 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54534 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44fa0, 0 },
54536 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54537 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44fa4, 0 },
54539 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54540 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44fa8, 0 },
54542 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54543 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44fac, 0 },
54545 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54546 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44e28, 0 },
54548 		{ "MAX_DQS_DRIFT", 0, 6 },
54549 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44e38, 0 },
54550 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44e3c, 0 },
54552 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44e40, 0 },
54553 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44e44, 0 },
54555 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44e4c, 0 },
54559 		{ "DQS_GATE_DELAY_N3", 0, 3 },
54560 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44e50, 0 },
54576 		{ "MIN_EYE", 0, 1 },
54577 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44e54, 0 },
54593 		{ "MIN_EYE_MASK", 0, 1 },
54594 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44e5c, 0 },
54603 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44e60, 0 },
54611 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44e64, 0 },
54613 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44e68, 0 },
54615 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x44e6c, 0 },
54627 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44e70, 0 },
54641 		{ "ADVANCE_PR_VALUE", 0, 1 },
54642 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44fd8, 0 },
54647 		{ "PLL_PLLXTR_0_1", 0, 2 },
54648 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44fdc, 0 },
54659 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44fe0, 0 },
54662 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44fe8, 0 },
54665 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44fe4, 0 },
54668 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44fec, 0 },
54671 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44fd4, 0 },
54675 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44e74, 0 },
54679 		{ "DP18_DFT_ERROR", 0, 6 },
54680 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44e20, 0 },
54686 		{ "DIGITAL_EYE_VALUE", 0, 8 },
54687 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44ec8, 0 },
54695 		{ "MEMINTD07_POS", 0, 2 },
54696 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44ecc, 0 },
54704 		{ "MEMINTD15_POS", 0, 2 },
54705 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44ed0, 0 },
54713 		{ "MEMINTD23_POS", 0, 2 },
54714 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44e78, 0 },
54716 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
54717 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44ed4, 0 },
54721 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
54722 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44ed8, 0 },
54730 		{ "MAX_DQS_ITER", 0, 1 },
54731 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44fb4, 0 },
54733 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
54734 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44fb8, 0 },
54736 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44edc, 0 },
54738 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x44e2c, 0 },
54742 		{ "WR_DEBUG_SEL", 0, 3 },
54743 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x44ffc, 0 },
54754 		{ "VCC_REG_PD", 0, 1 },
54755 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44e48, 0 },
54758 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44fbc, 0 },
54762 		{ "QUAD3_PWR_CTL", 0, 4 },
54763 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x45000, 0 },
54764 	{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x45004, 0 },
54773 		{ "MRS_CMD_DATA_N3", 0, 1 },
54774 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x451f0, 0 },
54775 	{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x451f4, 0 },
54777 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x45008, 0 },
54778 	{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4500c, 0 },
54787 		{ "ATEST_MUX_CTL3", 0, 1 },
54788 	{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x45010, 0 },
54803 	{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x45014, 0 },
54819 		{ "QUAD3_CLK18_BIT15", 0, 1 },
54820 	{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x451f8, 0 },
54824 		{ "DQ_WR_OFFSET_N3", 0, 4 },
54825 	{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x45018, 0 },
54831 		{ "READ_CENTERING_MODE", 0, 2 },
54832 	{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4501c, 0 },
54841 	{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x451cc, 0 },
54844 	{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4517c, 0 },
54846 		{ "PASS_FAIL_VALUE", 0, 8 },
54847 	{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x45178, 0 },
54862 		{ "QUAD0_CAVEAT", 0, 1 },
54863 	{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x45058, 0 },
54871 	{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4507c, 0 },
54872 	{ "MC_DDRPHY_DP18_WRCLK_PR", 0x451d0, 0 },
54874 	{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x450c0, 0 },
54876 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
54877 	{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x450c4, 0 },
54879 		{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
54880 	{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x45024, 0 },
54888 		{ "RDCLK_SELECT3", 0, 2 },
54889 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x45170, 0 },
54891 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
54892 	{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x45174, 0 },
54894 		{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
54895 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x450e0, 0 },
54897 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x450e4, 0 },
54899 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x450e8, 0 },
54901 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x450ec, 0 },
54903 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x450f0, 0 },
54905 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x450f4, 0 },
54907 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x450f8, 0 },
54909 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x450fc, 0 },
54911 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x45100, 0 },
54913 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x45104, 0 },
54915 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x45108, 0 },
54917 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4510c, 0 },
54919 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x45110, 0 },
54921 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x45114, 0 },
54923 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x45118, 0 },
54925 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4511c, 0 },
54927 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x45120, 0 },
54929 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x45124, 0 },
54931 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x45128, 0 },
54933 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4512c, 0 },
54935 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x45130, 0 },
54937 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x45134, 0 },
54939 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x45138, 0 },
54941 	{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4513c, 0 },
54943 	{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x45140, 0 },
54946 	{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x45144, 0 },
54949 	{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x45148, 0 },
54952 	{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4514c, 0 },
54955 	{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x45150, 0 },
54958 	{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x45154, 0 },
54961 	{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x45158, 0 },
54964 	{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4515c, 0 },
54967 	{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x45160, 0 },
54970 	{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x45164, 0 },
54973 	{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x45168, 0 },
54976 	{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4516c, 0 },
54979 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x45030, 0 },
54981 		{ "OFFSET_BITS9_15", 0, 7 },
54982 	{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x45034, 0 },
54984 		{ "OFFSET_BITS9_15", 0, 7 },
54985 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x451c0, 0 },
54987 		{ "REFERENCE_BITS9_15", 0, 7 },
54988 	{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x451c4, 0 },
54990 		{ "REFERENCE_BITS9_15", 0, 7 },
54991 	{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x451c8, 0 },
54993 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x45180, 0 },
54995 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54996 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x45184, 0 },
54998 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
54999 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x45188, 0 },
55001 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55002 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4518c, 0 },
55004 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55005 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x45190, 0 },
55007 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55008 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x45194, 0 },
55010 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55011 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x45198, 0 },
55013 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55014 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4519c, 0 },
55016 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55017 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x451a0, 0 },
55019 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55020 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x451a4, 0 },
55022 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55023 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x451a8, 0 },
55025 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55026 	{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x451ac, 0 },
55028 		{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
55029 	{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x45028, 0 },
55031 		{ "MAX_DQS_DRIFT", 0, 6 },
55032 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x45038, 0 },
55033 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4503c, 0 },
55035 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x45040, 0 },
55036 	{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x45044, 0 },
55038 	{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4504c, 0 },
55042 		{ "DQS_GATE_DELAY_N3", 0, 3 },
55043 	{ "MC_DDRPHY_DP18_RD_STATUS0", 0x45050, 0 },
55059 		{ "MIN_EYE", 0, 1 },
55060 	{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x45054, 0 },
55076 		{ "MIN_EYE_MASK", 0, 1 },
55077 	{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4505c, 0 },
55086 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x45060, 0 },
55094 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x45064, 0 },
55096 	{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x45068, 0 },
55098 	{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4506c, 0 },
55110 	{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x45070, 0 },
55124 		{ "ADVANCE_PR_VALUE", 0, 1 },
55125 	{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x451d8, 0 },
55130 		{ "PLL_PLLXTR_0_1", 0, 2 },
55131 	{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x451dc, 0 },
55142 	{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x451e0, 0 },
55145 	{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x451e8, 0 },
55148 	{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x451e4, 0 },
55151 	{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x451ec, 0 },
55154 	{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x451d4, 0 },
55158 	{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x45074, 0 },
55162 		{ "DP18_DFT_ERROR", 0, 6 },
55163 	{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x45020, 0 },
55169 		{ "DIGITAL_EYE_VALUE", 0, 8 },
55170 	{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x450c8, 0 },
55178 		{ "MEMINTD07_POS", 0, 2 },
55179 	{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x450cc, 0 },
55187 		{ "MEMINTD15_POS", 0, 2 },
55188 	{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x450d0, 0 },
55196 		{ "MEMINTD23_POS", 0, 2 },
55197 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x45078, 0 },
55199 		{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
55200 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x450d4, 0 },
55204 		{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
55205 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x450d8, 0 },
55213 		{ "MAX_DQS_ITER", 0, 1 },
55214 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x451b4, 0 },
55216 		{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
55217 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x451b8, 0 },
55219 	{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x450dc, 0 },
55221 	{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4502c, 0 },
55225 		{ "WR_DEBUG_SEL", 0, 3 },
55226 	{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x451fc, 0 },
55237 		{ "VCC_REG_PD", 0, 1 },
55238 	{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x45048, 0 },
55241 	{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x451bc, 0 },
55245 		{ "QUAD3_PWR_CTL", 0, 4 },
55246 	{ "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x47200, 0 },
55247 	{ "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x47204, 0 },
55248 	{ "MC_DDRPHY_SEQ_CONFIG0", 0x47208, 0 },
55258 		{ "X16_DEVICE", 0, 1 },
55259 	{ "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4720c, 0 },
55260 	{ "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x47210, 0 },
55261 	{ "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x47214, 0 },
55262 	{ "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x47218, 0 },
55263 	{ "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4721c, 0 },
55264 	{ "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x47220, 0 },
55271 		{ "EARLY_REQ_SOURCE", 0, 3 },
55272 	{ "MC_DDRPHY_SEQ_ERROR_MASK0", 0x47224, 0 },
55276 	{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x47228, 0 },
55278 		{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
55279 	{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4722c, 0 },
55281 		{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
55282 	{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x47230, 0 },
55284 		{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
55285 	{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x47234, 0 },
55287 		{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
55288 	{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x47238, 0 },
55290 		{ "ODT_RD_VALUES_x2plus1", 0, 8 },
55291 	{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4723c, 0 },
55293 		{ "ODT_RD_VALUES_x2plus1", 0, 8 },
55294 	{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x47240, 0 },
55296 		{ "ODT_RD_VALUES_x2plus1", 0, 8 },
55297 	{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x47244, 0 },
55299 		{ "ODT_RD_VALUES_x2plus1", 0, 8 },
55300 	{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x47248, 0 },
55304 		{ "TRFC_CYCLES", 0, 4 },
55305 	{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4724c, 0 },
55309 		{ "TWRMRD_CYCLES", 0, 4 },
55310 	{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x47250, 0 },
55314 		{ "MRS_CMD_SPACE", 0, 4 },
55315 	{ "MC_DDRPHY_WC_CONFIG0", 0x47600, 0 },
55319 		{ "CUSTOM_INIT_WRITE", 0, 1 },
55320 	{ "MC_DDRPHY_WC_CONFIG1", 0x47604, 0 },
55324 	{ "MC_DDRPHY_WC_CONFIG2", 0x47608, 0 },
55328 		{ "EN_RESET_WR_DELAY_WL", 0, 1 },
55329 	{ "MC_DDRPHY_WC_CONFIG3", 0x47614, 0 },
55333 	{ "MC_DDRPHY_WC_WRCLK_CNTL", 0x47618, 0 },
55336 	{ "MC_DDRPHY_WC_ERROR_STATUS0", 0x4760c, 0 },
55338 	{ "MC_DDRPHY_WC_ERROR_MASK0", 0x47610, 0 },
55340 	{ "MC_DDRPHY_RC_CONFIG0", 0x47400, 0 },
55350 		{ "STAGGERED_PATTERN", 0, 1 },
55351 	{ "MC_DDRPHY_RC_CONFIG1", 0x47404, 0 },
55353 	{ "MC_DDRPHY_RC_CONFIG2", 0x47408, 0 },
55358 	{ "MC_DDRPHY_RC_CONFIG3", 0x4741c, 0 },
55363 	{ "MC_DDRPHY_RC_PERIODIC", 0x47420, 0 },
55364 	{ "MC_DDRPHY_RC_ERROR_STATUS0", 0x47414, 0 },
55366 	{ "MC_DDRPHY_RC_ERROR_MASK0", 0x47418, 0 },
55368 	{ "MC_DDRPHY_APB_CONFIG0", 0x47800, 0 },
55374 	{ "MC_DDRPHY_APB_ERROR_STATUS0", 0x47804, 0 },
55377 	{ "MC_DDRPHY_APB_ERROR_MASK0", 0x47808, 0 },
55380 	{ "MC_DDRPHY_APB_DP18_POPULATION", 0x4780c, 0 },
55396 	{ "MC_DDRPHY_APB_ADR_POPULATION", 0x47810, 0 },
55405 	{ "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x47814, 0 },
55407 	{ "MC_DDRPHY_APB_MTCTL_REG0", 0x47820, 0 },
55416 	{ "MC_DDRPHY_APB_MTCTL_REG1", 0x47824, 0 },
55420 	{ "MC_DDRPHY_APB_MTSTAT_REG0", 0x47828, 0 },
55421 	{ "MC_DDRPHY_APB_MTSTAT_REG1", 0x4782c, 0 },
55423 		{ "MT_DP18_PLL_LOCK_SUM", 0, 1 },
55424 	{ "MC_LMC_MCSTAT", 0x40040, 0 },
55430 	{ "MC_LMC_MCOPT1", 0x40080, 0 },
55452 		{ "CE_THRESHOLD", 0, 8 },
55453 	{ "MC_LMC_MCOPT2", 0x40084, 0 },
55468 	{ "MC_LMC_CFGR0", 0x40100, 0 },
55472 		{ "RANK_ENABLE", 0, 1 },
55473 	{ "MC_LMC_INITSEQ0", 0x40140, 0 },
55477 		{ "RANK", 0, 4 },
55478 	{ "MC_LMC_CMD0", 0x40144, 0 },
55483 		{ "ADDR", 0, 16 },
55484 	{ "MC_LMC_INITSEQ1", 0x40148, 0 },
55488 		{ "RANK", 0, 4 },
55489 	{ "MC_LMC_CMD1", 0x4014c, 0 },
55494 		{ "ADDR", 0, 16 },
55495 	{ "MC_LMC_INITSEQ2", 0x40150, 0 },
55499 		{ "RANK", 0, 4 },
55500 	{ "MC_LMC_CMD2", 0x40154, 0 },
55505 		{ "ADDR", 0, 16 },
55506 	{ "MC_LMC_INITSEQ3", 0x40158, 0 },
55510 		{ "RANK", 0, 4 },
55511 	{ "MC_LMC_CMD3", 0x4015c, 0 },
55516 		{ "ADDR", 0, 16 },
55517 	{ "MC_LMC_INITSEQ4", 0x40160, 0 },
55521 		{ "RANK", 0, 4 },
55522 	{ "MC_LMC_CMD4", 0x40164, 0 },
55527 		{ "ADDR", 0, 16 },
55528 	{ "MC_LMC_INITSEQ5", 0x40168, 0 },
55532 		{ "RANK", 0, 4 },
55533 	{ "MC_LMC_CMD5", 0x4016c, 0 },
55538 		{ "ADDR", 0, 16 },
55539 	{ "MC_LMC_INITSEQ6", 0x40170, 0 },
55543 		{ "RANK", 0, 4 },
55544 	{ "MC_LMC_CMD6", 0x40174, 0 },
55549 		{ "ADDR", 0, 16 },
55550 	{ "MC_LMC_INITSEQ7", 0x40178, 0 },
55554 		{ "RANK", 0, 4 },
55555 	{ "MC_LMC_CMD7", 0x4017c, 0 },
55560 		{ "ADDR", 0, 16 },
55561 	{ "MC_LMC_INITSEQ8", 0x40180, 0 },
55565 		{ "RANK", 0, 4 },
55566 	{ "MC_LMC_CMD8", 0x40184, 0 },
55571 		{ "ADDR", 0, 16 },
55572 	{ "MC_LMC_INITSEQ9", 0x40188, 0 },
55576 		{ "RANK", 0, 4 },
55577 	{ "MC_LMC_CMD9", 0x4018c, 0 },
55582 		{ "ADDR", 0, 16 },
55583 	{ "MC_LMC_INITSEQ10", 0x40190, 0 },
55587 		{ "RANK", 0, 4 },
55588 	{ "MC_LMC_CMD10", 0x40194, 0 },
55593 		{ "ADDR", 0, 16 },
55594 	{ "MC_LMC_INITSEQ11", 0x40198, 0 },
55598 		{ "RANK", 0, 4 },
55599 	{ "MC_LMC_CMD11", 0x4019c, 0 },
55604 		{ "ADDR", 0, 16 },
55605 	{ "MC_LMC_INITSEQ12", 0x401a0, 0 },
55609 		{ "RANK", 0, 4 },
55610 	{ "MC_LMC_CMD12", 0x401a4, 0 },
55615 		{ "ADDR", 0, 16 },
55616 	{ "MC_LMC_INITSEQ13", 0x401a8, 0 },
55620 		{ "RANK", 0, 4 },
55621 	{ "MC_LMC_CMD13", 0x401ac, 0 },
55626 		{ "ADDR", 0, 16 },
55627 	{ "MC_LMC_INITSEQ14", 0x401b0, 0 },
55631 		{ "RANK", 0, 4 },
55632 	{ "MC_LMC_CMD14", 0x401b4, 0 },
55637 		{ "ADDR", 0, 16 },
55638 	{ "MC_LMC_INITSEQ15", 0x401b8, 0 },
55642 		{ "RANK", 0, 4 },
55643 	{ "MC_LMC_CMD15", 0x401bc, 0 },
55648 		{ "ADDR", 0, 16 },
55649 	{ "MC_LMC_SDTR0", 0x40200, 0 },
55651 		{ "T_RFC_XPR", 0, 12 },
55652 	{ "MC_LMC_SDTR1", 0x40204, 0 },
55660 		{ "T_RTRO", 0, 4 },
55661 	{ "MC_LMC_SDTR2", 0x40208, 0 },
55669 		{ "T_RAS", 0, 6 },
55670 	{ "MC_LMC_SDTR3", 0x4020c, 0 },
55677 		{ "T_XSDLL", 0, 8 },
55678 	{ "MC_LMC_SDTR4", 0x40210, 0 },
55684 		{ "T_MOD", 0, 5 },
55685 	{ "MC_LMC_SDTR5", 0x40214, 0 },
55688 	{ "MC_LMC_DBG0", 0x40228, 0 },
55690 	{ "MC_LMC_SMR0", 0x40240, 0 },
55699 		{ "BL", 0, 2 },
55700 	{ "MC_LMC_SMR1", 0x40244, 0 },
55712 		{ "SMR1_DLL", 0, 1 },
55713 	{ "MC_LMC_SMR2", 0x40248, 0 },
55721 		{ "PASR", 0, 3 },
55722 	{ "MC_LMC_SMR3", 0x4024c, 0 },
55730 		{ "MPR_SEL", 0, 2 },
55731 	{ "MC_LMC_SMR4", 0x40250, 0 },
55742 		{ "SMR4_RFU", 0, 1 },
55743 	{ "MC_LMC_SMR5", 0x40254, 0 },
55751 		{ "PAR_LAT_MODE", 0, 3 },
55752 	{ "MC_LMC_SMR6", 0x40258, 0 },
55756 		{ "VREF_DQ_VALUE", 0, 6 },
55757 	{ "MC_LMC_ODTR0", 0x40280, 0 },
55760 	{ "MC_LMC_CALSTAT", 0x40304, 0 },
55763 	{ "MC_LMC_T_PHYUPD0", 0x40330, 0 },
55764 	{ "MC_LMC_T_PHYUPD1", 0x40334, 0 },
55765 	{ "MC_LMC_T_PHYUPD2", 0x40338, 0 },
55766 	{ "MC_LMC_T_PHYUPD3", 0x4033c, 0 },
55767 	{ "MC_P_DDRPHY_RST_CTRL", 0x41300, 0 },
55775 		{ "PHY_RST_N", 0, 1 },
55776 	{ "MC_P_PERFORMANCE_CTRL", 0x41304, 0 },
55786 		{ "RMW_PERF_CTRL", 0, 1 },
55787 	{ "MC_P_ECC_CTRL", 0x41308, 0 },
55789 		{ "ECC_DISABLE", 0, 1 },
55790 	{ "MC_P_PAR_ENABLE", 0x4130c, 0 },
55794 		{ "PERR_BLK_INT_ENABLE", 0, 1 },
55795 	{ "MC_P_PAR_CAUSE", 0x41310, 0 },
55799 		{ "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
55800 	{ "MC_P_INT_ENABLE", 0x41314, 0 },
55803 		{ "PERR_INT_ENABLE", 0, 1 },
55804 	{ "MC_P_INT_CAUSE", 0x41318, 0 },
55807 		{ "PERR_INT_CAUSE", 0, 1 },
55808 	{ "MC_P_ECC_STATUS", 0x4131c, 0 },
55810 		{ "ECC_UECNT", 0, 16 },
55811 	{ "MC_P_PHY_CTRL", 0x41320, 0 },
55812 	{ "MC_P_STATIC_CFG_STATUS", 0x41324, 0 },
55827 		{ "STATIC_SLOW", 0, 1 },
55828 	{ "MC_P_CORE_PCTL_STAT", 0x41328, 0 },
55829 	{ "MC_P_DEBUG_CNT", 0x4132c, 0 },
55831 		{ "RDATA_OCNT", 0, 5 },
55832 	{ "MC_CE_ERR_DATA_RDATA", 0x41330, 0 },
55833 	{ "MC_CE_ERR_DATA_RDATA", 0x41334, 0 },
55834 	{ "MC_CE_ERR_DATA_RDATA", 0x41338, 0 },
55835 	{ "MC_CE_ERR_DATA_RDATA", 0x4133c, 0 },
55836 	{ "MC_CE_ERR_DATA_RDATA", 0x41340, 0 },
55837 	{ "MC_CE_ERR_DATA_RDATA", 0x41344, 0 },
55838 	{ "MC_CE_ERR_DATA_RDATA", 0x41348, 0 },
55839 	{ "MC_CE_ERR_DATA_RDATA", 0x4134c, 0 },
55840 	{ "MC_CE_ERR_DATA_RDATA", 0x41350, 0 },
55841 	{ "MC_CE_ERR_DATA_RDATA", 0x41354, 0 },
55842 	{ "MC_CE_ERR_DATA_RDATA", 0x41358, 0 },
55843 	{ "MC_CE_ERR_DATA_RDATA", 0x4135c, 0 },
55844 	{ "MC_CE_ERR_DATA_RDATA", 0x41360, 0 },
55845 	{ "MC_CE_ERR_DATA_RDATA", 0x41364, 0 },
55846 	{ "MC_CE_ERR_DATA_RDATA", 0x41368, 0 },
55847 	{ "MC_CE_ERR_DATA_RDATA", 0x4136c, 0 },
55848 	{ "MC_UE_ERR_DATA_RDATA", 0x41370, 0 },
55849 	{ "MC_UE_ERR_DATA_RDATA", 0x41374, 0 },
55850 	{ "MC_UE_ERR_DATA_RDATA", 0x41378, 0 },
55851 	{ "MC_UE_ERR_DATA_RDATA", 0x4137c, 0 },
55852 	{ "MC_UE_ERR_DATA_RDATA", 0x41380, 0 },
55853 	{ "MC_UE_ERR_DATA_RDATA", 0x41384, 0 },
55854 	{ "MC_UE_ERR_DATA_RDATA", 0x41388, 0 },
55855 	{ "MC_UE_ERR_DATA_RDATA", 0x4138c, 0 },
55856 	{ "MC_UE_ERR_DATA_RDATA", 0x41390, 0 },
55857 	{ "MC_UE_ERR_DATA_RDATA", 0x41394, 0 },
55858 	{ "MC_UE_ERR_DATA_RDATA", 0x41398, 0 },
55859 	{ "MC_UE_ERR_DATA_RDATA", 0x4139c, 0 },
55860 	{ "MC_UE_ERR_DATA_RDATA", 0x413a0, 0 },
55861 	{ "MC_UE_ERR_DATA_RDATA", 0x413a4, 0 },
55862 	{ "MC_UE_ERR_DATA_RDATA", 0x413a8, 0 },
55863 	{ "MC_UE_ERR_DATA_RDATA", 0x413ac, 0 },
55864 	{ "MC_CE_ADDR", 0x413b0, 0 },
55865 	{ "MC_UE_ADDR", 0x413b4, 0 },
55866 	{ "MC_P_DEEP_SLEEP", 0x413b8, 0 },
55868 		{ "SleepReq", 0, 1 },
55869 	{ "MC_P_FPGA_BONUS", 0x413bc, 0 },
55870 	{ "MC_P_DEBUG_CFG", 0x413c0, 0 },
55876 		{ "DEBUGSELL", 0, 5 },
55877 	{ "MC_P_DEBUG_RPT", 0x413c4, 0 },
55878 	{ "MC_P_PHY_ADR_CK_EN", 0x413c8, 0 },
55879 	{ "MC_CE_ERR_ECC_DATA0", 0x413d0, 0 },
55880 	{ "MC_CE_ERR_ECC_DATA1", 0x413d4, 0 },
55881 	{ "MC_UE_ERR_ECC_DATA0", 0x413d8, 0 },
55882 	{ "MC_UE_ERR_ECC_DATA1", 0x413dc, 0 },
55883 	{ "MC_P_RMW_PRIO", 0x413f0, 0 },
55887 		{ "RD_MID_TH", 0, 8 },
55888 	{ "MC_P_BIST_CMD", 0x41400, 0 },
55892 		{ "BIST_OPCODE", 0, 2 },
55893 	{ "MC_P_BIST_CMD_ADDR", 0x41404, 0 },
55894 	{ "MC_P_BIST_CMD_LEN", 0x41408, 0 },
55895 	{ "MC_P_BIST_DATA_PATTERN", 0x4140c, 0 },
55896 	{ "MC_P_BIST_USER_WMASK0", 0x41414, 0 },
55897 	{ "MC_P_BIST_USER_WMASK1", 0x41418, 0 },
55898 	{ "MC_P_BIST_USER_WMASK2", 0x4141c, 0 },
55901 		{ "USER_MASK_ECC", 0, 8 },
55902 	{ "MC_P_BIST_NUM_ERR", 0x41480, 0 },
55903 	{ "MC_P_BIST_ERR_FIRST_ADDR", 0x41484, 0 },
55904 	{ "MC_P_BIST_STATUS_RDATA", 0x41488, 0 },
55905 	{ "MC_P_BIST_STATUS_RDATA", 0x4148c, 0 },
55906 	{ "MC_P_BIST_STATUS_RDATA", 0x41490, 0 },
55907 	{ "MC_P_BIST_STATUS_RDATA", 0x41494, 0 },
55908 	{ "MC_P_BIST_STATUS_RDATA", 0x41498, 0 },
55909 	{ "MC_P_BIST_STATUS_RDATA", 0x4149c, 0 },
55910 	{ "MC_P_BIST_STATUS_RDATA", 0x414a0, 0 },
55911 	{ "MC_P_BIST_STATUS_RDATA", 0x414a4, 0 },
55912 	{ "MC_P_BIST_STATUS_RDATA", 0x414a8, 0 },
55913 	{ "MC_P_BIST_STATUS_RDATA", 0x414ac, 0 },
55914 	{ "MC_P_BIST_STATUS_RDATA", 0x414b0, 0 },
55915 	{ "MC_P_BIST_STATUS_RDATA", 0x414b4, 0 },
55916 	{ "MC_P_BIST_STATUS_RDATA", 0x414b8, 0 },
55917 	{ "MC_P_BIST_STATUS_RDATA", 0x414bc, 0 },
55918 	{ "MC_P_BIST_STATUS_RDATA", 0x414c0, 0 },
55919 	{ "MC_P_BIST_STATUS_RDATA", 0x414c4, 0 },
55920 	{ "MC_P_BIST_STATUS_RDATA", 0x414c8, 0 },
55921 	{ "MC_P_BIST_STATUS_RDATA", 0x414cc, 0 },
55922 	{ "MC_P_BIST_CRC_SEED", 0x414d0, 0 },
55927 	{ "EDC_H_REF", 0x50000, 0 },
55937 		{ "RefFreq", 0, 16 },
55938 	{ "EDC_H_BIST_CMD", 0x50004, 0 },
55942 		{ "BIST_OPCODE", 0, 2 },
55943 	{ "EDC_H_BIST_CMD_ADDR", 0x50008, 0 },
55944 	{ "EDC_H_BIST_CMD_LEN", 0x5000c, 0 },
55945 	{ "EDC_H_BIST_DATA_PATTERN", 0x50010, 0 },
55946 	{ "EDC_H_BIST_USER_WDATA0", 0x50014, 0 },
55947 	{ "EDC_H_BIST_USER_WDATA1", 0x50018, 0 },
55948 	{ "EDC_H_BIST_USER_WDATA2", 0x5001c, 0 },
55950 		{ "USER_DATA2", 0, 8 },
55951 	{ "EDC_H_BIST_NUM_ERR", 0x50020, 0 },
55952 	{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50024, 0 },
55953 	{ "EDC_H_BIST_STATUS_RDATA", 0x50028, 0 },
55954 	{ "EDC_H_BIST_STATUS_RDATA", 0x5002c, 0 },
55955 	{ "EDC_H_BIST_STATUS_RDATA", 0x50030, 0 },
55956 	{ "EDC_H_BIST_STATUS_RDATA", 0x50034, 0 },
55957 	{ "EDC_H_BIST_STATUS_RDATA", 0x50038, 0 },
55958 	{ "EDC_H_BIST_STATUS_RDATA", 0x5003c, 0 },
55959 	{ "EDC_H_BIST_STATUS_RDATA", 0x50040, 0 },
55960 	{ "EDC_H_BIST_STATUS_RDATA", 0x50044, 0 },
55961 	{ "EDC_H_BIST_STATUS_RDATA", 0x50048, 0 },
55962 	{ "EDC_H_BIST_STATUS_RDATA", 0x5004c, 0 },
55963 	{ "EDC_H_BIST_STATUS_RDATA", 0x50050, 0 },
55964 	{ "EDC_H_BIST_STATUS_RDATA", 0x50054, 0 },
55965 	{ "EDC_H_BIST_STATUS_RDATA", 0x50058, 0 },
55966 	{ "EDC_H_BIST_STATUS_RDATA", 0x5005c, 0 },
55967 	{ "EDC_H_BIST_STATUS_RDATA", 0x50060, 0 },
55968 	{ "EDC_H_BIST_STATUS_RDATA", 0x50064, 0 },
55969 	{ "EDC_H_BIST_STATUS_RDATA", 0x50068, 0 },
55970 	{ "EDC_H_BIST_STATUS_RDATA", 0x5006c, 0 },
55971 	{ "EDC_H_PAR_ENABLE", 0x50070, 0 },
55974 		{ "PERR_PAR_ENABLE", 0, 1 },
55975 	{ "EDC_H_INT_ENABLE", 0x50074, 0 },
55978 		{ "PERR_INT_ENABLE", 0, 1 },
55979 	{ "EDC_H_INT_CAUSE", 0x50078, 0 },
55985 		{ "PERR_INT_CAUSE", 0, 1 },
55986 	{ "EDC_H_ECC_STATUS", 0x5007c, 0 },
55988 		{ "ECC_UECNT", 0, 16 },
55989 	{ "EDC_H_ECC_ERR_SEL", 0x50080, 0 },
55990 	{ "EDC_H_ECC_ERR_ADDR", 0x50084, 0 },
55991 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50090, 0 },
55992 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50094, 0 },
55993 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50098, 0 },
55994 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5009c, 0 },
55995 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a0, 0 },
55996 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a4, 0 },
55997 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a8, 0 },
55998 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500ac, 0 },
55999 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b0, 0 },
56000 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b4, 0 },
56001 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b8, 0 },
56002 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500bc, 0 },
56003 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c0, 0 },
56004 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c4, 0 },
56005 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c8, 0 },
56006 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500cc, 0 },
56007 	{ "EDC_H_DBG_MA_CMD_INTF", 0x50300, 0 },
56014 		{ "MCmdVld", 0, 1 },
56015 	{ "EDC_H_DBG_MA_WDATA_INTF", 0x50304, 0 },
56018 		{ "MWData", 0, 30 },
56019 	{ "EDC_H_DBG_MA_RDATA_INTF", 0x50308, 0 },
56022 		{ "MRspData", 0, 30 },
56023 	{ "EDC_H_DBG_BIST_CMD_INTF", 0x5030c, 0 },
56028 		{ "BCmdVld", 0, 1 },
56029 	{ "EDC_H_DBG_BIST_WDATA_INTF", 0x50310, 0 },
56032 		{ "BWData", 0, 30 },
56033 	{ "EDC_H_DBG_BIST_RDATA_INTF", 0x50314, 0 },
56036 		{ "BRspData", 0, 30 },
56037 	{ "EDC_H_DBG_EDRAM_CMD_INTF", 0x50318, 0 },
56045 		{ "Edram0RdEnLo", 0, 1 },
56046 	{ "EDC_H_DBG_EDRAM_WDATA_INTF", 0x5031c, 0 },
56048 		{ "EdramWByteEn", 0, 9 },
56049 	{ "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50320, 0 },
56050 	{ "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50324, 0 },
56051 	{ "EDC_H_DBG_MA_WR_REQ_CNT", 0x50328, 0 },
56052 	{ "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x5032c, 0 },
56053 	{ "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50330, 0 },
56054 	{ "EDC_H_DBG_MA_RD_REQ_CNT", 0x50334, 0 },
56055 	{ "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50338, 0 },
56056 	{ "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x5033c, 0 },
56057 	{ "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50340, 0 },
56058 	{ "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50344, 0 },
56059 	{ "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50348, 0 },
56060 	{ "EDC_H_DBG_BIST_RD_REQ_CNT", 0x5034c, 0 },
56061 	{ "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50350, 0 },
56062 	{ "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50354, 0 },
56063 	{ "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50358, 0 },
56064 	{ "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x5035c, 0 },
56065 	{ "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50360, 0 },
56066 	{ "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50364, 0 },
56067 	{ "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50368, 0 },
56068 	{ "EDC_H_DBG_EDRAM1_RMW_CNT", 0x5036c, 0 },
56069 	{ "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50370, 0 },
56070 	{ "EDC_H_DBG_FIFO_STATUS", 0x50374, 0 },
56084 		{ "stg_wrdq_notempty", 0, 1 },
56085 	{ "EDC_H_DBG_FSM_STATE", 0x50378, 0 },
56087 		{ "CmdFsm", 0, 3 },
56088 	{ "EDC_H_DBG_STALL_CYCLES", 0x5037c, 0 },
56108 		{ "dead_cycle1_post_ref_rmw", 0, 1 },
56109 	{ "EDC_H_DBG_CMD_QUEUE", 0x50380, 0 },
56114 		{ "ECmdAddr", 0, 22 },
56115 	{ "EDC_H_DBG_REFRESH", 0x50384, 0 },
56119 		{ "RefCnt", 0, 8 },
56120 	{ "EDC_H_BIST_CRC_SEED", 0x50400, 0 },
56125 	{ "EDC_H_REF", 0x50800, 0 },
56135 		{ "RefFreq", 0, 16 },
56136 	{ "EDC_H_BIST_CMD", 0x50804, 0 },
56140 		{ "BIST_OPCODE", 0, 2 },
56141 	{ "EDC_H_BIST_CMD_ADDR", 0x50808, 0 },
56142 	{ "EDC_H_BIST_CMD_LEN", 0x5080c, 0 },
56143 	{ "EDC_H_BIST_DATA_PATTERN", 0x50810, 0 },
56144 	{ "EDC_H_BIST_USER_WDATA0", 0x50814, 0 },
56145 	{ "EDC_H_BIST_USER_WDATA1", 0x50818, 0 },
56146 	{ "EDC_H_BIST_USER_WDATA2", 0x5081c, 0 },
56148 		{ "USER_DATA2", 0, 8 },
56149 	{ "EDC_H_BIST_NUM_ERR", 0x50820, 0 },
56150 	{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50824, 0 },
56151 	{ "EDC_H_BIST_STATUS_RDATA", 0x50828, 0 },
56152 	{ "EDC_H_BIST_STATUS_RDATA", 0x5082c, 0 },
56153 	{ "EDC_H_BIST_STATUS_RDATA", 0x50830, 0 },
56154 	{ "EDC_H_BIST_STATUS_RDATA", 0x50834, 0 },
56155 	{ "EDC_H_BIST_STATUS_RDATA", 0x50838, 0 },
56156 	{ "EDC_H_BIST_STATUS_RDATA", 0x5083c, 0 },
56157 	{ "EDC_H_BIST_STATUS_RDATA", 0x50840, 0 },
56158 	{ "EDC_H_BIST_STATUS_RDATA", 0x50844, 0 },
56159 	{ "EDC_H_BIST_STATUS_RDATA", 0x50848, 0 },
56160 	{ "EDC_H_BIST_STATUS_RDATA", 0x5084c, 0 },
56161 	{ "EDC_H_BIST_STATUS_RDATA", 0x50850, 0 },
56162 	{ "EDC_H_BIST_STATUS_RDATA", 0x50854, 0 },
56163 	{ "EDC_H_BIST_STATUS_RDATA", 0x50858, 0 },
56164 	{ "EDC_H_BIST_STATUS_RDATA", 0x5085c, 0 },
56165 	{ "EDC_H_BIST_STATUS_RDATA", 0x50860, 0 },
56166 	{ "EDC_H_BIST_STATUS_RDATA", 0x50864, 0 },
56167 	{ "EDC_H_BIST_STATUS_RDATA", 0x50868, 0 },
56168 	{ "EDC_H_BIST_STATUS_RDATA", 0x5086c, 0 },
56169 	{ "EDC_H_PAR_ENABLE", 0x50870, 0 },
56172 		{ "PERR_PAR_ENABLE", 0, 1 },
56173 	{ "EDC_H_INT_ENABLE", 0x50874, 0 },
56176 		{ "PERR_INT_ENABLE", 0, 1 },
56177 	{ "EDC_H_INT_CAUSE", 0x50878, 0 },
56183 		{ "PERR_INT_CAUSE", 0, 1 },
56184 	{ "EDC_H_ECC_STATUS", 0x5087c, 0 },
56186 		{ "ECC_UECNT", 0, 16 },
56187 	{ "EDC_H_ECC_ERR_SEL", 0x50880, 0 },
56188 	{ "EDC_H_ECC_ERR_ADDR", 0x50884, 0 },
56189 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50890, 0 },
56190 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50894, 0 },
56191 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50898, 0 },
56192 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5089c, 0 },
56193 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a0, 0 },
56194 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a4, 0 },
56195 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a8, 0 },
56196 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508ac, 0 },
56197 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b0, 0 },
56198 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b4, 0 },
56199 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b8, 0 },
56200 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508bc, 0 },
56201 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c0, 0 },
56202 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c4, 0 },
56203 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c8, 0 },
56204 	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508cc, 0 },
56205 	{ "EDC_H_DBG_MA_CMD_INTF", 0x50b00, 0 },
56212 		{ "MCmdVld", 0, 1 },
56213 	{ "EDC_H_DBG_MA_WDATA_INTF", 0x50b04, 0 },
56216 		{ "MWData", 0, 30 },
56217 	{ "EDC_H_DBG_MA_RDATA_INTF", 0x50b08, 0 },
56220 		{ "MRspData", 0, 30 },
56221 	{ "EDC_H_DBG_BIST_CMD_INTF", 0x50b0c, 0 },
56226 		{ "BCmdVld", 0, 1 },
56227 	{ "EDC_H_DBG_BIST_WDATA_INTF", 0x50b10, 0 },
56230 		{ "BWData", 0, 30 },
56231 	{ "EDC_H_DBG_BIST_RDATA_INTF", 0x50b14, 0 },
56234 		{ "BRspData", 0, 30 },
56235 	{ "EDC_H_DBG_EDRAM_CMD_INTF", 0x50b18, 0 },
56243 		{ "Edram0RdEnLo", 0, 1 },
56244 	{ "EDC_H_DBG_EDRAM_WDATA_INTF", 0x50b1c, 0 },
56246 		{ "EdramWByteEn", 0, 9 },
56247 	{ "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50b20, 0 },
56248 	{ "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50b24, 0 },
56249 	{ "EDC_H_DBG_MA_WR_REQ_CNT", 0x50b28, 0 },
56250 	{ "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x50b2c, 0 },
56251 	{ "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50b30, 0 },
56252 	{ "EDC_H_DBG_MA_RD_REQ_CNT", 0x50b34, 0 },
56253 	{ "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50b38, 0 },
56254 	{ "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x50b3c, 0 },
56255 	{ "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50b40, 0 },
56256 	{ "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50b44, 0 },
56257 	{ "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50b48, 0 },
56258 	{ "EDC_H_DBG_BIST_RD_REQ_CNT", 0x50b4c, 0 },
56259 	{ "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50b50, 0 },
56260 	{ "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50b54, 0 },
56261 	{ "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50b58, 0 },
56262 	{ "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x50b5c, 0 },
56263 	{ "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50b60, 0 },
56264 	{ "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50b64, 0 },
56265 	{ "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50b68, 0 },
56266 	{ "EDC_H_DBG_EDRAM1_RMW_CNT", 0x50b6c, 0 },
56267 	{ "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50b70, 0 },
56268 	{ "EDC_H_DBG_FIFO_STATUS", 0x50b74, 0 },
56282 		{ "stg_wrdq_notempty", 0, 1 },
56283 	{ "EDC_H_DBG_FSM_STATE", 0x50b78, 0 },
56285 		{ "CmdFsm", 0, 3 },
56286 	{ "EDC_H_DBG_STALL_CYCLES", 0x50b7c, 0 },
56306 		{ "dead_cycle1_post_ref_rmw", 0, 1 },
56307 	{ "EDC_H_DBG_CMD_QUEUE", 0x50b80, 0 },
56312 		{ "ECmdAddr", 0, 22 },
56313 	{ "EDC_H_DBG_REFRESH", 0x50b84, 0 },
56317 		{ "RefCnt", 0, 8 },
56318 	{ "EDC_H_BIST_CRC_SEED", 0x50c00, 0 },
56323 	{ "HMA_TABLE_ACCESS", 0x51000, 0 },
56326 		{ "L_SEL", 0, 4 },
56327 	{ "HMA_TABLE_LINE0", 0x51004, 0 },
56328 	{ "HMA_TABLE_LINE1", 0x51008, 0 },
56329 	{ "HMA_TABLE_LINE2", 0x5100c, 0 },
56330 	{ "HMA_TABLE_LINE3", 0x51010, 0 },
56331 	{ "HMA_TABLE_LINE4", 0x51014, 0 },
56332 	{ "HMA_TABLE_LINE5", 0x51018, 0 },
56338 		{ "DCA", 0, 11 },
56339 	{ "HMA_COOKIE", 0x5101c, 0 },
56343 		{ "C_SEL", 0, 4 },
56344 	{ "HMA_CFG", 0x51020, 0 },
56346 	{ "HMA_TLB_ACCESS", 0x51028, 0 },
56351 		{ "E_SEL", 0, 5 },
56352 	{ "HMA_TLB_BITS", 0x5102c, 0 },
56357 		{ "REGION", 0, 2 },
56358 	{ "HMA_TLB_DESC_0_H", 0x51030, 0 },
56359 	{ "HMA_TLB_DESC_0_L", 0x51034, 0 },
56360 	{ "HMA_TLB_DESC_1_H", 0x51038, 0 },
56361 	{ "HMA_TLB_DESC_1_L", 0x5103c, 0 },
56362 	{ "HMA_TLB_DESC_2_H", 0x51040, 0 },
56363 	{ "HMA_TLB_DESC_2_L", 0x51044, 0 },
56364 	{ "HMA_TLB_DESC_3_H", 0x51048, 0 },
56365 	{ "HMA_TLB_DESC_3_L", 0x5104c, 0 },
56366 	{ "HMA_TLB_DESC_4_H", 0x51050, 0 },
56367 	{ "HMA_TLB_DESC_4_L", 0x51054, 0 },
56368 	{ "HMA_TLB_DESC_5_H", 0x51058, 0 },
56369 	{ "HMA_TLB_DESC_5_L", 0x5105c, 0 },
56370 	{ "HMA_TLB_DESC_6_H", 0x51060, 0 },
56371 	{ "HMA_TLB_DESC_6_L", 0x51064, 0 },
56372 	{ "HMA_TLB_DESC_7_H", 0x51068, 0 },
56373 	{ "HMA_TLB_DESC_7_L", 0x5106c, 0 },
56374 	{ "HMA_REG0_MIN", 0x51070, 0 },
56376 	{ "HMA_REG0_MAX", 0x51074, 0 },
56378 	{ "HMA_REG0_MASK", 0x51078, 0 },
56380 	{ "HMA_REG0_BASE", 0x5107c, 0 },
56381 	{ "HMA_REG1_MIN", 0x51080, 0 },
56383 	{ "HMA_REG1_MAX", 0x51084, 0 },
56385 	{ "HMA_REG1_MASK", 0x51088, 0 },
56387 	{ "HMA_REG1_BASE", 0x5108c, 0 },
56388 	{ "HMA_REG2_MIN", 0x51090, 0 },
56390 	{ "HMA_REG2_MAX", 0x51094, 0 },
56392 	{ "HMA_REG2_MASK", 0x51098, 0 },
56394 	{ "HMA_REG2_BASE", 0x5109c, 0 },
56395 	{ "HMA_REG3_MIN", 0x510a0, 0 },
56397 	{ "HMA_REG3_MAX", 0x510a4, 0 },
56399 	{ "HMA_REG3_MASK", 0x510a8, 0 },
56401 	{ "HMA_REG3_BASE", 0x510ac, 0 },
56402 	{ "HMA_SW_SYNC", 0x510b0, 0 },
56405 	{ "HMA_PAR_ENABLE", 0x51300, 0 },
56406 	{ "HMA_INT_ENABLE", 0x51304, 0 },
56412 		{ "PERR_INT_ENABLE", 0, 1 },
56413 	{ "HMA_INT_CAUSE", 0x51308, 0 },
56419 		{ "PERR_INT_CAUSE", 0, 1 },
56420 	{ "HMA_MA_MST_ERR", 0x5130c, 0 },
56421 	{ "HMA_RTF_ERR", 0x51310, 0 },
56422 	{ "HMA_OTF_ERR", 0x51314, 0 },
56423 	{ "HMA_IDTF_ERR", 0x51318, 0 },
56424 	{ "HMA_EXIT_TF", 0x5131c, 0 },
56429 	{ "HMA_LOCAL_DEBUG_CFG", 0x51320, 0 },
56435 		{ "DEBUGSELL", 0, 5 },
56436 	{ "HMA_LOCAL_DEBUG_RPT", 0x51324, 0 },