354 	evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype);  in pci_xhci_set_evtrb()
610 	if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) {  in pci_xhci_trb_next()
756 	         evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3));  in pci_xhci_insert_event()
777 		if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) {  in pci_xhci_insert_event()
785 			errev.dwTrb3 = XHCI_TRB_3_TYPE_SET(  in pci_xhci_insert_event()
802 	evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT;  in pci_xhci_insert_event()
803 	evtrb->dwTrb3 |= rts->event_pcs;  in pci_xhci_insert_event()
1040 	if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) {  in pci_xhci_cmd_config_ep()
1154 	epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);  in pci_xhci_cmd_reset_ep()
1165 	type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);  in pci_xhci_cmd_reset_ep()
1168 	    (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) {  in pci_xhci_cmd_reset_ep()
1261 	         XHCI_TRB_3_SLOT_GET(trb->dwTrb3),  in pci_xhci_cmd_set_tr()
1262 	         XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1));  in pci_xhci_cmd_set_tr()
1264 	epid = XHCI_TRB_3_EP_GET(trb->dwTrb3);  in pci_xhci_cmd_set_tr()
1420 		type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1422 		if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) !=  in pci_xhci_complete_commands()
1428 		        type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3,  in pci_xhci_complete_commands()
1429 		        trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs));  in pci_xhci_complete_commands()
1433 		evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) |  in pci_xhci_complete_commands()
1439 			if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)  in pci_xhci_complete_commands()
1448 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1453 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1458 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1463 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1469 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1475 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1480 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1485 			slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3);  in pci_xhci_complete_commands()
1519 			evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot);  in pci_xhci_complete_commands()
1564 	type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3);  in pci_xhci_dump_trb()
1568 	         trb->qwTrb0, trb->dwTrb2, trb->dwTrb3));  in pci_xhci_dump_trb()
1602 		trbflags = trb->dwTrb3;  in pci_xhci_xfer_complete()
1609 		     trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0));  in pci_xhci_xfer_complete()
1619 		trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs);  in pci_xhci_xfer_complete()
1626 		if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) &&  in pci_xhci_xfer_complete()
1628 		      (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) {  in pci_xhci_xfer_complete()
1637 		evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) |  in pci_xhci_xfer_complete()
1645 			evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT;  in pci_xhci_xfer_complete()
1791 		trbflags = trb->dwTrb3;  in pci_xhci_handle_transfer()
1805 			if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT)  in pci_xhci_handle_transfer()
2031 		        trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));  in pci_xhci_device_doorbell()
2042 		        trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT));  in pci_xhci_device_doorbell()
2045 	if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) {  in pci_xhci_device_doorbell()