112 	struct ppt_cfg_io pi;  in passthru_read_config()  local
114 	pi.pci_off = reg;  in passthru_read_config()
115 	pi.pci_width = width;  in passthru_read_config()
117 	if (ioctl(sc->pptfd, PPT_CFG_READ, &pi) != 0) {  in passthru_read_config()
120 	return (pi.pci_data);  in passthru_read_config()
127 	struct ppt_cfg_io pi;  in passthru_write_config()  local
129 	pi.pci_off = reg;  in passthru_write_config()
130 	pi.pci_width = width;  in passthru_write_config()
131 	pi.pci_data = data;  in passthru_write_config()
133 	(void) ioctl(sc->pptfd, PPT_CFG_WRITE, &pi);  in passthru_write_config()
184 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)  in passthru_add_msicap()  argument
201 		pci_set_cfgdata8(pi, capoff + i, capdata[i]);  in passthru_add_msicap()
210 	struct pci_devinst *pi = sc->psc_pi;  in passthru_intr_limit()  local
229 			pci_set_cfgdata16(pi, off + 2, sc->psc_msi.msgctrl);  in passthru_intr_limit()
238 			pci_set_cfgdata16(pi, off + 2, msixcap->msgctrl);  in passthru_intr_limit()
248 	struct pci_devinst *pi = sc->psc_pi;  in cfginitmsi()  local
275 					pci_set_cfgdata32(pi, capptr, u32);  in cfginitmsi()
291 					pci_set_cfgdata32(pi, capptr, u32);  in cfginitmsi()
304 		pi->pi_msix.pba_bar =  in cfginitmsi()
306 		pi->pi_msix.pba_offset =  in cfginitmsi()
308 		pi->pi_msix.table_bar =  in cfginitmsi()
310 		pi->pi_msix.table_offset =  in cfginitmsi()
312 		pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);  in cfginitmsi()
313 		pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);  in cfginitmsi()
316 		table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;  in cfginitmsi()
317 		pi->pi_msix.table = calloc(1, table_size);  in cfginitmsi()
320 		for (i = 0; i < pi->pi_msix.table_count; i++) {  in cfginitmsi()
321 			pi->pi_msix.table[i].vector_control |=  in cfginitmsi()
335 		msiptr = passthru_add_msicap(pi, 1, origptr);  in cfginitmsi()
337 		sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);  in cfginitmsi()
339 		pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);  in cfginitmsi()
353 	struct pci_devinst *pi;  in msix_table_read()  local
364 	pi = sc->psc_pi;  in msix_table_read()
366 	table_offset = pi->pi_msix.table_offset;  in msix_table_read()
367 	table_count = pi->pi_msix.table_count;  in msix_table_read()
372 			src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_read()
376 			src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_read()
380 			src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_read()
384 			src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_read()
397 	entry = &pi->pi_msix.table[index];  in msix_table_read()
428 	struct pci_devinst *pi;  in msix_table_write()  local
438 	pi = sc->psc_pi;  in msix_table_write()
440 	table_offset = pi->pi_msix.table_offset;  in msix_table_write()
441 	table_count = pi->pi_msix.table_count;  in msix_table_write()
446 			dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_write()
450 			dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_write()
454 			dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_write()
458 			dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);  in msix_table_write()
469 	entry = &pi->pi_msix.table[index];  in msix_table_write()
480 	if (pi->pi_msix.enabled) {  in msix_table_write()
494 	struct pci_devinst *pi = sc->psc_pi;  in init_msix_table()  local
498 	i = pci_msix_table_bar(pi);  in init_msix_table()
521 	pi->pi_msix.mapped_size = sc->psc_bar[i].size;  in init_msix_table()
522 	pi->pi_msix.mapped_addr = (uint8_t *)mmap(NULL, pi->pi_msix.mapped_size,  in init_msix_table()
524 	if (pi->pi_msix.mapped_addr == MAP_FAILED) {  in init_msix_table()
529 	table_offset = rounddown2(pi->pi_msix.table_offset, 4096);  in init_msix_table()
531 	table_size = pi->pi_msix.table_offset - table_offset;  in init_msix_table()
532 	table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;  in init_msix_table()
541 		if (mprotect((caddr_t)pi->pi_msix.mapped_addr, table_offset,  in init_msix_table()
544 	if (table_offset + table_size != pi->pi_msix.mapped_size)  in init_msix_table()
546 		    pi->pi_msix.mapped_addr + table_offset + table_size,  in init_msix_table()
547 		    pi->pi_msix.mapped_size - (table_offset + table_size),  in init_msix_table()
557 	struct pci_devinst *pi = sc->psc_pi;  in cfginitbar()  local
588 		error = pci_emul_alloc_bar(pi, i, bartype, size);  in cfginitbar()
600 		pi->pi_bar[i].lobits = lobits;  in cfginitbar()
618 	struct pci_devinst *pi = sc->psc_pi;  in cfginit()  local
627 	cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);  in cfginit()
628 	intline = pci_get_cfgdata8(pi, PCIR_INTLINE);  in cfginit()
629 	intpin = pci_get_cfgdata8(pi, PCIR_INTPIN);  in cfginit()
632 		pci_set_cfgdata32(pi, i, read_config(&sc->psc_sel, i, 4));  in cfginit()
634 		pci_set_cfgdata32(pi, i, passthru_read_config(sc, i, 4));  in cfginit()
638 	pci_set_cfgdata16(pi, PCIR_COMMAND, cmd);  in cfginit()
639 	pci_set_cfgdata8(pi, PCIR_INTLINE, intline);  in cfginit()
640 	pci_set_cfgdata8(pi, PCIR_INTPIN, intpin);  in cfginit()
652 	if (pci_msix_table_bar(pi) >= 0) {  in cfginit()
771 passthru_init(struct pci_devinst *pi, nvlist_t *nvl)  in passthru_init()  argument
776 	struct vmctx *ctx = pi->pi_vmctx;  in passthru_init()
801 	pi->pi_arg = sc;  in passthru_init()
802 	sc->psc_pi = pi;  in passthru_init()
868     struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv)  in passthru_cfgread_default()
892 		    pci_get_cfgdata16(pi, PCIR_COMMAND);  in passthru_cfgread_default()
904     struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,  in passthru_cfgread_emulate()
911 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv)  in passthru_cfgread()  argument
915 	sc = pi->pi_arg;  in passthru_cfgread()
918 		return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv));  in passthru_cfgread()
920 	return (passthru_cfgread_default(sc, pi, coff, bytes, rv));  in passthru_cfgread()
924 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi,  in passthru_cfgwrite_default()  argument
929 	struct vmctx *ctx = pi->pi_vmctx;  in passthru_cfgwrite_default()
935 		pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,  in passthru_cfgwrite_default()
938 		    pi->pi_msi.addr, pi->pi_msi.msg_data, pi->pi_msi.maxmsgnum);  in passthru_cfgwrite_default()
945 		pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,  in passthru_cfgwrite_default()
947 		if (pi->pi_msix.enabled) {  in passthru_cfgwrite_default()
948 			msix_table_entries = pi->pi_msix.table_count;  in passthru_cfgwrite_default()
952 				    pi->pi_msix.table[i].addr,  in passthru_cfgwrite_default()
953 				    pi->pi_msix.table[i].msg_data,  in passthru_cfgwrite_default()
954 				    pi->pi_msix.table[i].vector_control);  in passthru_cfgwrite_default()
979 		cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);  in passthru_cfgwrite_default()
980 		pci_set_cfgdata16(pi, PCIR_COMMAND, val & 0xffff);  in passthru_cfgwrite_default()
981 		pci_emul_cmd_changed(pi, cmd_old);  in passthru_cfgwrite_default()
992     struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,  in passthru_cfgwrite_emulate()
999 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val)  in passthru_cfgwrite()  argument
1003 	sc = pi->pi_arg;  in passthru_cfgwrite()
1006 		return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val));  in passthru_cfgwrite()
1008 	return (passthru_cfgwrite_default(sc, pi, coff, bytes, val));  in passthru_cfgwrite()
1012 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,  in passthru_write()  argument
1015 	struct passthru_softc *sc = pi->pi_arg;  in passthru_write()
1016 	struct vmctx *ctx = pi->pi_vmctx;  in passthru_write()
1018 	if (baridx == pci_msix_table_bar(pi)) {  in passthru_write()
1023 		assert(pi->pi_bar[baridx].type == PCIBAR_IO);  in passthru_write()
1034 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)  in passthru_read()  argument
1036 	struct passthru_softc *sc = pi->pi_arg;  in passthru_read()
1039 	if (baridx == pci_msix_table_bar(pi)) {  in passthru_read()
1044 		assert(pi->pi_bar[baridx].type == PCIBAR_IO);  in passthru_read()
1060 passthru_msix_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,  in passthru_msix_addr()  argument
1067 	sc = pi->pi_arg;  in passthru_msix_addr()
1068 	table_offset = rounddown2(pi->pi_msix.table_offset, 4096);  in passthru_msix_addr()
1080 	table_size = pi->pi_msix.table_offset - table_offset;  in passthru_msix_addr()
1081 	table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;  in passthru_msix_addr()
1083 	remaining = pi->pi_bar[baridx].size - table_offset - table_size;  in passthru_msix_addr()
1100 passthru_mmio_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,  in passthru_mmio_addr()  argument
1105 	sc = pi->pi_arg;  in passthru_mmio_addr()
1118 passthru_addr_rom(struct pci_devinst *const pi, const int idx,  in passthru_addr_rom()  argument
1121 	const uint64_t addr = pi->pi_bar[idx].addr;  in passthru_addr_rom()
1122 	const uint64_t size = pi->pi_bar[idx].size;  in passthru_addr_rom()
1125 		if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) {  in passthru_addr_rom()
1131 		if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM,  in passthru_addr_rom()
1132 			pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) {  in passthru_addr_rom()
1140 passthru_addr(struct pci_devinst *pi, int baridx,  in passthru_addr()  argument
1143 	struct vmctx *ctx = pi->pi_vmctx;  in passthru_addr()
1145 	switch (pi->pi_bar[baridx].type) {  in passthru_addr()
1150 		passthru_addr_rom(pi, baridx, enabled);  in passthru_addr()
1154 		if (baridx == pci_msix_table_bar(pi))  in passthru_addr()
1155 			passthru_msix_addr(ctx, pi, baridx, enabled, address);  in passthru_addr()
1157 			passthru_mmio_addr(ctx, pi, baridx, enabled, address);  in passthru_addr()
1161 		    pi->pi_bar[baridx].type);  in passthru_addr()