401 	if (offset < pi->pi_msix.pba_offset)  in pci_valid_pba_offset()
404 	if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {  in pci_valid_pba_offset()
427 	if (tab_index >= pi->pi_msix.table_count)  in pci_emul_msix_twrite()
436 	dest = (char *)(pi->pi_msix.table + tab_index);  in pci_emul_msix_twrite()
472 	if (tab_index < pi->pi_msix.table_count) {  in pci_emul_msix_tread()
474 		dest = (char *)(pi->pi_msix.table + tab_index);  in pci_emul_msix_tread()
495 	if (pi->pi_msix.table != NULL)  in pci_msix_table_bar()
496 		return (pi->pi_msix.table_bar);  in pci_msix_table_bar()
505 	if (pi->pi_msix.table != NULL)  in pci_msix_pba_bar()
506 		return (pi->pi_msix.pba_bar);  in pci_msix_pba_bar()
1200 	pi->pi_msix.table = calloc(1, table_size);  in pci_msix_table_init()
1204 		pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;  in pci_msix_table_init()
1221 	pi->pi_msix.table_bar = barnum;  in pci_emul_add_msixcap()
1222 	pi->pi_msix.pba_bar   = barnum;  in pci_emul_add_msixcap()
1223 	pi->pi_msix.table_offset = 0;  in pci_emul_add_msixcap()
1224 	pi->pi_msix.table_count = msgnum;  in pci_emul_add_msixcap()
1225 	pi->pi_msix.pba_offset = tab_size;  in pci_emul_add_msixcap()
1226 	pi->pi_msix.pba_size = PBA_SIZE(msgnum);  in pci_emul_add_msixcap()
1234 				tab_size + pi->pi_msix.pba_size);  in pci_emul_add_msixcap()
1256 		pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;  in msixcap_cfgwrite()
1257 		pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;  in msixcap_cfgwrite()
1888 	return (pi->pi_msix.enabled && !pi->pi_msi.enabled);  in pci_msix_enabled()
1899 	if (pi->pi_msix.function_mask)  in pci_generate_msix()
1902 	if (index >= pi->pi_msix.table_count)  in pci_generate_msix()
1905 	mte = &pi->pi_msix.table[index];  in pci_generate_msix()
1928 	return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||  in pci_lintr_permitted()