415 	uint8_t	mask;  in vga_mem_wr_handler()  local
463 		mask = sc->vga_gc.gc_bit_mask;  in vga_mem_wr_handler()
470 			m0 = (set_reset & 1) ? mask : 0x00;  in vga_mem_wr_handler()
471 			m1 = (set_reset & 2) ? mask : 0x00;  in vga_mem_wr_handler()
472 			m2 = (set_reset & 4) ? mask : 0x00;  in vga_mem_wr_handler()
473 			m3 = (set_reset & 8) ? mask : 0x00;  in vga_mem_wr_handler()
475 			c0 = (enb_set_reset & 1) ? (c0 & ~mask) : (val & mask);  in vga_mem_wr_handler()
476 			c1 = (enb_set_reset & 2) ? (c1 & ~mask) : (val & mask);  in vga_mem_wr_handler()
477 			c2 = (enb_set_reset & 4) ? (c2 & ~mask) : (val & mask);  in vga_mem_wr_handler()
478 			c3 = (enb_set_reset & 8) ? (c3 & ~mask) : (val & mask);  in vga_mem_wr_handler()
486 			m0 = set_reset & 1 ? 0xff : ~mask;  in vga_mem_wr_handler()
487 			m1 = set_reset & 2 ? 0xff : ~mask;  in vga_mem_wr_handler()
488 			m2 = set_reset & 4 ? 0xff : ~mask;  in vga_mem_wr_handler()
489 			m3 = set_reset & 8 ? 0xff : ~mask;  in vga_mem_wr_handler()
497 			m0 = set_reset & 1 ? mask : 0x00;  in vga_mem_wr_handler()
498 			m1 = set_reset & 2 ? mask : 0x00;  in vga_mem_wr_handler()
499 			m2 = set_reset & 4 ? mask : 0x00;  in vga_mem_wr_handler()
500 			m3 = set_reset & 8 ? mask : 0x00;  in vga_mem_wr_handler()
508 			m0 = set_reset & 1 ? mask : 0x00;  in vga_mem_wr_handler()
509 			m1 = set_reset & 2 ? mask : 0x00;  in vga_mem_wr_handler()
510 			m2 = set_reset & 4 ? mask : 0x00;  in vga_mem_wr_handler()
511 			m3 = set_reset & 8 ? mask : 0x00;  in vga_mem_wr_handler()
525 		mask = sc->vga_gc.gc_bit_mask;  in vga_mem_wr_handler()
529 			m0 = (val & 1 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
530 			m1 = (val & 2 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
531 			m2 = (val & 4 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
532 			m3 = (val & 8 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
534 			c0 &= ~mask;  in vga_mem_wr_handler()
535 			c1 &= ~mask;  in vga_mem_wr_handler()
536 			c2 &= ~mask;  in vga_mem_wr_handler()
537 			c3 &= ~mask;  in vga_mem_wr_handler()
545 			m0 = (val & 1 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
546 			m1 = (val & 2 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
547 			m2 = (val & 4 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
548 			m3 = (val & 8 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
556 			m0 = (val & 1 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
557 			m1 = (val & 2 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
558 			m2 = (val & 4 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
559 			m3 = (val & 8 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
567 			m0 = (val & 1 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
568 			m1 = (val & 2 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
569 			m2 = (val & 4 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
570 			m3 = (val & 8 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
581 		mask = sc->vga_gc.gc_bit_mask & val;  in vga_mem_wr_handler()
588 			m0 = (set_reset & 1 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
589 			m1 = (set_reset & 2 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
590 			m2 = (set_reset & 4 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
591 			m3 = (set_reset & 8 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
593 			c0 &= ~mask;  in vga_mem_wr_handler()
594 			c1 &= ~mask;  in vga_mem_wr_handler()
595 			c2 &= ~mask;  in vga_mem_wr_handler()
596 			c3 &= ~mask;  in vga_mem_wr_handler()
604 			m0 = (set_reset & 1 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
605 			m1 = (set_reset & 2 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
606 			m2 = (set_reset & 4 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
607 			m3 = (set_reset & 8 ? 0xff : 0x00) | ~mask;  in vga_mem_wr_handler()
615 			m0 = (set_reset & 1 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
616 			m1 = (set_reset & 2 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
617 			m2 = (set_reset & 4 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
618 			m3 = (set_reset & 8 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
626 			m0 = (set_reset & 1 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
627 			m1 = (set_reset & 2 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
628 			m2 = (set_reset & 4 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()
629 			m3 = (set_reset & 8 ? 0xff : 0x00) & mask;  in vga_mem_wr_handler()