Lines Matching +full:trigger +full:- +full:address
3 * Module Name: dmtbinfo2 - Table info for non-AML tables
11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
157 /* This module used for application-level code only */
165 * - Add the C table definition to the actbl1.h or actbl2.h header.
166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below.
167 * - Define the table in this file (for the disassembler). If any
169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*)
171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData)
175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h
176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c
177 * - Create a template for the new table
178 * - Add data table compiler support
182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h
183 * - Add length and implementation cases in dmtable.c (disassembler)
184 * - Add type and length cases in dtutils.c (DT compiler)
194 * IORT - IO Remapping Table
302 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0},
343 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0},
349 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0},
364 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0},
367 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0},
374 * IVRS - I/O Virtualization Reporting Structure
403 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0},
416 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0},
428 /* 4-byte device entry */
436 /* 8-byte device entry */
447 /* 8-byte device entry */
456 /* 8-byte device entry */
470 * LPIT - Low Power Idle Table
492 /* 0: Native C-state */
496 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0},
507 * MADT - Multiple APIC Description Table and subtables
513 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0},
515 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0},
547 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0},
561 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
571 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
583 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
588 /* 5: Address Override */
593 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0},
604 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0},
629 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
658 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
674 …{ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mod…
675 …{ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mod…
678 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0},
679 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0},
680 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0},
681 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0},
683 … {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0},
696 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0},
709 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0},
722 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0},
733 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0},
741 * MCFG - PCI Memory Mapped Configuration table and Subtable
753 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0},
764 * MCHI - Management Controller Host Interface table
788 * MPST - Memory Power State Table
815 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0},
822 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */
831 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */
869 * MSCT - Maximum System Characteristics Table (ACPI 4.0)
878 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0},
882 /* Subtable - Maximum Proximity Domain Information. Version 1 */
898 * MTMR - MID Timer Table
907 /* MTMR Subtables - MTMR Entry */
920 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0)
939 /* 0: System Physical Address Range Structure */
949 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Address Range GUID", 0},
950 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0},
951 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0},
956 /* 1: Memory Device to System Address Range Map Structure */
967 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0},
1051 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0},
1055 /* 6: Flush Hint Address Structure */
1067 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL},
1086 * PCCT - Platform Communications Channel Table (ACPI 5.0)
1112 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0},
1113 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0},
1123 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */
1132 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0},
1133 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0},
1143 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */
1152 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0},
1153 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0},
1175 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0},
1176 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0},
1206 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0},
1207 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0},
1231 * PDTT - Platform Debug Trigger Table (ACPI 6.2)
1237 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0},
1247 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0},
1255 * PMTT - Platform Memory Topology Table
1273 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0},
1328 * PPTT - Processor Properties Topology Table (ACPI 6.2)
1332 /* Main table consists of only the standard ACPI header - subtables follow */
1405 * RASF - RAS Feature table
1418 * S3PT - S3 Performance Table
1461 * SBST - Smart Battery Specification Table
1476 * SDEI - Software Delegated Execption Interface Descriptor Table
1488 * SDEV - Secure Devices Table (ACPI 6.2)