Lines Matching +full:trigger +full:- +full:address

5 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
51   Get the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for
52   the legacy mode mask and the protected mode mask. The base address for the 8259
72   Get the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for
73   the legacy mode mask and the protected mode mask. The base address for the 8259
77   @param  LegacyMask            Bit 0 is Irq0 - Bit 15 is Irq15.
78   @param  LegacyEdgeLevel       Bit 0 is Irq0 - Bit 15 is Irq15.
79   @param  ProtectedMask         Bit 0 is Irq0 - Bit 15 is Irq15.
80   @param  ProtectedEdgeLevel    Bit 0 is Irq0 - Bit 15 is Irq15.
97   Set the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for
98   the legacy mode mask and the protected mode mask. The base address for the 8259
103   @param  LegacyMask            Bit 0 is Irq0 - Bit 15 is Irq15.
104   @param  LegacyEdgeLevel       Bit 0 is Irq0 - Bit 15 is Irq15.
105   @param  ProtectedMask         Bit 0 is Irq0 - Bit 15 is Irq15.
106   @param  ProtectedEdgeLevel    Bit 0 is Irq0 - Bit 15 is Irq15.
123   Set the 8259 mode of operation. The base address for the 8259 is different for
134   @param  EdgeLevel             Optional trigger mask for the new mode.
153   @param  Irq                   8259 IRQ0 - IRQ15.
172   @param  Irq                   8259 IRQ0 - IRQ15.
191   @param  Irq                   8259 IRQ0 - IRQ15.
230   @param  Irq                   8259 IRQ0 - IRQ15.
252   Gets IRQ and edge/level masks for 16-bit real mode and 32-bit protected mode.
255   Sets the IRQ and edge\level masks for 16-bit real mode and 32-bit protected mode.
258   Sets PIC mode to 16-bit real mode or 32-bit protected mode.