Lines Matching full:cap

53 	uint16_t cap, status;
55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
58 cap & PCIM_PCAP_SPEC,
59 cap & PCIM_PCAP_D1SUPP ? " D1" : "",
60 cap & PCIM_PCAP_D2SUPP ? " D2" : "",
312 printf(" Intel cap %d version %d", version >> 4, version & 0xf);
554 slot_power(uint32_t cap)
558 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7;
559 switch (cap & PCIEM_SLOT_CAP_SPLS) {
578 uint32_t cap;
619 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4);
623 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD));
624 if ((cap & PCIEM_CAP_FLR) != 0)
631 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4);
632 if ((cap & PCIEM_CAP2_ARI) != 0) {
641 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4);
643 if (cap == 0 && sta == 0)
647 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4);
648 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) {
651 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED));
653 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
656 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10));
658 if ((cap & PCIEM_LINK_CAP_CLOCK_PM) != 0) {
665 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4);
669 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19);
670 printf(" power limit %d mW", slot_power(cap));
671 if (cap & PCIEM_SLOT_CAP_HPC)
674 if (cap & PCIEM_SLOT_CAP_HPS)
676 if (cap & PCIEM_SLOT_CAP_APB)
678 if (cap & PCIEM_SLOT_CAP_PCP)
680 if (cap & PCIEM_SLOT_CAP_MRLSP)
683 if (cap & PCIEM_SLOT_CAP_EIP)
725 uint8_t cap;
727 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
729 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "",
730 cap & PCIM_PCIAFCAP_TP ? " TP" : "");
873 uint8_t ptr, cap;
898 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
899 printf(" cap %02x[%02x] = ", cap, ptr);
900 switch (cap) {
1134 check_avail_and_state(u_int cap, u_int capbit, u_int ctl, u_int ctlbit)
1137 if (cap & capbit)
1299 uint8_t ptr, cap;
1320 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
1321 if (cap == id)